dra76x.dtsi

  1// SPDX-License-Identifier: GPL-2.0-only
  2/*
  3 * Copyright (C) 2017 Texas Instruments Incorporated - https://www.ti.com/
  4 */
  5
  6#include "dra74x.dtsi"
  7
  8/ {
  9	compatible = "ti,dra762", "ti,dra7";
 10
 11	ocp {
 12		target-module@42c01900 {
 13			compatible = "ti,sysc-dra7-mcan", "ti,sysc";
 14			ranges = <0x0 0x42c00000 0x2000>;
 15			#address-cells = <1>;
 16			#size-cells = <1>;
 17			reg = <0x42c01900 0x4>,
 18			      <0x42c01904 0x4>,
 19			      <0x42c01908 0x4>;
 20			reg-names = "rev", "sysc", "syss";
 21			ti,sysc-mask = <(SYSC_OMAP4_SOFTRESET |
 22					 SYSC_DRA7_MCAN_ENAWAKEUP)>;
 23			ti,syss-mask = <1>;
 24			clocks = <&wkupaon_clkctrl DRA7_WKUPAON_ADC_CLKCTRL 0>;
 25			clock-names = "fck";
 26
 27			m_can0: mcan@1a00 {
 28				compatible = "bosch,m_can";
 29				reg = <0x1a00 0x4000>, <0x0 0x18FC>;
 30				reg-names = "m_can", "message_ram";
 31				interrupt-parent = <&gic>;
 32				interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
 33					     <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
 34				interrupt-names = "int0", "int1";
 35				clocks = <&l3_iclk_div>, <&mcan_clk>;
 36				clock-names = "hclk", "cclk";
 37				bosch,mram-cfg = <0x0 0 0 32 0 0 1 1>;
 38			};
 39		};
 40	};
 41
 42};
 43
 44&l4_per3 {
 45	target-module@1b0000 {			/* 0x489b0000, ap 25 34.0 */
 46		compatible = "ti,sysc-omap4", "ti,sysc";
 47		reg = <0x1b0000 0x4>,
 48		      <0x1b0010 0x4>;
 49		reg-names = "rev", "sysc";
 50		ti,sysc-midle = <SYSC_IDLE_FORCE>,
 51				<SYSC_IDLE_NO>;
 52		ti,sysc-sidle = <SYSC_IDLE_FORCE>,
 53				<SYSC_IDLE_NO>;
 54		clocks = <&cam_clkctrl DRA7_CAM_VIP3_CLKCTRL 0>;
 55		clock-names = "fck";
 56		#address-cells = <1>;
 57		#size-cells = <1>;
 58		ranges = <0x0 0x1b0000 0x10000>;
 59
 60		cal: cal@0 {
 61			compatible = "ti,dra76-cal";
 62			reg = <0x0000 0x400>,
 63			      <0x0800 0x40>,
 64			      <0x0900 0x40>;
 65			reg-names = "cal_top",
 66				    "cal_rx_core0",
 67				    "cal_rx_core1";
 68			interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
 69			ti,camerrx-control = <&scm_conf 0x6dc>;
 70
 71			ports {
 72				#address-cells = <1>;
 73				#size-cells = <0>;
 74
 75				csi2_0: port@0 {
 76					reg = <0>;
 77				};
 78				csi2_1: port@1 {
 79					reg = <1>;
 80				};
 81			};
 82		};
 83	};
 84};
 85
 86&scm_conf_clocks {
 87	/* CTRL_CORE_SMA_SW_0 */
 88	clock@3fc {
 89		compatible = "ti,clksel";
 90		reg = <0x3fc>;
 91		#clock-cells = <2>;
 92		#address-cells = <1>;
 93		#size-cells = <0>;
 94
 95		dpll_gmac_h14x2_ctrl_ck: clock@20 {
 96			reg = <20>;
 97			clock-output-names = "dpll_gmac_h14x2_ctrl_ck";
 98			compatible = "ti,divider-clock";
 99			clocks = <&dpll_gmac_x2_ck>;
100			ti,max-div = <63>;
101			ti,latch-bit = <26>;
102			assigned-clocks = <&dpll_gmac_h14x2_ctrl_ck>;
103			assigned-clock-rates = <80000000>;
104			#clock-cells = <0>;
105		};
106
107		mcan_clk: clock@27 {
108			reg = <27>;
109			clock-output-names = "mcan_clk";
110			compatible = "ti,gate-clock";
111			clocks = <&dpll_gmac_h14x2_ctrl_mux_ck>;
112			#clock-cells = <0>;
113		};
114
115		dpll_gmac_h14x2_ctrl_mux_ck: clock@29 {
116			reg = <29>;
117			clock-output-names = "dpll_gmac_h14x2_ctrl_mux_ck";
118			compatible = "ti,mux-clock";
119			clocks = <&dpll_gmac_ck>, <&dpll_gmac_h14x2_ctrl_ck>;
120			ti,latch-bit = <26>;
121			assigned-clocks = <&dpll_gmac_h14x2_ctrl_mux_ck>;
122			assigned-clock-parents = <&dpll_gmac_h14x2_ctrl_ck>;
123			#clock-cells = <0>;
124		};
125	};
126};
127
128&rtctarget {
129	status = "disabled";
130};
131
132&usb4_tm {
133	status = "disabled";
134};
135
136&mmc3 {
137	/* dra76x is not affected by i887 */
138	max-frequency = <96000000>;
139};
140
141&cpu0_opp_table {
142	opp-1800000000 {
143		/* OPP Plus */
144		opp-hz = /bits/ 64 <1800000000>;
145		opp-microvolt = <1250000 950000 1250000>,
146				<1250000 950000 1250000>;
147		opp-supported-hw = <0xFF 0x08>;
148	};
149};
150
151&opp_supply_mpu {
152	ti,efuse-settings = <
153	/* uV   offset */
154	1060000 0x0
155	1160000 0x4
156	1210000 0x8
157	1250000 0xC
158	>;
159};
160
161&abb_mpu {
162	ti,abb_info = <
163	/*uV		ABB	efuse	rbb_m fbb_m	vset_m*/
164	1060000		0	0x0	0 0x02000000 0x01F00000
165	1160000		0	0x4	0 0x02000000 0x01F00000
166	1210000		0	0x8	0 0x02000000 0x01F00000
167	1250000		0	0xC	0 0x02000000 0x01F00000
168	>;
169};