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dra7.dtsi
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linux-6.19.14/arch/arm/boot/dts/ti/omap/dra7.dtsi
1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com/ 4 * 5 * Based on "omap4.dtsi" 6 */ 7 8#include <dt-bindings/bus/ti-sysc.h> 9#include <dt-bindings/clock/dra7.h> 10#include <dt-bindings/interrupt-controller/arm-gic.h> 11#include <dt-bindings/pinctrl/dra.h> 12 13#define MAX_SOURCES 400 14 15/ { 16 #address-cells = <2>; 17 #size-cells = <2>; 18 19 compatible = "ti,dra7xx"; 20 interrupt-parent = <&crossbar_mpu>; 21 chosen { }; 22 23 aliases { 24 i2c0 = &i2c1; 25 i2c1 = &i2c2; 26 i2c2 = &i2c3; 27 i2c3 = &i2c4; 28 i2c4 = &i2c5; 29 serial0 = &uart1; 30 serial1 = &uart2; 31 serial2 = &uart3; 32 serial3 = &uart4; 33 serial4 = &uart5; 34 serial5 = &uart6; 35 serial6 = &uart7; 36 serial7 = &uart8; 37 serial8 = &uart9; 38 serial9 = &uart10; 39 ethernet0 = &cpsw_port1; 40 ethernet1 = &cpsw_port2; 41 d_can0 = &dcan1; 42 d_can1 = &dcan2; 43 spi0 = &qspi; 44 }; 45 46 timer { 47 compatible = "arm,armv7-timer"; 48 status = "disabled"; /* See ARM architected timer wrap erratum i940 */ 49 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, 50 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, 51 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, 52 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>; 53 interrupt-parent = <&gic>; 54 }; 55 56 gic: interrupt-controller@48211000 { 57 compatible = "arm,cortex-a15-gic"; 58 interrupt-controller; 59 #interrupt-cells = <3>; 60 reg = <0x0 0x48211000 0x0 0x1000>, 61 <0x0 0x48212000 0x0 0x2000>, 62 <0x0 0x48214000 0x0 0x2000>, 63 <0x0 0x48216000 0x0 0x2000>; 64 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>; 65 interrupt-parent = <&gic>; 66 }; 67 68 wakeupgen: interrupt-controller@48281000 { 69 compatible = "ti,omap5-wugen-mpu", "ti,omap4-wugen-mpu"; 70 interrupt-controller; 71 #interrupt-cells = <3>; 72 reg = <0x0 0x48281000 0x0 0x1000>; 73 interrupt-parent = <&gic>; 74 }; 75 76 cpus { 77 #address-cells = <1>; 78 #size-cells = <0>; 79 80 cpu0: cpu@0 { 81 device_type = "cpu"; 82 compatible = "arm,cortex-a15"; 83 reg = <0>; 84 85 operating-points-v2 = <&cpu0_opp_table>; 86 87 clocks = <&dpll_mpu_ck>; 88 clock-names = "cpu"; 89 90 clock-latency = <300000>; /* From omap-cpufreq driver */ 91 92 /* cooling options */ 93 #cooling-cells = <2>; /* min followed by max */ 94 95 vbb-supply = <&abb_mpu>; 96 }; 97 }; 98 99 cpu0_opp_table: opp-table { 100 compatible = "operating-points-v2-ti-cpu"; 101 syscon = <&scm_wkup>; 102 103 opp-1000000000 { 104 /* OPP NOM */ 105 opp-hz = /bits/ 64 <1000000000>; 106 opp-microvolt = <1060000 850000 1150000>, 107 <1060000 850000 1150000>; 108 opp-supported-hw = <0xFF 0x01>; 109 opp-suspend; 110 }; 111 112 opp-1176000000 { 113 /* OPP OD */ 114 opp-hz = /bits/ 64 <1176000000>; 115 opp-microvolt = <1160000 885000 1160000>, 116 <1160000 885000 1160000>; 117 118 opp-supported-hw = <0xFF 0x02>; 119 }; 120 121 opp-1500000000 { 122 /* OPP High */ 123 opp-hz = /bits/ 64 <1500000000>; 124 opp-microvolt = <1210000 950000 1250000>, 125 <1210000 950000 1250000>; 126 opp-supported-hw = <0xFF 0x04>; 127 }; 128 }; 129 130 /* 131 * XXX: Use a flat representation of the SOC interconnect. 132 * The real OMAP interconnect network is quite complex. 133 * Since it will not bring real advantage to represent that in DT for 134 * the moment, just use a fake OCP bus entry to represent the whole bus 135 * hierarchy. 136 */ 137 ocp: ocp { 138 compatible = "simple-pm-bus"; 139 power-domains = <&prm_core>; 140 clocks = <&l3main1_clkctrl DRA7_L3MAIN1_L3_MAIN_1_CLKCTRL 0>, 141 <&l3instr_clkctrl DRA7_L3INSTR_L3_MAIN_2_CLKCTRL 0>; 142 #address-cells = <1>; 143 #size-cells = <1>; 144 ranges = <0x0 0x0 0x0 0xc0000000>; 145 dma-ranges = <0x80000000 0x0 0x80000000 0x80000000>; 146 147 l3-noc@44000000 { 148 compatible = "ti,dra7-l3-noc"; 149 reg = <0x44000000 0x1000000>, 150 <0x45000000 0x1000>; 151 interrupts-extended = <&crossbar_mpu GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 152 <&wakeupgen GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 153 }; 154 155 l4_cfg: interconnect@4a000000 { 156 }; 157 l4_wkup: interconnect@4ae00000 { 158 }; 159 l4_per1: interconnect@48000000 { 160 }; 161 162 target-module@48210000 { 163 compatible = "ti,sysc-omap4-simple", "ti,sysc"; 164 power-domains = <&prm_mpu>; 165 clocks = <&mpu_clkctrl DRA7_MPU_MPU_CLKCTRL 0>; 166 clock-names = "fck"; 167 #address-cells = <1>; 168 #size-cells = <1>; 169 ranges = <0 0x48210000 0x1f0000>; 170 171 mpu { 172 compatible = "ti,omap5-mpu"; 173 }; 174 }; 175 176 l4_per2: interconnect@48400000 { 177 }; 178 l4_per3: interconnect@48800000 { 179 }; 180 181 /* 182 * Register access seems to have complex dependencies and also 183 * seems to need an enabled phy. See the TRM chapter for "Table 184 * 26-678. Main Sequence PCIe Controller Global Initialization" 185 * and also dra7xx_pcie_probe(). 186 */ 187 axi0: target-module@51000000 { 188 compatible = "ti,sysc-omap4", "ti,sysc"; 189 power-domains = <&prm_l3init>; 190 resets = <&prm_l3init 0>; 191 reset-names = "rstctrl"; 192 clocks = <&pcie_clkctrl DRA7_PCIE_PCIE1_CLKCTRL 0>, 193 <&pcie_clkctrl DRA7_PCIE_PCIE1_CLKCTRL 9>, 194 <&pcie_clkctrl DRA7_PCIE_PCIE1_CLKCTRL 10>; 195 clock-names = "fck", "phy-clk", "phy-clk-div"; 196 #size-cells = <1>; 197 #address-cells = <1>; 198 ranges = <0x51000000 0x51000000 0x3000 199 0x0 0x20000000 0x10000000>; 200 dma-ranges; 201 /** 202 * To enable PCI endpoint mode, disable the pcie1_rc 203 * node and enable pcie1_ep mode. 204 */ 205 pcie1_rc: pcie@51000000 { 206 reg = <0x51000000 0x2000>, <0x51002000 0x14c>, <0x1000 0x2000>; 207 reg-names = "rc_dbics", "ti_conf", "config"; 208 interrupts = <0 232 0x4>, <0 233 0x4>; 209 #address-cells = <3>; 210 #size-cells = <2>; 211 device_type = "pci"; 212 ranges = <0x81000000 0 0 0x03000 0 0x00010000 213 0x82000000 0 0x20013000 0x13000 0 0xffed000>; 214 bus-range = <0x00 0xff>; 215 #interrupt-cells = <1>; 216 num-lanes = <1>; 217 linux,pci-domain = <0>; 218 phys = <&pcie1_phy>; 219 phy-names = "pcie-phy0"; 220 ti,syscon-lane-sel = <&scm_conf_pcie 0x18>; 221 interrupt-map-mask = <0 0 0 7>; 222 interrupt-map = <0 0 0 1 &pcie1_intc 1>, 223 <0 0 0 2 &pcie1_intc 2>, 224 <0 0 0 3 &pcie1_intc 3>, 225 <0 0 0 4 &pcie1_intc 4>; 226 ti,syscon-unaligned-access = <&scm_conf1 0x14 1>; 227 status = "disabled"; 228 pcie1_intc: interrupt-controller { 229 interrupt-controller; 230 #address-cells = <0>; 231 #interrupt-cells = <1>; 232 }; 233 }; 234 235 pcie1_ep: pcie_ep@51000000 { 236 reg = <0x51000000 0x28>, <0x51002000 0x14c>, <0x51001000 0x28>, <0x1000 0x10000000>; 237 reg-names = "ep_dbics", "ti_conf", "ep_dbics2", "addr_space"; 238 interrupts = <0 232 0x4>; 239 num-lanes = <1>; 240 num-ib-windows = <4>; 241 num-ob-windows = <16>; 242 phys = <&pcie1_phy>; 243 phy-names = "pcie-phy0"; 244 ti,syscon-unaligned-access = <&scm_conf1 0x14 1>; 245 ti,syscon-lane-sel = <&scm_conf_pcie 0x18>; 246 status = "disabled"; 247 }; 248 }; 249 250 /* 251 * Register access seems to have complex dependencies and also 252 * seems to need an enabled phy. See the TRM chapter for "Table 253 * 26-678. Main Sequence PCIe Controller Global Initialization" 254 * and also dra7xx_pcie_probe(). 255 */ 256 axi1: target-module@51800000 { 257 compatible = "ti,sysc-omap4", "ti,sysc"; 258 clocks = <&pcie_clkctrl DRA7_PCIE_PCIE2_CLKCTRL 0>, 259 <&pcie_clkctrl DRA7_PCIE_PCIE2_CLKCTRL 9>, 260 <&pcie_clkctrl DRA7_PCIE_PCIE2_CLKCTRL 10>; 261 clock-names = "fck", "phy-clk", "phy-clk-div"; 262 power-domains = <&prm_l3init>; 263 resets = <&prm_l3init 1>; 264 reset-names = "rstctrl"; 265 #size-cells = <1>; 266 #address-cells = <1>; 267 ranges = <0x51800000 0x51800000 0x3000 268 0x0 0x30000000 0x10000000>; 269 dma-ranges; 270 status = "disabled"; 271 pcie2_rc: pcie@51800000 { 272 reg = <0x51800000 0x2000>, <0x51802000 0x14c>, <0x1000 0x2000>; 273 reg-names = "rc_dbics", "ti_conf", "config"; 274 interrupts = <0 355 0x4>, <0 356 0x4>; 275 #address-cells = <3>; 276 #size-cells = <2>; 277 device_type = "pci"; 278 ranges = <0x81000000 0 0 0x03000 0 0x00010000 279 0x82000000 0 0x30013000 0x13000 0 0xffed000>; 280 bus-range = <0x00 0xff>; 281 #interrupt-cells = <1>; 282 num-lanes = <1>; 283 linux,pci-domain = <1>; 284 phys = <&pcie2_phy>; 285 phy-names = "pcie-phy0"; 286 interrupt-map-mask = <0 0 0 7>; 287 interrupt-map = <0 0 0 1 &pcie2_intc 1>, 288 <0 0 0 2 &pcie2_intc 2>, 289 <0 0 0 3 &pcie2_intc 3>, 290 <0 0 0 4 &pcie2_intc 4>; 291 ti,syscon-unaligned-access = <&scm_conf1 0x14 2>; 292 pcie2_intc: interrupt-controller { 293 interrupt-controller; 294 #address-cells = <0>; 295 #interrupt-cells = <1>; 296 }; 297 }; 298 }; 299 300 ocmcram1: ocmcram@40300000 { 301 compatible = "mmio-sram"; 302 reg = <0x40300000 0x80000>; 303 ranges = <0x0 0x40300000 0x80000>; 304 #address-cells = <1>; 305 #size-cells = <1>; 306 /* 307 * This is a placeholder for an optional reserved 308 * region for use by secure software. The size 309 * of this region is not known until runtime so it 310 * is set as zero to either be updated to reserve 311 * space or left unchanged to leave all SRAM for use. 312 * On HS parts that that require the reserved region 313 * either the bootloader can update the size to 314 * the required amount or the node can be overridden 315 * from the board dts file for the secure platform. 316 */ 317 sram-hs@0 { 318 compatible = "ti,secure-ram"; 319 reg = <0x0 0x0>; 320 }; 321 }; 322 323 /* 324 * NOTE: ocmcram2 and ocmcram3 are not available on all 325 * DRA7xx and AM57xx variants. Confirm availability in 326 * the data manual for the exact part number in use 327 * before enabling these nodes in the board dts file. 328 */ 329 ocmcram2: ocmcram@40400000 { 330 status = "disabled"; 331 compatible = "mmio-sram"; 332 reg = <0x40400000 0x100000>; 333 ranges = <0x0 0x40400000 0x100000>; 334 #address-cells = <1>; 335 #size-cells = <1>; 336 }; 337 338 ocmcram3: ocmcram@40500000 { 339 status = "disabled"; 340 compatible = "mmio-sram"; 341 reg = <0x40500000 0x100000>; 342 ranges = <0x0 0x40500000 0x100000>; 343 #address-cells = <1>; 344 #size-cells = <1>; 345 }; 346 347 bandgap: bandgap@4a0021e0 { 348 reg = <0x4a0021e0 0xc 349 0x4a00232c 0xc 350 0x4a002380 0x2c 351 0x4a0023C0 0x3c 352 0x4a002564 0x8 353 0x4a002574 0x50>; 354 compatible = "ti,dra752-bandgap"; 355 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; 356 #thermal-sensor-cells = <1>; 357 }; 358 359 dsp1_system: dsp_system@40d00000 { 360 compatible = "syscon"; 361 reg = <0x40d00000 0x100>; 362 }; 363 364 dra7_iodelay_core: padconf@4844a000 { 365 compatible = "ti,dra7-iodelay"; 366 reg = <0x4844a000 0x0d1c>; 367 #address-cells = <1>; 368 #size-cells = <0>; 369 #pinctrl-cells = <2>; 370 }; 371 372 target-module@43300000 { 373 compatible = "ti,sysc-omap4", "ti,sysc"; 374 reg = <0x43300000 0x4>, 375 <0x43300010 0x4>; 376 reg-names = "rev", "sysc"; 377 ti,sysc-midle = <SYSC_IDLE_FORCE>, 378 <SYSC_IDLE_NO>, 379 <SYSC_IDLE_SMART>; 380 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 381 <SYSC_IDLE_NO>, 382 <SYSC_IDLE_SMART>; 383 clocks = <&l3main1_clkctrl DRA7_L3MAIN1_TPCC_CLKCTRL 0>; 384 clock-names = "fck"; 385 #address-cells = <1>; 386 #size-cells = <1>; 387 ranges = <0x0 0x43300000 0x100000>; 388 389 edma: dma@0 { 390 compatible = "ti,edma3-tpcc"; 391 reg = <0 0x100000>; 392 reg-names = "edma3_cc"; 393 interrupts = <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>, 394 <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>, 395 <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>; 396 interrupt-names = "edma3_ccint", "edma3_mperr", 397 "edma3_ccerrint"; 398 dma-requests = <64>; 399 #dma-cells = <2>; 400 401 ti,tptcs = <&edma_tptc0 7>, <&edma_tptc1 0>; 402 403 /* 404 * memcpy is disabled, can be enabled with: 405 * ti,edma-memcpy-channels = <20 21>; 406 * for example. Note that these channels need to be 407 * masked in the xbar as well. 408 */ 409 }; 410 }; 411 412 target-module@43400000 { 413 compatible = "ti,sysc-omap4", "ti,sysc"; 414 reg = <0x43400000 0x4>, 415 <0x43400010 0x4>; 416 reg-names = "rev", "sysc"; 417 ti,sysc-midle = <SYSC_IDLE_FORCE>, 418 <SYSC_IDLE_NO>, 419 <SYSC_IDLE_SMART>; 420 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 421 <SYSC_IDLE_NO>, 422 <SYSC_IDLE_SMART>; 423 clocks = <&l3main1_clkctrl DRA7_L3MAIN1_TPTC0_CLKCTRL 0>; 424 clock-names = "fck"; 425 #address-cells = <1>; 426 #size-cells = <1>; 427 ranges = <0x0 0x43400000 0x100000>; 428 429 edma_tptc0: dma@0 { 430 compatible = "ti,edma3-tptc"; 431 reg = <0 0x100000>; 432 interrupts = <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>; 433 interrupt-names = "edma3_tcerrint"; 434 }; 435 }; 436 437 target-module@43500000 { 438 compatible = "ti,sysc-omap4", "ti,sysc"; 439 reg = <0x43500000 0x4>, 440 <0x43500010 0x4>; 441 reg-names = "rev", "sysc"; 442 ti,sysc-midle = <SYSC_IDLE_FORCE>, 443 <SYSC_IDLE_NO>, 444 <SYSC_IDLE_SMART>; 445 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 446 <SYSC_IDLE_NO>, 447 <SYSC_IDLE_SMART>; 448 clocks = <&l3main1_clkctrl DRA7_L3MAIN1_TPTC1_CLKCTRL 0>; 449 clock-names = "fck"; 450 #address-cells = <1>; 451 #size-cells = <1>; 452 ranges = <0x0 0x43500000 0x100000>; 453 454 edma_tptc1: dma@0 { 455 compatible = "ti,edma3-tptc"; 456 reg = <0 0x100000>; 457 interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>; 458 interrupt-names = "edma3_tcerrint"; 459 }; 460 }; 461 462 target-module@4e000000 { 463 compatible = "ti,sysc-omap2", "ti,sysc"; 464 reg = <0x4e000000 0x4>, 465 <0x4e000010 0x4>; 466 reg-names = "rev", "sysc"; 467 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 468 <SYSC_IDLE_NO>, 469 <SYSC_IDLE_SMART>; 470 ranges = <0x0 0x4e000000 0x2000000>; 471 #size-cells = <1>; 472 #address-cells = <1>; 473 474 dmm@0 { 475 compatible = "ti,omap5-dmm"; 476 reg = <0 0x800>; 477 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 478 }; 479 }; 480 481 ipu1: ipu@58820000 { 482 compatible = "ti,dra7-ipu"; 483 reg = <0x58820000 0x10000>; 484 reg-names = "l2ram"; 485 iommus = <&mmu_ipu1>; 486 status = "disabled"; 487 resets = <&prm_ipu 0>, <&prm_ipu 1>; 488 clocks = <&ipu1_clkctrl DRA7_IPU1_MMU_IPU1_CLKCTRL 0>; 489 firmware-name = "dra7-ipu1-fw.xem4"; 490 }; 491 492 ipu2: ipu@55020000 { 493 compatible = "ti,dra7-ipu"; 494 reg = <0x55020000 0x10000>; 495 reg-names = "l2ram"; 496 iommus = <&mmu_ipu2>; 497 status = "disabled"; 498 resets = <&prm_core 0>, <&prm_core 1>; 499 clocks = <&ipu2_clkctrl DRA7_IPU2_MMU_IPU2_CLKCTRL 0>; 500 firmware-name = "dra7-ipu2-fw.xem4"; 501 }; 502 503 dsp1: dsp@40800000 { 504 compatible = "ti,dra7-dsp"; 505 reg = <0x40800000 0x48000>, 506 <0x40e00000 0x8000>, 507 <0x40f00000 0x8000>; 508 reg-names = "l2ram", "l1pram", "l1dram"; 509 ti,bootreg = <&scm_conf 0x55c 10>; 510 iommus = <&mmu0_dsp1>, <&mmu1_dsp1>; 511 status = "disabled"; 512 resets = <&prm_dsp1 0>; 513 clocks = <&dsp1_clkctrl DRA7_DSP1_MMU0_DSP1_CLKCTRL 0>; 514 firmware-name = "dra7-dsp1-fw.xe66"; 515 }; 516 517 target-module@40d01000 { 518 compatible = "ti,sysc-omap2", "ti,sysc"; 519 reg = <0x40d01000 0x4>, 520 <0x40d01010 0x4>, 521 <0x40d01014 0x4>; 522 reg-names = "rev", "sysc", "syss"; 523 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 524 <SYSC_IDLE_NO>, 525 <SYSC_IDLE_SMART>; 526 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | 527 SYSC_OMAP2_SOFTRESET | 528 SYSC_OMAP2_AUTOIDLE)>; 529 clocks = <&dsp1_clkctrl DRA7_DSP1_MMU0_DSP1_CLKCTRL 0>; 530 clock-names = "fck"; 531 resets = <&prm_dsp1 1>; 532 reset-names = "rstctrl"; 533 ranges = <0x0 0x40d01000 0x1000>; 534 #size-cells = <1>; 535 #address-cells = <1>; 536 537 mmu0_dsp1: mmu@0 { 538 compatible = "ti,dra7-dsp-iommu"; 539 reg = <0x0 0x100>; 540 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 541 #iommu-cells = <0>; 542 ti,syscon-mmuconfig = <&dsp1_system 0x0>; 543 }; 544 }; 545 546 target-module@40d02000 { 547 compatible = "ti,sysc-omap2", "ti,sysc"; 548 reg = <0x40d02000 0x4>, 549 <0x40d02010 0x4>, 550 <0x40d02014 0x4>; 551 reg-names = "rev", "sysc", "syss"; 552 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 553 <SYSC_IDLE_NO>, 554 <SYSC_IDLE_SMART>; 555 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | 556 SYSC_OMAP2_SOFTRESET | 557 SYSC_OMAP2_AUTOIDLE)>; 558 clocks = <&dsp1_clkctrl DRA7_DSP1_MMU0_DSP1_CLKCTRL 0>; 559 clock-names = "fck"; 560 resets = <&prm_dsp1 1>; 561 reset-names = "rstctrl"; 562 ranges = <0x0 0x40d02000 0x1000>; 563 #size-cells = <1>; 564 #address-cells = <1>; 565 566 mmu1_dsp1: mmu@0 { 567 compatible = "ti,dra7-dsp-iommu"; 568 reg = <0x0 0x100>; 569 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>; 570 #iommu-cells = <0>; 571 ti,syscon-mmuconfig = <&dsp1_system 0x1>; 572 }; 573 }; 574 575 target-module@58882000 { 576 compatible = "ti,sysc-omap2", "ti,sysc"; 577 reg = <0x58882000 0x4>, 578 <0x58882010 0x4>, 579 <0x58882014 0x4>; 580 reg-names = "rev", "sysc", "syss"; 581 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 582 <SYSC_IDLE_NO>, 583 <SYSC_IDLE_SMART>; 584 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | 585 SYSC_OMAP2_SOFTRESET | 586 SYSC_OMAP2_AUTOIDLE)>; 587 clocks = <&ipu1_clkctrl DRA7_IPU1_MMU_IPU1_CLKCTRL 0>; 588 clock-names = "fck"; 589 resets = <&prm_ipu 2>; 590 reset-names = "rstctrl"; 591 #address-cells = <1>; 592 #size-cells = <1>; 593 ranges = <0x0 0x58882000 0x100>; 594 595 mmu_ipu1: mmu@0 { 596 compatible = "ti,dra7-iommu"; 597 reg = <0x0 0x100>; 598 interrupts = <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>; 599 #iommu-cells = <0>; 600 ti,iommu-bus-err-back; 601 }; 602 }; 603 604 target-module@55082000 { 605 compatible = "ti,sysc-omap2", "ti,sysc"; 606 reg = <0x55082000 0x4>, 607 <0x55082010 0x4>, 608 <0x55082014 0x4>; 609 reg-names = "rev", "sysc", "syss"; 610 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 611 <SYSC_IDLE_NO>, 612 <SYSC_IDLE_SMART>; 613 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | 614 SYSC_OMAP2_SOFTRESET | 615 SYSC_OMAP2_AUTOIDLE)>; 616 clocks = <&ipu2_clkctrl DRA7_IPU2_MMU_IPU2_CLKCTRL 0>; 617 clock-names = "fck"; 618 resets = <&prm_core 2>; 619 reset-names = "rstctrl"; 620 #address-cells = <1>; 621 #size-cells = <1>; 622 ranges = <0x0 0x55082000 0x100>; 623 624 mmu_ipu2: mmu@0 { 625 compatible = "ti,dra7-iommu"; 626 reg = <0x0 0x100>; 627 interrupts = <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>; 628 #iommu-cells = <0>; 629 ti,iommu-bus-err-back; 630 }; 631 }; 632 633 abb_mpu: regulator-abb-mpu@4ae07ddc { 634 compatible = "ti,abb-v3"; 635 regulator-name = "abb_mpu"; 636 #address-cells = <0>; 637 #size-cells = <0>; 638 clocks = <&sys_clkin1>; 639 ti,settling-time = <50>; 640 ti,clock-cycles = <16>; 641 642 reg = <0x4ae07ddc 0x4>, <0x4ae07de0 0x4>, 643 <0x4ae06014 0x4>, <0x4a003b20 0xc>, 644 <0x4ae0c158 0x4>; 645 reg-names = "setup-address", "control-address", 646 "int-address", "efuse-address", 647 "ldo-address"; 648 ti,tranxdone-status-mask = <0x80>; 649 /* LDOVBBMPU_FBB_MUX_CTRL */ 650 ti,ldovbb-override-mask = <0x400>; 651 /* LDOVBBMPU_FBB_VSET_OUT */ 652 ti,ldovbb-vset-mask = <0x1F>; 653 654 /* 655 * NOTE: only FBB mode used but actual vset will 656 * determine final biasing 657 */ 658 ti,abb_info = < 659 /*uV ABB efuse rbb_m fbb_m vset_m*/ 660 1060000 0 0x0 0 0x02000000 0x01F00000 661 1160000 0 0x4 0 0x02000000 0x01F00000 662 1210000 0 0x8 0 0x02000000 0x01F00000 663 >; 664 }; 665 666 abb_ivahd: regulator-abb-ivahd@4ae07e34 { 667 compatible = "ti,abb-v3"; 668 regulator-name = "abb_ivahd"; 669 #address-cells = <0>; 670 #size-cells = <0>; 671 clocks = <&sys_clkin1>; 672 ti,settling-time = <50>; 673 ti,clock-cycles = <16>; 674 675 reg = <0x4ae07e34 0x4>, <0x4ae07e24 0x4>, 676 <0x4ae06010 0x4>, <0x4a0025cc 0xc>, 677 <0x4a002470 0x4>; 678 reg-names = "setup-address", "control-address", 679 "int-address", "efuse-address", 680 "ldo-address"; 681 ti,tranxdone-status-mask = <0x40000000>; 682 /* LDOVBBIVA_FBB_MUX_CTRL */ 683 ti,ldovbb-override-mask = <0x400>; 684 /* LDOVBBIVA_FBB_VSET_OUT */ 685 ti,ldovbb-vset-mask = <0x1F>; 686 687 /* 688 * NOTE: only FBB mode used but actual vset will 689 * determine final biasing 690 */ 691 ti,abb_info = < 692 /*uV ABB efuse rbb_m fbb_m vset_m*/ 693 1055000 0 0x0 0 0x02000000 0x01F00000 694 1150000 0 0x4 0 0x02000000 0x01F00000 695 1250000 0 0x8 0 0x02000000 0x01F00000 696 >; 697 }; 698 699 abb_dspeve: regulator-abb-dspeve@4ae07e30 { 700 compatible = "ti,abb-v3"; 701 regulator-name = "abb_dspeve"; 702 #address-cells = <0>; 703 #size-cells = <0>; 704 clocks = <&sys_clkin1>; 705 ti,settling-time = <50>; 706 ti,clock-cycles = <16>; 707 708 reg = <0x4ae07e30 0x4>, <0x4ae07e20 0x4>, 709 <0x4ae06010 0x4>, <0x4a0025e0 0xc>, 710 <0x4a00246c 0x4>; 711 reg-names = "setup-address", "control-address", 712 "int-address", "efuse-address", 713 "ldo-address"; 714 ti,tranxdone-status-mask = <0x20000000>; 715 /* LDOVBBDSPEVE_FBB_MUX_CTRL */ 716 ti,ldovbb-override-mask = <0x400>; 717 /* LDOVBBDSPEVE_FBB_VSET_OUT */ 718 ti,ldovbb-vset-mask = <0x1F>; 719 720 /* 721 * NOTE: only FBB mode used but actual vset will 722 * determine final biasing 723 */ 724 ti,abb_info = < 725 /*uV ABB efuse rbb_m fbb_m vset_m*/ 726 1055000 0 0x0 0 0x02000000 0x01F00000 727 1150000 0 0x4 0 0x02000000 0x01F00000 728 1250000 0 0x8 0 0x02000000 0x01F00000 729 >; 730 }; 731 732 abb_gpu: regulator-abb-gpu@4ae07de4 { 733 compatible = "ti,abb-v3"; 734 regulator-name = "abb_gpu"; 735 #address-cells = <0>; 736 #size-cells = <0>; 737 clocks = <&sys_clkin1>; 738 ti,settling-time = <50>; 739 ti,clock-cycles = <16>; 740 741 reg = <0x4ae07de4 0x4>, <0x4ae07de8 0x4>, 742 <0x4ae06010 0x4>, <0x4a003b08 0xc>, 743 <0x4ae0c154 0x4>; 744 reg-names = "setup-address", "control-address", 745 "int-address", "efuse-address", 746 "ldo-address"; 747 ti,tranxdone-status-mask = <0x10000000>; 748 /* LDOVBBGPU_FBB_MUX_CTRL */ 749 ti,ldovbb-override-mask = <0x400>; 750 /* LDOVBBGPU_FBB_VSET_OUT */ 751 ti,ldovbb-vset-mask = <0x1F>; 752 753 /* 754 * NOTE: only FBB mode used but actual vset will 755 * determine final biasing 756 */ 757 ti,abb_info = < 758 /*uV ABB efuse rbb_m fbb_m vset_m*/ 759 1090000 0 0x0 0 0x02000000 0x01F00000 760 1210000 0 0x4 0 0x02000000 0x01F00000 761 1280000 0 0x8 0 0x02000000 0x01F00000 762 >; 763 }; 764 765 target-module@4b300000 { 766 compatible = "ti,sysc-omap4", "ti,sysc"; 767 reg = <0x4b300000 0x4>, 768 <0x4b300010 0x4>; 769 reg-names = "rev", "sysc"; 770 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 771 <SYSC_IDLE_NO>, 772 <SYSC_IDLE_SMART>, 773 <SYSC_IDLE_SMART_WKUP>; 774 clocks = <&l4per2_clkctrl DRA7_L4PER2_QSPI_CLKCTRL 0>; 775 clock-names = "fck"; 776 #address-cells = <1>; 777 #size-cells = <1>; 778 ranges = <0x0 0x4b300000 0x1000>, 779 <0x5c000000 0x5c000000 0x4000000>; 780 781 qspi: spi@0 { 782 compatible = "ti,dra7xxx-qspi"; 783 reg = <0 0x100>, 784 <0x5c000000 0x4000000>; 785 reg-names = "qspi_base", "qspi_mmap"; 786 syscon-chipselects = <&scm_conf 0x558>; 787 #address-cells = <1>; 788 #size-cells = <0>; 789 clocks = <&l4per2_clkctrl DRA7_L4PER2_QSPI_CLKCTRL 25>; 790 clock-names = "fck"; 791 num-cs = <4>; 792 interrupts = <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>; 793 status = "disabled"; 794 }; 795 }; 796 797 /* OCP2SCP1 */ 798 /* IRQ for DWC3_3 and DWC3_4 need IRQ crossbar */ 799 800 target-module@50000000 { 801 compatible = "ti,sysc-omap2", "ti,sysc"; 802 reg = <0x50000000 4>, 803 <0x50000010 4>, 804 <0x50000014 4>; 805 reg-names = "rev", "sysc", "syss"; 806 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 807 <SYSC_IDLE_NO>, 808 <SYSC_IDLE_SMART>; 809 ti,syss-mask = <1>; 810 clocks = <&l3main1_clkctrl DRA7_L3MAIN1_GPMC_CLKCTRL 0>; 811 clock-names = "fck"; 812 #address-cells = <1>; 813 #size-cells = <1>; 814 ranges = <0x50000000 0x50000000 0x00001000>, /* regs */ 815 <0x00000000 0x00000000 0x40000000>; /* data */ 816 817 gpmc: gpmc@50000000 { 818 compatible = "ti,am3352-gpmc"; 819 reg = <0x50000000 0x37c>; /* device IO registers */ 820 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 821 dmas = <&edma_xbar 4 0>; 822 dma-names = "rxtx"; 823 gpmc,num-cs = <8>; 824 gpmc,num-waitpins = <2>; 825 #address-cells = <2>; 826 #size-cells = <1>; 827 interrupt-controller; 828 #interrupt-cells = <2>; 829 gpio-controller; 830 #gpio-cells = <2>; 831 status = "disabled"; 832 }; 833 }; 834 835 target-module@56000000 { 836 compatible = "ti,sysc-omap4", "ti,sysc"; 837 reg = <0x5600fe00 0x4>, 838 <0x5600fe10 0x4>; 839 reg-names = "rev", "sysc"; 840 ti,sysc-midle = <SYSC_IDLE_FORCE>, 841 <SYSC_IDLE_NO>, 842 <SYSC_IDLE_SMART>; 843 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 844 <SYSC_IDLE_NO>, 845 <SYSC_IDLE_SMART>, 846 <SYSC_IDLE_SMART_WKUP>; 847 clocks = <&gpu_clkctrl DRA7_GPU_CLKCTRL 0>; 848 clock-names = "fck"; 849 #address-cells = <1>; 850 #size-cells = <1>; 851 ranges = <0 0x56000000 0x2000000>; 852 853 gpu@0 { 854 compatible = "ti,am5728-gpu", "img,powervr-sgx544"; 855 reg = <0x0 0x10000>; /* 64kB */ 856 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 857 }; 858 }; 859 860 crossbar_mpu: crossbar@4a002a48 { 861 compatible = "ti,irq-crossbar"; 862 reg = <0x4a002a48 0x130>; 863 interrupt-controller; 864 interrupt-parent = <&wakeupgen>; 865 #interrupt-cells = <3>; 866 ti,max-irqs = <160>; 867 ti,max-crossbar-sources = <MAX_SOURCES>; 868 ti,reg-size = <2>; 869 ti,irqs-reserved = <0 1 2 3 5 6 131 132>; 870 ti,irqs-skip = <10 133 139 140>; 871 ti,irqs-safe-map = <0>; 872 }; 873 874 target-module@58000000 { 875 compatible = "ti,sysc-omap2", "ti,sysc"; 876 reg = <0x58000000 4>, 877 <0x58000014 4>; 878 reg-names = "rev", "syss"; 879 ti,syss-mask = <1>; 880 clocks = <&dss_clkctrl DRA7_DSS_DSS_CORE_CLKCTRL 0>, 881 <&dss_clkctrl DRA7_DSS_DSS_CORE_CLKCTRL 9>, 882 <&dss_clkctrl DRA7_DSS_DSS_CORE_CLKCTRL 10>, 883 <&dss_clkctrl DRA7_DSS_DSS_CORE_CLKCTRL 11>; 884 clock-names = "fck", "hdmi_clk", "sys_clk", "tv_clk"; 885 #address-cells = <1>; 886 #size-cells = <1>; 887 ranges = <0 0x58000000 0x800000>; 888 889 dss: dss@0 { 890 compatible = "ti,dra7-dss"; 891 /* 'reg' defined in dra72x.dtsi and dra74x.dtsi */ 892 /* 'clocks' defined in dra72x.dtsi and dra74x.dtsi */ 893 status = "disabled"; 894 /* CTRL_CORE_DSS_PLL_CONTROL */ 895 syscon-pll-ctrl = <&scm_conf 0x538>; 896 #address-cells = <1>; 897 #size-cells = <1>; 898 ranges = <0 0 0x800000>; 899 900 target-module@1000 { 901 compatible = "ti,sysc-omap2", "ti,sysc"; 902 reg = <0x1000 0x4>, 903 <0x1010 0x4>, 904 <0x1014 0x4>; 905 reg-names = "rev", "sysc", "syss"; 906 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 907 <SYSC_IDLE_NO>, 908 <SYSC_IDLE_SMART>; 909 ti,sysc-midle = <SYSC_IDLE_FORCE>, 910 <SYSC_IDLE_NO>, 911 <SYSC_IDLE_SMART>; 912 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | 913 SYSC_OMAP2_ENAWAKEUP | 914 SYSC_OMAP2_SOFTRESET | 915 SYSC_OMAP2_AUTOIDLE)>; 916 ti,syss-mask = <1>; 917 clocks = <&dss_clkctrl DRA7_DSS_DSS_CORE_CLKCTRL 8>; 918 clock-names = "fck"; 919 #address-cells = <1>; 920 #size-cells = <1>; 921 ranges = <0 0x1000 0x1000>; 922 923 dispc@0 { 924 compatible = "ti,dra7-dispc"; 925 reg = <0 0x1000>; 926 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 927 clocks = <&dss_clkctrl DRA7_DSS_DSS_CORE_CLKCTRL 8>; 928 clock-names = "fck"; 929 /* CTRL_CORE_SMA_SW_1 */ 930 syscon-pol = <&scm_conf 0x534>; 931 }; 932 }; 933 934 target-module@40000 { 935 compatible = "ti,sysc-omap4", "ti,sysc"; 936 reg = <0x40000 0x4>, 937 <0x40010 0x4>; 938 reg-names = "rev", "sysc"; 939 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 940 <SYSC_IDLE_NO>, 941 <SYSC_IDLE_SMART>, 942 <SYSC_IDLE_SMART_WKUP>; 943 ti,sysc-mask = <(SYSC_OMAP4_SOFTRESET)>; 944 clocks = <&dss_clkctrl DRA7_DSS_DSS_CORE_CLKCTRL 9>, 945 <&dss_clkctrl DRA7_DSS_DSS_CORE_CLKCTRL 8>; 946 clock-names = "fck", "dss_clk"; 947 #address-cells = <1>; 948 #size-cells = <1>; 949 ranges = <0 0x40000 0x40000>; 950 951 hdmi: encoder@0 { 952 compatible = "ti,dra7-hdmi"; 953 reg = <0 0x200>, 954 <0x200 0x80>, 955 <0x300 0x80>, 956 <0x20000 0x19000>; 957 reg-names = "wp", "pll", "phy", "core"; 958 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 959 status = "disabled"; 960 clocks = <&dss_clkctrl DRA7_DSS_DSS_CORE_CLKCTRL 9>, 961 <&dss_clkctrl DRA7_DSS_DSS_CORE_CLKCTRL 10>; 962 clock-names = "fck", "sys_clk"; 963 dmas = <&sdma_xbar 76>; 964 dma-names = "audio_tx"; 965 }; 966 }; 967 }; 968 }; 969 970 target-module@59000000 { 971 compatible = "ti,sysc-omap4", "ti,sysc"; 972 reg = <0x59000020 0x4>; 973 reg-names = "rev"; 974 clocks = <&dss_clkctrl DRA7_DSS_BB2D_CLKCTRL 0>; 975 clock-names = "fck"; 976 #address-cells = <1>; 977 #size-cells = <1>; 978 ranges = <0x0 0x59000000 0x1000>; 979 980 bb2d: gpu@0 { 981 compatible = "vivante,gc"; 982 reg = <0x0 0x700>; 983 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; 984 clocks = <&dss_clkctrl DRA7_DSS_BB2D_CLKCTRL 0>; 985 clock-names = "core"; 986 }; 987 }; 988 989 aes1_target: target-module@4b500000 { 990 compatible = "ti,sysc-omap2", "ti,sysc"; 991 reg = <0x4b500080 0x4>, 992 <0x4b500084 0x4>, 993 <0x4b500088 0x4>; 994 reg-names = "rev", "sysc", "syss"; 995 ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET | 996 SYSC_OMAP2_AUTOIDLE)>; 997 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 998 <SYSC_IDLE_NO>, 999 <SYSC_IDLE_SMART>, 1000 <SYSC_IDLE_SMART_WKUP>; 1001 ti,syss-mask = <1>; 1002 /* Domains (P, C): per_pwrdm, l4sec_clkdm */ 1003 clocks = <&l4sec_clkctrl DRA7_L4SEC_AES1_CLKCTRL 0>; 1004 clock-names = "fck"; 1005 #address-cells = <1>; 1006 #size-cells = <1>; 1007 ranges = <0x0 0x4b500000 0x1000>; 1008 1009 aes1: aes@0 { 1010 compatible = "ti,omap4-aes"; 1011 reg = <0 0xa0>; 1012 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; 1013 dmas = <&edma_xbar 111 0>, <&edma_xbar 110 0>; 1014 dma-names = "tx", "rx"; 1015 clocks = <&l3_iclk_div>; 1016 clock-names = "fck"; 1017 }; 1018 }; 1019 1020 aes2_target: target-module@4b700000 { 1021 compatible = "ti,sysc-omap2", "ti,sysc"; 1022 reg = <0x4b700080 0x4>, 1023 <0x4b700084 0x4>, 1024 <0x4b700088 0x4>; 1025 reg-names = "rev", "sysc", "syss"; 1026 ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET | 1027 SYSC_OMAP2_AUTOIDLE)>; 1028 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 1029 <SYSC_IDLE_NO>, 1030 <SYSC_IDLE_SMART>, 1031 <SYSC_IDLE_SMART_WKUP>; 1032 ti,syss-mask = <1>; 1033 /* Domains (P, C): per_pwrdm, l4sec_clkdm */ 1034 clocks = <&l4sec_clkctrl DRA7_L4SEC_AES2_CLKCTRL 0>; 1035 clock-names = "fck"; 1036 #address-cells = <1>; 1037 #size-cells = <1>; 1038 ranges = <0x0 0x4b700000 0x1000>; 1039 1040 aes2: aes@0 { 1041 compatible = "ti,omap4-aes"; 1042 reg = <0 0xa0>; 1043 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; 1044 dmas = <&edma_xbar 114 0>, <&edma_xbar 113 0>; 1045 dma-names = "tx", "rx"; 1046 clocks = <&l3_iclk_div>; 1047 clock-names = "fck"; 1048 }; 1049 }; 1050 1051 sham1_target: target-module@4b101000 { 1052 compatible = "ti,sysc-omap3-sham", "ti,sysc"; 1053 reg = <0x4b101100 0x4>, 1054 <0x4b101110 0x4>, 1055 <0x4b101114 0x4>; 1056 reg-names = "rev", "sysc", "syss"; 1057 ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET | 1058 SYSC_OMAP2_AUTOIDLE)>; 1059 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 1060 <SYSC_IDLE_NO>, 1061 <SYSC_IDLE_SMART>; 1062 ti,syss-mask = <1>; 1063 /* Domains (P, C): l4per_pwrdm, l4sec_clkdm */ 1064 clocks = <&l4sec_clkctrl DRA7_L4SEC_SHAM_CLKCTRL 0>; 1065 clock-names = "fck"; 1066 #address-cells = <1>; 1067 #size-cells = <1>; 1068 ranges = <0x0 0x4b101000 0x1000>; 1069 1070 sham1: sham@0 { 1071 compatible = "ti,omap5-sham"; 1072 reg = <0 0x300>; 1073 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; 1074 dmas = <&edma_xbar 119 0>; 1075 dma-names = "rx"; 1076 clocks = <&l3_iclk_div>; 1077 clock-names = "fck"; 1078 }; 1079 }; 1080 1081 sham2_target: target-module@42701000 { 1082 compatible = "ti,sysc-omap3-sham", "ti,sysc"; 1083 reg = <0x42701100 0x4>, 1084 <0x42701110 0x4>, 1085 <0x42701114 0x4>; 1086 reg-names = "rev", "sysc", "syss"; 1087 ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET | 1088 SYSC_OMAP2_AUTOIDLE)>; 1089 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 1090 <SYSC_IDLE_NO>, 1091 <SYSC_IDLE_SMART>; 1092 ti,syss-mask = <1>; 1093 /* Domains (P, C): l4per_pwrdm, l4sec_clkdm */ 1094 clocks = <&l4sec_clkctrl DRA7_L4SEC_SHAM2_CLKCTRL 0>; 1095 clock-names = "fck"; 1096 #address-cells = <1>; 1097 #size-cells = <1>; 1098 ranges = <0x0 0x42701000 0x1000>; 1099 1100 sham2: sham@0 { 1101 compatible = "ti,omap5-sham"; 1102 reg = <0 0x300>; 1103 interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>; 1104 dmas = <&edma_xbar 165 0>; 1105 dma-names = "rx"; 1106 clocks = <&l3_iclk_div>; 1107 clock-names = "fck"; 1108 }; 1109 }; 1110 1111 iva_hd_target: target-module@5a000000 { 1112 compatible = "ti,sysc-omap4", "ti,sysc"; 1113 reg = <0x5a05a400 0x4>, 1114 <0x5a05a410 0x4>; 1115 reg-names = "rev", "sysc"; 1116 ti,sysc-midle = <SYSC_IDLE_FORCE>, 1117 <SYSC_IDLE_NO>, 1118 <SYSC_IDLE_SMART>; 1119 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 1120 <SYSC_IDLE_NO>, 1121 <SYSC_IDLE_SMART>; 1122 power-domains = <&prm_iva>; 1123 resets = <&prm_iva 2>; 1124 reset-names = "rstctrl"; 1125 clocks = <&iva_clkctrl DRA7_IVA_CLKCTRL 0>; 1126 clock-names = "fck"; 1127 #address-cells = <1>; 1128 #size-cells = <1>; 1129 ranges = <0x5a000000 0x5a000000 0x1000000>, 1130 <0x5b000000 0x5b000000 0x1000000>; 1131 1132 iva { 1133 compatible = "ti,ivahd"; 1134 }; 1135 }; 1136 1137 opp_supply_mpu: opp-supply@4a003b20 { 1138 compatible = "ti,omap5-opp-supply"; 1139 reg = <0x4a003b20 0xc>; 1140 ti,efuse-settings = < 1141 /* uV offset */ 1142 1060000 0x0 1143 1160000 0x4 1144 1210000 0x8 1145 >; 1146 ti,absolute-max-voltage-uv = <1500000>; 1147 }; 1148 1149 }; 1150 1151 thermal_zones: thermal-zones { 1152 #include "omap4-cpu-thermal.dtsi" 1153 #include "omap5-gpu-thermal.dtsi" 1154 #include "omap5-core-thermal.dtsi" 1155 #include "dra7-dspeve-thermal.dtsi" 1156 #include "dra7-iva-thermal.dtsi" 1157 }; 1158 1159}; 1160 1161&cpu_thermal { 1162 polling-delay = <500>; /* milliseconds */ 1163 coefficients = <0 2000>; 1164}; 1165 1166&gpu_thermal { 1167 coefficients = <0 2000>; 1168}; 1169 1170&core_thermal { 1171 coefficients = <0 2000>; 1172}; 1173 1174&dspeve_thermal { 1175 coefficients = <0 2000>; 1176}; 1177 1178&iva_thermal { 1179 coefficients = <0 2000>; 1180}; 1181 1182&cpu_crit { 1183 temperature = <120000>; /* milli Celsius */ 1184}; 1185 1186&core_crit { 1187 temperature = <120000>; /* milli Celsius */ 1188}; 1189 1190&gpu_crit { 1191 temperature = <120000>; /* milli Celsius */ 1192}; 1193 1194&dspeve_crit { 1195 temperature = <120000>; /* milli Celsius */ 1196}; 1197 1198&iva_crit { 1199 temperature = <120000>; /* milli Celsius */ 1200}; 1201 1202#include "dra7-l4.dtsi" 1203#include "dra7xx-clocks.dtsi" 1204 1205&prm { 1206 prm_mpu: prm@300 { 1207 compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst"; 1208 reg = <0x300 0x100>; 1209 #power-domain-cells = <0>; 1210 }; 1211 1212 prm_dsp1: prm@400 { 1213 compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst"; 1214 reg = <0x400 0x100>; 1215 #reset-cells = <1>; 1216 #power-domain-cells = <0>; 1217 }; 1218 1219 prm_ipu: prm@500 { 1220 compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst"; 1221 reg = <0x500 0x100>; 1222 #reset-cells = <1>; 1223 #power-domain-cells = <0>; 1224 }; 1225 1226 prm_coreaon: prm@628 { 1227 compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst"; 1228 reg = <0x628 0xd8>; 1229 #power-domain-cells = <0>; 1230 }; 1231 1232 prm_core: prm@700 { 1233 compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst"; 1234 reg = <0x700 0x100>; 1235 #reset-cells = <1>; 1236 #power-domain-cells = <0>; 1237 }; 1238 1239 prm_iva: prm@f00 { 1240 compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst"; 1241 reg = <0xf00 0x100>; 1242 #reset-cells = <1>; 1243 #power-domain-cells = <0>; 1244 }; 1245 1246 prm_cam: prm@1000 { 1247 compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst"; 1248 reg = <0x1000 0x100>; 1249 #power-domain-cells = <0>; 1250 }; 1251 1252 prm_dss: prm@1100 { 1253 compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst"; 1254 reg = <0x1100 0x100>; 1255 #power-domain-cells = <0>; 1256 }; 1257 1258 prm_gpu: prm@1200 { 1259 compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst"; 1260 reg = <0x1200 0x100>; 1261 #power-domain-cells = <0>; 1262 }; 1263 1264 prm_l3init: prm@1300 { 1265 compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst"; 1266 reg = <0x1300 0x100>; 1267 #reset-cells = <1>; 1268 #power-domain-cells = <0>; 1269 }; 1270 1271 prm_l4per: prm@1400 { 1272 compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst"; 1273 reg = <0x1400 0x100>; 1274 #power-domain-cells = <0>; 1275 }; 1276 1277 prm_custefuse: prm@1600 { 1278 compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst"; 1279 reg = <0x1600 0x100>; 1280 #power-domain-cells = <0>; 1281 }; 1282 1283 prm_wkupaon: prm@1724 { 1284 compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst"; 1285 reg = <0x1724 0x100>; 1286 #power-domain-cells = <0>; 1287 }; 1288 1289 prm_dsp2: prm@1b00 { 1290 compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst"; 1291 reg = <0x1b00 0x40>; 1292 #reset-cells = <1>; 1293 #power-domain-cells = <0>; 1294 }; 1295 1296 prm_eve1: prm@1b40 { 1297 compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst"; 1298 reg = <0x1b40 0x40>; 1299 #power-domain-cells = <0>; 1300 }; 1301 1302 prm_eve2: prm@1b80 { 1303 compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst"; 1304 reg = <0x1b80 0x40>; 1305 #power-domain-cells = <0>; 1306 }; 1307 1308 prm_eve3: prm@1bc0 { 1309 compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst"; 1310 reg = <0x1bc0 0x40>; 1311 #power-domain-cells = <0>; 1312 }; 1313 1314 prm_eve4: prm@1c00 { 1315 compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst"; 1316 reg = <0x1c00 0x60>; 1317 #power-domain-cells = <0>; 1318 }; 1319 1320 prm_rtc: prm@1c60 { 1321 compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst"; 1322 reg = <0x1c60 0x20>; 1323 #power-domain-cells = <0>; 1324 }; 1325 1326 prm_vpe: prm@1c80 { 1327 compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst"; 1328 reg = <0x1c80 0x80>; 1329 #power-domain-cells = <0>; 1330 }; 1331}; 1332 1333/* Preferred always-on timer for clockevent */ 1334&timer1_target { 1335 ti,no-reset-on-init; 1336 ti,no-idle; 1337 timer@0 { 1338 assigned-clocks = <&wkupaon_clkctrl DRA7_WKUPAON_TIMER1_CLKCTRL 24>; 1339 assigned-clock-parents = <&sys_32k_ck>; 1340 }; 1341}; 1342 1343/* Local timers, see ARM architected timer wrap erratum i940 */ 1344&timer15_target { 1345 ti,no-reset-on-init; 1346 ti,no-idle; 1347 timer@0 { 1348 assigned-clocks = <&l4per3_clkctrl DRA7_L4PER3_TIMER15_CLKCTRL 24>; 1349 assigned-clock-parents = <&timer_sys_clk_div>; 1350 }; 1351}; 1352 1353&timer16_target { 1354 ti,no-reset-on-init; 1355 ti,no-idle; 1356 timer@0 { 1357 assigned-clocks = <&l4per3_clkctrl DRA7_L4PER3_TIMER16_CLKCTRL 24>; 1358 assigned-clock-parents = <&timer_sys_clk_div>; 1359 }; 1360};
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