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am335x-myirtech-myc.dtsi

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linux-6.19.14/arch/arm/boot/dts/ti/omap/am335x-myirtech-myc.dtsi DEVICETREE 
  1// SPDX-License-Identifier: GPL-2.0-or-later
  2/* SPDX-FileCopyrightText: Alexander Shiyan, <shc_work@mail.ru> */
  3
  4/* Based on code by myc_c335x.dts, MYiRtech.com */
  5/* Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/ */
  6
  7/dts-v1/;
  8
  9#include "am33xx.dtsi"
 10
 11#include <dt-bindings/interrupt-controller/irq.h>
 12#include <dt-bindings/leds/common.h>
 13
 14/ {
 15	model = "MYIR MYC-AM335X";
 16	compatible = "myir,myc-am335x", "ti,am33xx";
 17
 18	cpus {
 19		cpu@0 {
 20			cpu0-supply = <&vdd_core>;
 21			voltage-tolerance = <2>;
 22		};
 23	};
 24
 25	memory@80000000 {
 26		device_type = "memory";
 27		reg = <0x80000000 0x10000000>;
 28	};
 29
 30	clk32k: clk32k {
 31		compatible = "fixed-clock";
 32		clock-frequency = <32768>;
 33
 34		#clock-cells = <0>;
 35	};
 36
 37	vdd_mod: vdd_mod_reg {
 38		compatible = "regulator-fixed";
 39		regulator-name = "vdd-mod";
 40		regulator-always-on;
 41		regulator-boot-on;
 42	};
 43
 44	vdd_core: vdd_core_reg {
 45		compatible = "regulator-fixed";
 46		regulator-name = "vdd-core";
 47		regulator-always-on;
 48		regulator-boot-on;
 49		vin-supply = <&vdd_mod>;
 50	};
 51
 52	leds: leds {
 53		compatible = "gpio-leds";
 54		pinctrl-names = "default";
 55		pinctrl-0 = <&led_mod_pins>;
 56
 57		led_mod: led_mod {
 58			label = "module:user";
 59			gpios = <&gpio3 18 GPIO_ACTIVE_LOW>;
 60			color = <LED_COLOR_ID_GREEN>;
 61			default-state = "off";
 62			panic-indicator;
 63		};
 64	};
 65};
 66
 67&mac_sw {
 68	pinctrl-names = "default", "sleep";
 69	pinctrl-0 = <&eth_slave1_pins_default>;
 70	pinctrl-1 = <&eth_slave1_pins_sleep>;
 71	status = "okay";
 72};
 73
 74&cpsw_port1 {
 75	phy-handle = <&phy0>;
 76	phy-mode = "rgmii-id";
 77	ti,dual-emac-pvid = <1>;
 78};
 79
 80&cpsw_port2 {
 81	status = "disabled";
 82};
 83
 84&davinci_mdio_sw {
 85	pinctrl-names = "default", "sleep";
 86	pinctrl-0 = <&mdio_pins_default>;
 87	pinctrl-1 = <&mdio_pins_sleep>;
 88
 89	phy0: ethernet-phy@4 {
 90		reg = <4>;
 91	};
 92};
 93
 94&elm {
 95	status = "okay";
 96};
 97
 98&gpmc {
 99	pinctrl-names = "default", "sleep";
100	pinctrl-0 = <&nand_pins_default>;
101	pinctrl-1 = <&nand_pins_sleep>;
102	ranges = <0 0 0x8000000 0x1000000>;
103	status = "okay";
104
105	nand0: nand@0,0 {
106		compatible = "ti,omap2-nand";
107		reg = <0 0 4>;
108		interrupt-parent = <&gpmc>;
109		interrupts = <0 IRQ_TYPE_NONE>, <1 IRQ_TYPE_NONE>;
110		nand-bus-width = <8>;
111		rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>;
112		gpmc,device-width = <1>;
113		gpmc,sync-clk-ps = <0>;
114		gpmc,cs-on-ns = <0>;
115		gpmc,cs-rd-off-ns = <44>;
116		gpmc,cs-wr-off-ns = <44>;
117		gpmc,adv-on-ns = <6>;
118		gpmc,adv-rd-off-ns = <34>;
119		gpmc,adv-wr-off-ns = <44>;
120		gpmc,we-on-ns = <0>;
121		gpmc,we-off-ns = <40>;
122		gpmc,oe-on-ns = <0>;
123		gpmc,oe-off-ns = <54>;
124		gpmc,access-ns = <64>;
125		gpmc,rd-cycle-ns = <82>;
126		gpmc,wr-cycle-ns = <82>;
127		gpmc,bus-turnaround-ns = <0>;
128		gpmc,cycle2cycle-delay-ns = <0>;
129		gpmc,clk-activation-ns = <0>;
130		gpmc,wait-pin = <0>;
131		gpmc,wr-access-ns = <40>;
132		gpmc,wr-data-mux-bus-ns = <0>;
133		ti,elm-id = <&elm>;
134		ti,nand-ecc-opt = "bch8";
135	};
136};
137
138&i2c0 {
139	pinctrl-names = "default", "gpio", "sleep";
140	pinctrl-0 = <&i2c0_pins_default>;
141	pinctrl-1 = <&i2c0_pins_gpio>;
142	pinctrl-2 = <&i2c0_pins_sleep>;
143	clock-frequency = <400000>;
144	scl-gpios = <&gpio3 6 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
145	sda-gpios = <&gpio3 5 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
146	status = "okay";
147
148	eeprom: eeprom@50 {
149		compatible = "atmel,24c32";
150		reg = <0x50>;
151		pagesize = <32>;
152		vcc-supply = <&vdd_mod>;
153	};
154};
155
156&rtc {
157	clocks = <&clk32k>;
158	clock-names = "ext-clk";
159	system-power-controller;
160};
161
162&am33xx_pinmux {
163	mdio_pins_default: mdio-default-pins {
164		pinctrl-single,pins = <
165			AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLUP | SLEWCTRL_FAST, MUX_MODE0)	/* mdio_data */
166			AM33XX_PADCONF(AM335X_PIN_MDC, PIN_OUTPUT_PULLUP, MUX_MODE0)			/* mdio_clk */
167		>;
168	};
169
170	mdio_pins_sleep: mdio-sleep-pins {
171		pinctrl-single,pins = <
172			AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLDOWN, MUX_MODE7)
173			AM33XX_PADCONF(AM335X_PIN_MDC, PIN_INPUT_PULLDOWN, MUX_MODE7)
174		>;
175	};
176
177	eth_slave1_pins_default: eth-slave1-default-pins {
178		pinctrl-single,pins = <
179			AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_OUTPUT_PULLDOWN, MUX_MODE2)		/* rgmii1_tctl */
180			AM33XX_PADCONF(AM335X_PIN_MII1_RX_DV, PIN_INPUT_PULLDOWN, MUX_MODE2)		/* rgmii1_rctl */
181			AM33XX_PADCONF(AM335X_PIN_MII1_TXD3, PIN_OUTPUT_PULLDOWN, MUX_MODE2)		/* rgmii1_td3 */
182			AM33XX_PADCONF(AM335X_PIN_MII1_TXD2, PIN_OUTPUT_PULLDOWN, MUX_MODE2)		/* rgmii1_td2 */
183			AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_OUTPUT_PULLDOWN, MUX_MODE2)		/* rgmii1_td1 */
184			AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_OUTPUT_PULLDOWN, MUX_MODE2)		/* rgmii1_td0 */
185			AM33XX_PADCONF(AM335X_PIN_MII1_TX_CLK, PIN_OUTPUT_PULLDOWN, MUX_MODE2)		/* rgmii1_tclk */
186			AM33XX_PADCONF(AM335X_PIN_MII1_RX_CLK, PIN_INPUT_PULLDOWN, MUX_MODE2)		/* rgmii1_rclk */
187			AM33XX_PADCONF(AM335X_PIN_MII1_RXD3, PIN_INPUT_PULLDOWN, MUX_MODE2)		/* rgmii1_rd3 */
188			AM33XX_PADCONF(AM335X_PIN_MII1_RXD2, PIN_INPUT_PULLDOWN, MUX_MODE2)		/* rgmii1_rd2 */
189			AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLDOWN, MUX_MODE2)		/* rgmii1_rd1 */
190			AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLDOWN, MUX_MODE2)		/* rgmii1_rd0 */
191		>;
192	};
193
194	eth_slave1_pins_sleep: eth-slave1-sleep-pins {
195		pinctrl-single,pins = <
196			AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_INPUT_PULLDOWN, MUX_MODE7)
197			AM33XX_PADCONF(AM335X_PIN_MII1_RX_DV, PIN_INPUT_PULLDOWN, MUX_MODE7)
198			AM33XX_PADCONF(AM335X_PIN_MII1_TXD3, PIN_INPUT_PULLDOWN, MUX_MODE7)
199			AM33XX_PADCONF(AM335X_PIN_MII1_TXD2, PIN_INPUT_PULLDOWN, MUX_MODE7)
200			AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_INPUT_PULLDOWN, MUX_MODE7)
201			AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_INPUT_PULLDOWN, MUX_MODE7)
202			AM33XX_PADCONF(AM335X_PIN_MII1_TX_CLK, PIN_INPUT_PULLDOWN, MUX_MODE7)
203			AM33XX_PADCONF(AM335X_PIN_MII1_RX_CLK, PIN_INPUT_PULLDOWN, MUX_MODE7)
204			AM33XX_PADCONF(AM335X_PIN_MII1_RXD3, PIN_INPUT_PULLDOWN, MUX_MODE7)
205			AM33XX_PADCONF(AM335X_PIN_MII1_RXD2, PIN_INPUT_PULLDOWN, MUX_MODE7)
206			AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLDOWN, MUX_MODE7)
207			AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLDOWN, MUX_MODE7)
208		>;
209	};
210
211	i2c0_pins_default: i2c0-default-pins {
212		pinctrl-single,pins = <
213			AM33XX_PADCONF(AM335X_PIN_I2C0_SDA, PIN_INPUT | SLEWCTRL_FAST, MUX_MODE0)	/* I2C0_SDA */
214			AM33XX_PADCONF(AM335X_PIN_I2C0_SCL, PIN_INPUT | SLEWCTRL_FAST, MUX_MODE0)	/* I2C0_SCL */
215		>;
216	};
217
218	i2c0_pins_gpio: i2c0-gpio-pins {
219		pinctrl-single,pins = <
220			AM33XX_PADCONF(AM335X_PIN_I2C0_SDA, PIN_INPUT, MUX_MODE7)			/* gpio3[5] */
221			AM33XX_PADCONF(AM335X_PIN_I2C0_SCL, PIN_INPUT, MUX_MODE7)			/* gpio3[6] */
222		>;
223	};
224
225	i2c0_pins_sleep: i2c0-sleep-pins {
226		pinctrl-single,pins = <
227			AM33XX_PADCONF(AM335X_PIN_I2C0_SDA, PIN_INPUT_PULLDOWN, MUX_MODE7)
228			AM33XX_PADCONF(AM335X_PIN_I2C0_SCL, PIN_INPUT_PULLDOWN, MUX_MODE7)
229		>;
230	};
231
232	led_mod_pins: led-mod-pins {
233		pinctrl-single,pins = <
234			AM33XX_PADCONF(AM335X_PIN_MCASP0_ACLKR, PIN_OUTPUT_PULLDOWN, MUX_MODE7)		/* gpio3[18] */
235		>;
236	};
237
238	nand_pins_default: nand-default-pins {
239		pinctrl-single,pins = <
240			AM33XX_PADCONF(AM335X_PIN_GPMC_AD0, PIN_INPUT_PULLUP, MUX_MODE0)		/* gpmc_ad0 */
241			AM33XX_PADCONF(AM335X_PIN_GPMC_AD1, PIN_INPUT_PULLUP, MUX_MODE0)		/* gpmc_ad1 */
242			AM33XX_PADCONF(AM335X_PIN_GPMC_AD2, PIN_INPUT_PULLUP, MUX_MODE0)		/* gpmc_ad2 */
243			AM33XX_PADCONF(AM335X_PIN_GPMC_AD3, PIN_INPUT_PULLUP, MUX_MODE0)		/* gpmc_ad3 */
244			AM33XX_PADCONF(AM335X_PIN_GPMC_AD4, PIN_INPUT_PULLUP, MUX_MODE0)		/* gpmc_ad4 */
245			AM33XX_PADCONF(AM335X_PIN_GPMC_AD5, PIN_INPUT_PULLUP, MUX_MODE0)		/* gpmc_ad5 */
246			AM33XX_PADCONF(AM335X_PIN_GPMC_AD6, PIN_INPUT_PULLUP, MUX_MODE0)		/* gpmc_ad6 */
247			AM33XX_PADCONF(AM335X_PIN_GPMC_AD7, PIN_INPUT_PULLUP, MUX_MODE0)		/* gpmc_ad7 */
248			AM33XX_PADCONF(AM335X_PIN_GPMC_WAIT0, PIN_INPUT_PULLUP, MUX_MODE0)		/* gpmc_wait0 */
249			AM33XX_PADCONF(AM335X_PIN_GPMC_WPN, PIN_INPUT_PULLUP, MUX_MODE7)		/* gpio0[31] */
250			AM33XX_PADCONF(AM335X_PIN_GPMC_CSN0, PIN_OUTPUT, MUX_MODE0)			/* gpmc_csn0 */
251			AM33XX_PADCONF(AM335X_PIN_GPMC_ADVN_ALE, PIN_OUTPUT, MUX_MODE0)			/* gpmc_advn_ale */
252			AM33XX_PADCONF(AM335X_PIN_GPMC_OEN_REN, PIN_OUTPUT, MUX_MODE0)			/* gpmc_oen_ren */
253			AM33XX_PADCONF(AM335X_PIN_GPMC_WEN, PIN_OUTPUT, MUX_MODE0)			/* gpmc_wen */
254			AM33XX_PADCONF(AM335X_PIN_GPMC_BEN0_CLE, PIN_OUTPUT, MUX_MODE0)			/* gpmc_be0n_cle */
255		>;
256	};
257
258	nand_pins_sleep: nand-sleep-pins {
259		pinctrl-single,pins = <
260			AM33XX_PADCONF(AM335X_PIN_GPMC_AD0, PIN_INPUT_PULLDOWN, MUX_MODE7)
261			AM33XX_PADCONF(AM335X_PIN_GPMC_AD1, PIN_INPUT_PULLDOWN, MUX_MODE7)
262			AM33XX_PADCONF(AM335X_PIN_GPMC_AD2, PIN_INPUT_PULLDOWN, MUX_MODE7)
263			AM33XX_PADCONF(AM335X_PIN_GPMC_AD3, PIN_INPUT_PULLDOWN, MUX_MODE7)
264			AM33XX_PADCONF(AM335X_PIN_GPMC_AD4, PIN_INPUT_PULLDOWN, MUX_MODE7)
265			AM33XX_PADCONF(AM335X_PIN_GPMC_AD5, PIN_INPUT_PULLDOWN, MUX_MODE7)
266			AM33XX_PADCONF(AM335X_PIN_GPMC_AD6, PIN_INPUT_PULLDOWN, MUX_MODE7)
267			AM33XX_PADCONF(AM335X_PIN_GPMC_AD7, PIN_INPUT_PULLDOWN, MUX_MODE7)
268			AM33XX_PADCONF(AM335X_PIN_GPMC_WAIT0, PIN_INPUT_PULLDOWN, MUX_MODE7)
269			AM33XX_PADCONF(AM335X_PIN_GPMC_WPN, PIN_INPUT_PULLDOWN, MUX_MODE7)
270			AM33XX_PADCONF(AM335X_PIN_GPMC_CSN0, PIN_INPUT_PULLDOWN, MUX_MODE7)
271			AM33XX_PADCONF(AM335X_PIN_GPMC_ADVN_ALE, PIN_INPUT_PULLDOWN, MUX_MODE7)
272			AM33XX_PADCONF(AM335X_PIN_GPMC_OEN_REN, PIN_INPUT_PULLDOWN, MUX_MODE7)
273			AM33XX_PADCONF(AM335X_PIN_GPMC_WEN, PIN_INPUT_PULLDOWN, MUX_MODE7)
274			AM33XX_PADCONF(AM335X_PIN_GPMC_BEN0_CLE, PIN_INPUT_PULLDOWN, MUX_MODE7)
275		>;
276	};
277};
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