am335x-baltos.dtsi

  1// SPDX-License-Identifier: GPL-2.0-only
  2/*
  3 * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/
  4 */
  5
  6/*
  7 * VScom OnRISC
  8 * https://www.vscom.de
  9 */
 10
 11#include "am33xx.dtsi"
 12#include <dt-bindings/pwm/pwm.h>
 13#include <dt-bindings/interrupt-controller/irq.h>
 14
 15/ {
 16	compatible = "vscom,onrisc", "ti,am33xx";
 17
 18	cpus {
 19		cpu@0 {
 20			cpu0-supply = <&vdd1_reg>;
 21		};
 22	};
 23
 24	memory@80000000 {
 25		device_type = "memory";
 26		reg = <0x80000000 0x10000000>; /* 256 MB */
 27	};
 28
 29	vbat: fixedregulator0 {
 30		compatible = "regulator-fixed";
 31		regulator-name = "vbat";
 32		regulator-min-microvolt = <5000000>;
 33		regulator-max-microvolt = <5000000>;
 34		regulator-boot-on;
 35	};
 36
 37	wl12xx_vmmc: fixedregulator2 {
 38		pinctrl-names = "default";
 39		pinctrl-0 = <&wl12xx_gpio>;
 40		compatible = "regulator-fixed";
 41		regulator-name = "vwl1271";
 42		regulator-min-microvolt = <3300000>;
 43		regulator-max-microvolt = <3300000>;
 44		gpio = <&gpio3 8 0>;
 45		startup-delay-us = <70000>;
 46		enable-active-high;
 47	};
 48
 49	mpcie_regulator: mpcie-regulator {
 50		compatible = "regulator-fixed";
 51		regulator-name = "mpcie-regulator";
 52		regulator-min-microvolt = <3300000>;
 53		regulator-max-microvolt = <3300000>;
 54		gpio = <&gpio3 4 0>;
 55		enable-active-high;
 56		regulator-boot-on;
 57	};
 58
 59	mpcie_power_switch: mpcie-power-switch {
 60		compatible = "regulator-output";
 61		regulator-name = "mpcie-power-switch";
 62		regulator-supplies = "vcc";
 63		vout-supply = <&mpcie_regulator>;
 64	};
 65};
 66
 67&am33xx_pinmux {
 68	mmc2_pins: mmc2-pins {
 69		pinctrl-single,pins = <
 70			AM33XX_PADCONF(AM335X_PIN_GPMC_AD8, PIN_INPUT_PULLUP, MUX_MODE2)      /* gpmc_ad8.mmc1_dat0_mux0 */
 71			AM33XX_PADCONF(AM335X_PIN_GPMC_AD9, PIN_INPUT_PULLUP, MUX_MODE2)      /* gpmc_ad9.mmc1_dat1_mux0 */
 72			AM33XX_PADCONF(AM335X_PIN_GPMC_AD10, PIN_INPUT_PULLUP, MUX_MODE2)      /* gpmc_ad10.mmc1_dat2_mux0 */
 73			AM33XX_PADCONF(AM335X_PIN_GPMC_AD11, PIN_INPUT_PULLUP, MUX_MODE2)      /* gpmc_ad11.mmc1_dat3_mux0 */
 74			AM33XX_PADCONF(AM335X_PIN_GPMC_CSN1, PIN_INPUT_PULLUP, MUX_MODE2)      /* gpmc_csn1.mmc1_clk_mux0 */
 75			AM33XX_PADCONF(AM335X_PIN_GPMC_CSN2, PIN_INPUT_PULLUP, MUX_MODE2)      /* gpmc_csn2.mmc1_cmd_mux0 */
 76			AM33XX_PADCONF(AM335X_PIN_EMU0, PIN_INPUT_PULLUP, MUX_MODE7)      /* emu0.gpio3[7] */
 77		>;
 78	};
 79
 80	wl12xx_gpio: wl12xx-gpio-pins {
 81		pinctrl-single,pins = <
 82			AM33XX_PADCONF(AM335X_PIN_EMU1, PIN_OUTPUT_PULLUP, MUX_MODE7)      /* emu1.gpio3[8] */
 83		>;
 84	};
 85
 86	tps65910_pins: tps65910-pins {
 87		pinctrl-single,pins = <
 88			AM33XX_PADCONF(AM335X_PIN_GPMC_BEN1, PIN_INPUT_PULLUP, MUX_MODE7)      /* gpmc_ben1.gpio1[28] */
 89		>;
 90	};
 91
 92	i2c1_pins: i2c1-pins {
 93		pinctrl-single,pins = <
 94			AM33XX_PADCONF(AM335X_PIN_SPI0_D1, PIN_INPUT, MUX_MODE2)      /* spi0_d1.i2c1_sda_mux3 */
 95			AM33XX_PADCONF(AM335X_PIN_SPI0_CS0, PIN_INPUT, MUX_MODE2)      /* spi0_cs0.i2c1_scl_mux3 */
 96		>;
 97	};
 98
 99	uart0_pins: uart0-pins {
100		pinctrl-single,pins = <
101			AM33XX_PADCONF(AM335X_PIN_UART0_RXD, PIN_INPUT_PULLUP, MUX_MODE0)
102			AM33XX_PADCONF(AM335X_PIN_UART0_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0)
103		>;
104	};
105
106	cpsw_default: cpsw-default-pins {
107		pinctrl-single,pins = <
108			/* Slave 1 */
109			AM33XX_PADCONF(AM335X_PIN_MII1_CRS, PIN_INPUT_PULLDOWN, MUX_MODE1)       /* mii1_crs.rmii1_crs_dv */
110			AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_OUTPUT_PULLDOWN, MUX_MODE1)      /* mii1_tx_en.rmii1_txen */
111			AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_OUTPUT_PULLDOWN, MUX_MODE1)      /* mii1_txd1.rmii1_txd1 */
112			AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_OUTPUT_PULLDOWN, MUX_MODE1)      /* mii1_txd0.rmii1_txd0 */
113			AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLDOWN, MUX_MODE1)      /* mii1_rxd1.rmii1_rxd1 */
114			AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLDOWN, MUX_MODE1)      /* mii1_rxd0.rmii1_rxd0 */
115			AM33XX_PADCONF(AM335X_PIN_RMII1_REF_CLK, PIN_INPUT_PULLDOWN, MUX_MODE0)      /* rmii1_ref_clk.rmii1_refclk */
116
117
118			/* Slave 2 */
119			AM33XX_PADCONF(AM335X_PIN_GPMC_A0, PIN_OUTPUT_PULLDOWN, MUX_MODE2)	/* gpmc_a0.rgmii2_tctl */
120			AM33XX_PADCONF(AM335X_PIN_GPMC_A1, PIN_INPUT_PULLDOWN, MUX_MODE2)	/* gpmc_a1.rgmii2_rctl */
121			AM33XX_PADCONF(AM335X_PIN_GPMC_A2, PIN_OUTPUT_PULLDOWN, MUX_MODE2)	/* gpmc_a2.rgmii2_td3 */
122			AM33XX_PADCONF(AM335X_PIN_GPMC_A3, PIN_OUTPUT_PULLDOWN, MUX_MODE2)	/* gpmc_a3.rgmii2_td2 */
123			AM33XX_PADCONF(AM335X_PIN_GPMC_A4, PIN_OUTPUT_PULLDOWN, MUX_MODE2)	/* gpmc_a4.rgmii2_td1 */
124			AM33XX_PADCONF(AM335X_PIN_GPMC_A5, PIN_OUTPUT_PULLDOWN, MUX_MODE2)	/* gpmc_a5.rgmii2_td0 */
125			AM33XX_PADCONF(AM335X_PIN_GPMC_A6, PIN_OUTPUT_PULLDOWN, MUX_MODE2)	/* gpmc_a6.rgmii2_tclk */
126			AM33XX_PADCONF(AM335X_PIN_GPMC_A7, PIN_INPUT_PULLDOWN, MUX_MODE2)	/* gpmc_a7.rgmii2_rclk */
127			AM33XX_PADCONF(AM335X_PIN_GPMC_A8, PIN_INPUT_PULLDOWN, MUX_MODE2)	/* gpmc_a8.rgmii2_rd3 */
128			AM33XX_PADCONF(AM335X_PIN_GPMC_A9, PIN_INPUT_PULLDOWN, MUX_MODE2)	/* gpmc_a9.rgmii2_rd2 */
129			AM33XX_PADCONF(AM335X_PIN_GPMC_A10, PIN_INPUT_PULLDOWN, MUX_MODE2)	/* gpmc_a10.rgmii2_rd1 */
130			AM33XX_PADCONF(AM335X_PIN_GPMC_A11, PIN_INPUT_PULLDOWN, MUX_MODE2)	/* gpmc_a11.rgmii2_rd0 */
131		>;
132	};
133
134	cpsw_sleep: cpsw-sleep-pins {
135		pinctrl-single,pins = <
136			/* Slave 1 reset value */
137			AM33XX_PADCONF(AM335X_PIN_MII1_CRS, PIN_INPUT_PULLDOWN, MUX_MODE7)
138			AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_INPUT_PULLDOWN, MUX_MODE7)
139			AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_INPUT_PULLDOWN, MUX_MODE7)
140			AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_INPUT_PULLDOWN, MUX_MODE7)
141			AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLDOWN, MUX_MODE7)
142			AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLDOWN, MUX_MODE7)
143			AM33XX_PADCONF(AM335X_PIN_RMII1_REF_CLK, PIN_INPUT_PULLDOWN, MUX_MODE7)
144
145			/* Slave 2 reset value*/
146			AM33XX_PADCONF(AM335X_PIN_GPMC_A0, PIN_INPUT_PULLDOWN, MUX_MODE7)
147			AM33XX_PADCONF(AM335X_PIN_GPMC_A1, PIN_INPUT_PULLDOWN, MUX_MODE7)
148			AM33XX_PADCONF(AM335X_PIN_GPMC_A2, PIN_INPUT_PULLDOWN, MUX_MODE7)
149			AM33XX_PADCONF(AM335X_PIN_GPMC_A3, PIN_INPUT_PULLDOWN, MUX_MODE7)
150			AM33XX_PADCONF(AM335X_PIN_GPMC_A4, PIN_INPUT_PULLDOWN, MUX_MODE7)
151			AM33XX_PADCONF(AM335X_PIN_GPMC_A5, PIN_INPUT_PULLDOWN, MUX_MODE7)
152			AM33XX_PADCONF(AM335X_PIN_GPMC_A6, PIN_INPUT_PULLDOWN, MUX_MODE7)
153			AM33XX_PADCONF(AM335X_PIN_GPMC_A7, PIN_INPUT_PULLDOWN, MUX_MODE7)
154			AM33XX_PADCONF(AM335X_PIN_GPMC_A8, PIN_INPUT_PULLDOWN, MUX_MODE7)
155			AM33XX_PADCONF(AM335X_PIN_GPMC_A9, PIN_INPUT_PULLDOWN, MUX_MODE7)
156			AM33XX_PADCONF(AM335X_PIN_GPMC_A10, PIN_INPUT_PULLDOWN, MUX_MODE7)
157			AM33XX_PADCONF(AM335X_PIN_GPMC_A11, PIN_INPUT_PULLDOWN, MUX_MODE7)
158		>;
159	};
160
161	davinci_mdio_default: davinci-mdio-default-pins {
162		pinctrl-single,pins = <
163			/* MDIO */
164			AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLUP | SLEWCTRL_FAST, MUX_MODE0)	/* mdio_data.mdio_data */
165			AM33XX_PADCONF(AM335X_PIN_MDC, PIN_OUTPUT_PULLUP, MUX_MODE0)			/* mdio_clk.mdio_clk */
166		>;
167	};
168
169	davinci_mdio_sleep: davinci-mdio-sleep-pins {
170		pinctrl-single,pins = <
171			/* MDIO reset value */
172			AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLDOWN, MUX_MODE7)
173			AM33XX_PADCONF(AM335X_PIN_MDC, PIN_INPUT_PULLDOWN, MUX_MODE7)
174		>;
175	};
176
177	nandflash_pins_s0: nandflash-s0-pins {
178		pinctrl-single,pins = <
179			AM33XX_PADCONF(AM335X_PIN_GPMC_AD0, PIN_INPUT_PULLUP, MUX_MODE0)	/* gpmc_ad0.gpmc_ad0 */
180			AM33XX_PADCONF(AM335X_PIN_GPMC_AD1, PIN_INPUT_PULLUP, MUX_MODE0)	/* gpmc_ad1.gpmc_ad1 */
181			AM33XX_PADCONF(AM335X_PIN_GPMC_AD2, PIN_INPUT_PULLUP, MUX_MODE0)	/* gpmc_ad2.gpmc_ad2 */
182			AM33XX_PADCONF(AM335X_PIN_GPMC_AD3, PIN_INPUT_PULLUP, MUX_MODE0)	/* gpmc_ad3.gpmc_ad3 */
183			AM33XX_PADCONF(AM335X_PIN_GPMC_AD4, PIN_INPUT_PULLUP, MUX_MODE0)	/* gpmc_ad4.gpmc_ad4 */
184			AM33XX_PADCONF(AM335X_PIN_GPMC_AD5, PIN_INPUT_PULLUP, MUX_MODE0)	/* gpmc_ad5.gpmc_ad5 */
185			AM33XX_PADCONF(AM335X_PIN_GPMC_AD6, PIN_INPUT_PULLUP, MUX_MODE0)	/* gpmc_ad6.gpmc_ad6 */
186			AM33XX_PADCONF(AM335X_PIN_GPMC_AD7, PIN_INPUT_PULLUP, MUX_MODE0)	/* gpmc_ad7.gpmc_ad7 */
187			AM33XX_PADCONF(AM335X_PIN_GPMC_WAIT0, PIN_INPUT_PULLUP, MUX_MODE0)	/* gpmc_wait0.gpmc_wait0 */
188			AM33XX_PADCONF(AM335X_PIN_GPMC_WPN, PIN_INPUT_PULLUP, MUX_MODE7)	/* gpmc_wpn.gpio0_31 */
189			AM33XX_PADCONF(AM335X_PIN_GPMC_CSN0, PIN_OUTPUT, MUX_MODE0)		/* gpmc_csn0.gpmc_csn0  */
190			AM33XX_PADCONF(AM335X_PIN_GPMC_ADVN_ALE, PIN_OUTPUT, MUX_MODE0)		/* gpmc_advn_ale.gpmc_advn_ale */
191			AM33XX_PADCONF(AM335X_PIN_GPMC_OEN_REN, PIN_OUTPUT, MUX_MODE0)		/* gpmc_oen_ren.gpmc_oen_ren */
192			AM33XX_PADCONF(AM335X_PIN_GPMC_WEN, PIN_OUTPUT, MUX_MODE0)		/* gpmc_wen.gpmc_wen */
193			AM33XX_PADCONF(AM335X_PIN_GPMC_BEN0_CLE, PIN_OUTPUT, MUX_MODE0)		/* gpmc_be0n_cle.gpmc_be0n_cle */
194		>;
195	};
196};
197
198&elm {
199	status = "okay";
200};
201
202&gpmc {
203	pinctrl-names = "default";
204	pinctrl-0 = <&nandflash_pins_s0>;
205	ranges = <0 0 0x08000000 0x10000000>;	/* CS0: NAND */
206	status = "okay";
207
208	nand@0,0 {
209		compatible = "ti,omap2-nand";
210		reg = <0 0 4>; /* CS0, offset 0, IO size 4 */
211		interrupt-parent = <&gpmc>;
212		interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
213			     <1 IRQ_TYPE_NONE>;	/* termcount */
214		rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 */
215		nand-bus-width = <8>;
216		ti,nand-ecc-opt = "bch8";
217		ti,nand-xfer-type = "prefetch-dma";
218
219		gpmc,device-width = <1>;
220		gpmc,sync-clk-ps = <0>;
221		gpmc,cs-on-ns = <0>;
222		gpmc,cs-rd-off-ns = <44>;
223		gpmc,cs-wr-off-ns = <44>;
224		gpmc,adv-on-ns = <6>;
225		gpmc,adv-rd-off-ns = <34>;
226		gpmc,adv-wr-off-ns = <44>;
227		gpmc,we-on-ns = <0>;
228		gpmc,we-off-ns = <40>;
229		gpmc,oe-on-ns = <0>;
230		gpmc,oe-off-ns = <54>;
231		gpmc,access-ns = <64>;
232		gpmc,rd-cycle-ns = <82>;
233		gpmc,wr-cycle-ns = <82>;
234		gpmc,bus-turnaround-ns = <0>;
235		gpmc,cycle2cycle-delay-ns = <0>;
236		gpmc,clk-activation-ns = <0>;
237		gpmc,wr-access-ns = <40>;
238		gpmc,wr-data-mux-bus-ns = <0>;
239
240		#address-cells = <1>;
241		#size-cells = <1>;
242		ti,elm-id = <&elm>;
243	};
244};
245
246&uart0 {
247	pinctrl-names = "default";
248	pinctrl-0 = <&uart0_pins>;
249
250	status = "okay";
251};
252
253&i2c1 {
254	pinctrl-names = "default";
255	pinctrl-0 = <&i2c1_pins>;
256
257	status = "okay";
258	clock-frequency = <400000>;
259
260	tps: tps@2d {
261		reg = <0x2d>;
262		gpio-controller;
263		#gpio-cells = <2>;
264		interrupt-parent = <&gpio1>;
265		interrupts = <28 IRQ_TYPE_EDGE_RISING>;
266		pinctrl-names = "default";
267		pinctrl-0 = <&tps65910_pins>;
268	};
269
270	eeprom@50 {
271		compatible = "atmel,24c02";
272		pagesize = <8>;
273		reg = <0x50>;
274	};
275};
276
277#include "../../tps65910.dtsi"
278
279&tps {
280	vcc1-supply = <&vbat>;
281	vcc2-supply = <&vbat>;
282	vcc3-supply = <&vbat>;
283	vcc4-supply = <&vbat>;
284	vcc5-supply = <&vbat>;
285	vcc6-supply = <&vbat>;
286	vcc7-supply = <&vbat>;
287	vccio-supply = <&vbat>;
288
289	ti,en-ck32k-xtal;
290
291	regulators {
292		vrtc_reg: regulator@0 {
293			regulator-always-on;
294		};
295
296		vio_reg: regulator@1 {
297			regulator-always-on;
298		};
299
300		vdd1_reg: regulator@2 {
301			/* VDD_MPU voltage limits 0.95V - 1.26V with +/-4% tolerance */
302			regulator-name = "vdd_mpu";
303			regulator-min-microvolt = <912500>;
304			regulator-max-microvolt = <1351500>;
305			regulator-boot-on;
306			regulator-always-on;
307		};
308
309		vdd2_reg: regulator@3 {
310			/* VDD_CORE voltage limits 0.95V - 1.1V with +/-4% tolerance */
311			regulator-name = "vdd_core";
312			regulator-min-microvolt = <912500>;
313			regulator-max-microvolt = <1150000>;
314			regulator-boot-on;
315			regulator-always-on;
316		};
317
318		vdd3_reg: regulator@4 {
319			regulator-always-on;
320		};
321
322		vdig1_reg: regulator@5 {
323			regulator-always-on;
324		};
325
326		vdig2_reg: regulator@6 {
327			regulator-always-on;
328		};
329
330		vpll_reg: regulator@7 {
331			regulator-always-on;
332		};
333
334		vdac_reg: regulator@8 {
335			regulator-always-on;
336		};
337
338		vaux1_reg: regulator@9 {
339			regulator-always-on;
340		};
341
342		vaux2_reg: regulator@10 {
343			regulator-always-on;
344		};
345
346		vaux33_reg: regulator@11 {
347			regulator-always-on;
348		};
349
350		vmmc_reg: regulator@12 {
351			regulator-min-microvolt = <1800000>;
352			regulator-max-microvolt = <3300000>;
353			regulator-always-on;
354		};
355	};
356};
357
358&mac_sw {
359	pinctrl-names = "default", "sleep";
360	pinctrl-0 = <&cpsw_default>;
361	pinctrl-1 = <&cpsw_sleep>;
362
363	status = "okay";
364};
365
366&davinci_mdio_sw {
367	status = "okay";
368	pinctrl-names = "default", "sleep";
369	pinctrl-0 = <&davinci_mdio_default>;
370	pinctrl-1 = <&davinci_mdio_sleep>;
371
372	phy1: ethernet-phy@1 {
373		reg = <7>;
374		eee-broken-100tx;
375		eee-broken-1000t;
376	};
377};
378
379&mmc1 {
380	vmmc-supply = <&vmmc_reg>;
381	status = "okay";
382};
383
384&mmc2 {
385	status = "okay";
386	vmmc-supply = <&wl12xx_vmmc>;
387	non-removable;
388	bus-width = <4>;
389	cap-power-off-card;
390	pinctrl-names = "default";
391	pinctrl-0 = <&mmc2_pins>;
392
393	#address-cells = <1>;
394	#size-cells = <0>;
395	wlcore: wlcore@2 {
396		compatible = "ti,wl1835";
397		reg = <2>;
398		interrupt-parent = <&gpio3>;
399		interrupts = <7 IRQ_TYPE_EDGE_RISING>;
400	};
401};
402
403&sham {
404	status = "okay";
405};
406
407&aes {
408	status = "okay";
409};
410
411&gpio0_target {
412	ti,no-reset-on-init;
413};
414
415&gpio3_target {
416	ti,no-reset-on-init;
417};