stm32mp151a-prtt1l.dtsi

  1// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
  2/*
  3 * Copyright (C) Protonic Holland
  4 * Author: David Jander <david@protonic.nl>
  5 */
  6/dts-v1/;
  7
  8#include "stm32mp151.dtsi"
  9#include "stm32mp15-pinctrl.dtsi"
 10#include "stm32mp15xxad-pinctrl.dtsi"
 11#include <dt-bindings/gpio/gpio.h>
 12#include <dt-bindings/input/input.h>
 13#include <dt-bindings/leds/common.h>
 14
 15/ {
 16	aliases {
 17		ethernet0 = &ethernet0;
 18		mdio-gpio0 = &mdio0;
 19		serial0 = &uart4;
 20	};
 21
 22	led-controller-0 {
 23		compatible = "gpio-leds";
 24
 25		led-0 {
 26			color = <LED_COLOR_ID_RED>;
 27			function = LED_FUNCTION_INDICATOR;
 28			gpios = <&gpioa 13 GPIO_ACTIVE_LOW>;
 29		};
 30
 31		led-1 {
 32			color = <LED_COLOR_ID_GREEN>;
 33			function = LED_FUNCTION_INDICATOR;
 34			gpios = <&gpioa 14 GPIO_ACTIVE_LOW>;
 35			linux,default-trigger = "heartbeat";
 36		};
 37	};
 38
 39
 40	/* DP83TD510E PHYs have max MDC rate of 1.75MHz. Since we can't reduce
 41	 * stmmac MDC clock without reducing system bus rate, we need to use
 42	 * gpio based MDIO bus.
 43	 */
 44	mdio0: mdio {
 45		compatible = "virtual,mdio-gpio";
 46		#address-cells = <1>;
 47		#size-cells = <0>;
 48		gpios = <&gpioc 1 GPIO_ACTIVE_HIGH
 49			 &gpioa 2 GPIO_ACTIVE_HIGH>;
 50	};
 51
 52	reg_3v3: regulator-3v3 {
 53		compatible = "regulator-fixed";
 54		regulator-name = "3v3";
 55		regulator-min-microvolt = <3300000>;
 56		regulator-max-microvolt = <3300000>;
 57	};
 58};
 59
 60&dts {
 61	status = "okay";
 62};
 63
 64&ethernet0 {
 65	pinctrl-0 = <&ethernet0_rmii_pins_a>;
 66	pinctrl-1 = <&ethernet0_rmii_sleep_pins_a>;
 67	pinctrl-names = "default", "sleep";
 68	phy-mode = "rmii";
 69	status = "okay";
 70};
 71
 72&{ethernet0_rmii_pins_a/pins1} {
 73	pinmux = <STM32_PINMUX('B', 12, AF11)>, /* ETH1_RMII_TXD0 */
 74		 <STM32_PINMUX('B', 13, AF11)>, /* ETH1_RMII_TXD1 */
 75		 <STM32_PINMUX('B', 11, AF11)>; /* ETH1_RMII_TX_EN */
 76};
 77
 78&{ethernet0_rmii_pins_a/pins2} {
 79	pinmux = <STM32_PINMUX('C', 4, AF11)>,  /* ETH1_RMII_RXD0 */
 80		 <STM32_PINMUX('C', 5, AF11)>,  /* ETH1_RMII_RXD1 */
 81		 <STM32_PINMUX('A', 1, AF11)>,  /* ETH1_RMII_REF_CLK input */
 82		 <STM32_PINMUX('A', 7, AF11)>;  /* ETH1_RMII_CRS_DV */
 83};
 84
 85&{ethernet0_rmii_sleep_pins_a/pins1} {
 86	pinmux = <STM32_PINMUX('B', 12, ANALOG)>, /* ETH1_RMII_TXD0 */
 87		 <STM32_PINMUX('B', 13, ANALOG)>, /* ETH1_RMII_TXD1 */
 88		 <STM32_PINMUX('B', 11, ANALOG)>, /* ETH1_RMII_TX_EN */
 89		 <STM32_PINMUX('C', 4, ANALOG)>,  /* ETH1_RMII_RXD0 */
 90		 <STM32_PINMUX('C', 5, ANALOG)>,  /* ETH1_RMII_RXD1 */
 91		 <STM32_PINMUX('A', 1, ANALOG)>,  /* ETH1_RMII_REF_CLK */
 92		 <STM32_PINMUX('A', 7, ANALOG)>;  /* ETH1_RMII_CRS_DV */
 93};
 94
 95&iwdg2 {
 96	status = "okay";
 97};
 98
 99&qspi {
100	pinctrl-names = "default", "sleep";
101	pinctrl-0 = <&qspi_clk_pins_a
102		     &qspi_bk1_pins_a
103		     &qspi_cs1_pins_a>;
104	pinctrl-1 = <&qspi_clk_sleep_pins_a
105		     &qspi_bk1_sleep_pins_a
106		     &qspi_cs1_sleep_pins_a>;
107	reg = <0x58003000 0x1000>, <0x70000000 0x4000000>;
108	#address-cells = <1>;
109	#size-cells = <0>;
110	status = "okay";
111
112	flash@0 {
113		compatible = "spi-nand";
114		reg = <0>;
115		spi-rx-bus-width = <4>;
116		spi-max-frequency = <104000000>;
117		#address-cells = <1>;
118		#size-cells = <1>;
119	};
120};
121
122&{qspi_bk1_pins_a/pins} {
123	/delete-property/ bias-disable;
124	bias-pull-up;
125	drive-push-pull;
126	slew-rate = <1>;
127};
128
129&rng1 {
130	status = "okay";
131};
132
133&sdmmc1 {
134	pinctrl-names = "default", "opendrain", "sleep";
135	pinctrl-0 = <&sdmmc1_b4_pins_a>;
136	pinctrl-1 = <&sdmmc1_b4_od_pins_a>;
137	pinctrl-2 = <&sdmmc1_b4_sleep_pins_a>;
138	broken-cd;
139	st,neg-edge;
140	bus-width = <4>;
141	vmmc-supply = <&reg_3v3>;
142	vqmmc-supply = <&reg_3v3>;
143	status = "okay";
144};
145
146&{sdmmc1_b4_od_pins_a/pins1} {
147	/delete-property/ bias-disable;
148	bias-pull-up;
149};
150
151&{sdmmc1_b4_od_pins_a/pins2} {
152	/delete-property/ bias-disable;
153	bias-pull-up;
154};
155
156&{sdmmc1_b4_pins_a/pins1} {
157	/delete-property/ bias-disable;
158	bias-pull-up;
159};
160
161&{sdmmc1_b4_pins_a/pins2} {
162	/delete-property/ bias-disable;
163	bias-pull-up;
164};
165
166&uart4 {
167	pinctrl-names = "default", "sleep", "idle";
168	pinctrl-0 = <&uart4_pins_a>;
169	pinctrl-1 = <&uart4_sleep_pins_a>;
170	pinctrl-2 = <&uart4_idle_pins_a>;
171	/delete-property/dmas;
172	/delete-property/dma-names;
173	status = "okay";
174};
175
176&{uart4_idle_pins_a/pins1} {
177	pinmux = <STM32_PINMUX('B', 9, ANALOG)>; /* UART4_TX */
178};
179
180&{uart4_idle_pins_a/pins2} {
181	pinmux = <STM32_PINMUX('B', 2, AF8)>; /* UART4_RX */
182	/delete-property/ bias-disable;
183	bias-pull-up;
184};
185
186&{uart4_pins_a/pins1} {
187	pinmux = <STM32_PINMUX('B', 9, AF8)>; /* UART4_TX */
188	slew-rate = <0>;
189};
190
191&{uart4_pins_a/pins2} {
192	pinmux = <STM32_PINMUX('B', 2, AF8)>; /* UART4_RX */
193	/delete-property/ bias-disable;
194	bias-pull-up;
195};
196
197&{uart4_sleep_pins_a/pins} {
198	pinmux = <STM32_PINMUX('B', 9, ANALOG)>, /* UART4_TX */
199		<STM32_PINMUX('B', 2, ANALOG)>; /* UART4_RX */
200};
201
202&usbh_ehci {
203	status = "okay";
204};
205
206&usbotg_hs {
207	dr_mode = "host";
208	pinctrl-0 = <&usbotg_hs_pins_a>;
209	pinctrl-names = "default";
210	phys = <&usbphyc_port1 0>;
211	phy-names = "usb2-phy";
212	status = "okay";
213};
214
215&usbphyc {
216	status = "okay";
217};
218
219&usbphyc_port0 {
220	phy-supply = <&reg_3v3>;
221};
222
223&usbphyc_port1 {
224	phy-supply = <&reg_3v3>;
225};