stm32mp133.dtsi

  1// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
  2/*
  3 * Copyright (C) STMicroelectronics 2021 - All Rights Reserved
  4 * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
  5 */
  6
  7#include "stm32mp131.dtsi"
  8
  9/ {
 10	soc {
 11		m_can1: can@4400e000 {
 12			compatible = "bosch,m_can";
 13			reg = <0x4400e000 0x400>, <0x44011000 0x1400>;
 14			reg-names = "m_can", "message_ram";
 15			interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
 16				     <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
 17			interrupt-names = "int0", "int1";
 18			clocks = <&scmi_clk CK_SCMI_HSE>, <&rcc FDCAN_K>;
 19			clock-names = "hclk", "cclk";
 20			bosch,mram-cfg = <0x0 0 0 32 0 0 2 2>;
 21			status = "disabled";
 22		};
 23
 24		m_can2: can@4400f000 {
 25			compatible = "bosch,m_can";
 26			reg = <0x4400f000 0x400>, <0x44011000 0x2800>;
 27			reg-names = "m_can", "message_ram";
 28			interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
 29				     <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
 30			interrupt-names = "int0", "int1";
 31			clocks = <&scmi_clk CK_SCMI_HSE>, <&rcc FDCAN_K>;
 32			clock-names = "hclk", "cclk";
 33			bosch,mram-cfg = <0x1400 0 0 32 0 0 2 2>;
 34			status = "disabled";
 35		};
 36	};
 37};
 38
 39&etzpc {
 40	adc_1: adc@48003000 {
 41		compatible = "st,stm32mp13-adc-core";
 42		reg = <0x48003000 0x400>;
 43		interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
 44		clocks = <&rcc ADC1>, <&rcc ADC1_K>;
 45		clock-names = "bus", "adc";
 46		interrupt-controller;
 47		#interrupt-cells = <1>;
 48		#address-cells = <1>;
 49		#size-cells = <0>;
 50		access-controllers = <&etzpc 32>;
 51		status = "disabled";
 52
 53		adc1: adc@0 {
 54			compatible = "st,stm32mp13-adc";
 55			#io-channel-cells = <1>;
 56			#address-cells = <1>;
 57			#size-cells = <0>;
 58			reg = <0x0>;
 59			interrupt-parent = <&adc_1>;
 60			interrupts = <0>;
 61			dmas = <&dmamux1 9 0x400 0x80000001>;
 62			dma-names = "rx";
 63			nvmem-cells = <&vrefint>;
 64			nvmem-cell-names = "vrefint";
 65			status = "disabled";
 66
 67			channel@18 {
 68				reg = <18>;
 69				label = "vrefint";
 70			};
 71		};
 72	};
 73
 74	ethernet2: ethernet@5800e000 {
 75		compatible = "st,stm32mp13-dwmac", "snps,dwmac-4.20a";
 76		reg = <0x5800e000 0x2000>;
 77		reg-names = "stmmaceth";
 78		interrupts-extended = <&intc GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
 79		interrupt-names = "macirq";
 80		clock-names = "stmmaceth",
 81			      "mac-clk-tx",
 82			      "mac-clk-rx",
 83			      "ethstp",
 84			      "ptp_ref",
 85			      "eth-ck";
 86		clocks = <&rcc ETH2MAC>,
 87			 <&rcc ETH2TX>,
 88			 <&rcc ETH2RX>,
 89			 <&rcc ETH2STP>,
 90			 <&rcc ETH2PTP_K>,
 91			 <&rcc ETH2CK_K>;
 92		st,syscon = <&syscfg 0x4 0xff000000>;
 93		snps,mixed-burst;
 94		snps,pbl = <2>;
 95		snps,axi-config = <&stmmac_axi_config_2>;
 96		snps,tso;
 97		access-controllers = <&etzpc 49>;
 98		nvmem-cells = <&ethernet_mac2_address>;
 99		nvmem-cell-names = "mac-address";
100		status = "disabled";
101
102		stmmac_axi_config_2: stmmac-axi-config {
103			snps,blen = <0 0 0 0 16 8 4>;
104			snps,rd_osr_lmt = <0x7>;
105			snps,wr_osr_lmt = <0x7>;
106		};
107	};
108};