FILE
stm32mp131.dtsi
File preview with syntax highlighting.
linux-6.19.14/arch/arm/boot/dts/st/stm32mp131.dtsi
1// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) 2/* 3 * Copyright (C) STMicroelectronics 2021 - All Rights Reserved 4 * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics. 5 */ 6#include <dt-bindings/interrupt-controller/arm-gic.h> 7#include <dt-bindings/clock/stm32mp13-clks.h> 8#include <dt-bindings/reset/stm32mp13-resets.h> 9 10/ { 11 #address-cells = <1>; 12 #size-cells = <1>; 13 14 cpus { 15 #address-cells = <1>; 16 #size-cells = <0>; 17 18 cpu0: cpu@0 { 19 compatible = "arm,cortex-a7"; 20 device_type = "cpu"; 21 reg = <0>; 22 }; 23 }; 24 25 arm-pmu { 26 compatible = "arm,cortex-a7-pmu"; 27 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 28 interrupt-affinity = <&cpu0>; 29 interrupt-parent = <&intc>; 30 }; 31 32 arm_wdt: watchdog { 33 compatible = "arm,smc-wdt"; 34 arm,smc-id = <0xbc000000>; 35 status = "disabled"; 36 }; 37 38 firmware { 39 optee { 40 method = "smc"; 41 compatible = "linaro,optee-tz"; 42 interrupt-parent = <&intc>; 43 interrupts = <GIC_PPI 15 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>; 44 }; 45 46 scmi: scmi { 47 compatible = "linaro,scmi-optee"; 48 #address-cells = <1>; 49 #size-cells = <0>; 50 linaro,optee-channel-id = <0>; 51 52 scmi_clk: protocol@14 { 53 reg = <0x14>; 54 #clock-cells = <1>; 55 }; 56 57 scmi_reset: protocol@16 { 58 reg = <0x16>; 59 #reset-cells = <1>; 60 }; 61 62 scmi_voltd: protocol@17 { 63 reg = <0x17>; 64 65 scmi_regu: regulators { 66 #address-cells = <1>; 67 #size-cells = <0>; 68 69 scmi_reg11: regulator@0 { 70 reg = <VOLTD_SCMI_REG11>; 71 regulator-name = "reg11"; 72 }; 73 scmi_reg18: regulator@1 { 74 reg = <VOLTD_SCMI_REG18>; 75 regulator-name = "reg18"; 76 }; 77 scmi_usb33: regulator@2 { 78 reg = <VOLTD_SCMI_USB33>; 79 regulator-name = "usb33"; 80 }; 81 }; 82 }; 83 }; 84 }; 85 86 intc: interrupt-controller@a0021000 { 87 compatible = "arm,cortex-a7-gic"; 88 #interrupt-cells = <3>; 89 interrupt-controller; 90 reg = <0xa0021000 0x1000>, 91 <0xa0022000 0x2000>; 92 }; 93 94 psci { 95 compatible = "arm,psci-1.0"; 96 method = "smc"; 97 }; 98 99 timer { 100 compatible = "arm,armv7-timer"; 101 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, 102 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, 103 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, 104 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>; 105 interrupt-parent = <&intc>; 106 always-on; 107 }; 108 109 thermal-zones { 110 cpu_thermal: cpu-thermal { 111 polling-delay-passive = <0>; 112 polling-delay = <0>; 113 thermal-sensors = <&dts>; 114 115 trips { 116 cpu_alert1: cpu-alert1 { 117 temperature = <85000>; 118 hysteresis = <0>; 119 type = "passive"; 120 }; 121 122 cpu-crit { 123 temperature = <120000>; 124 hysteresis = <0>; 125 type = "critical"; 126 }; 127 }; 128 129 cooling-maps { 130 }; 131 }; 132 }; 133 134 soc { 135 compatible = "simple-bus"; 136 #address-cells = <1>; 137 #size-cells = <1>; 138 interrupt-parent = <&intc>; 139 ranges; 140 141 timers2: timer@40000000 { 142 #address-cells = <1>; 143 #size-cells = <0>; 144 compatible = "st,stm32-timers"; 145 reg = <0x40000000 0x400>; 146 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 147 interrupt-names = "global"; 148 clocks = <&rcc TIM2_K>; 149 clock-names = "int"; 150 dmas = <&dmamux1 18 0x400 0x1>, 151 <&dmamux1 19 0x400 0x1>, 152 <&dmamux1 20 0x400 0x1>, 153 <&dmamux1 21 0x400 0x1>, 154 <&dmamux1 22 0x400 0x1>; 155 dma-names = "ch1", "ch2", "ch3", "ch4", "up"; 156 status = "disabled"; 157 158 pwm { 159 compatible = "st,stm32-pwm"; 160 #pwm-cells = <3>; 161 status = "disabled"; 162 }; 163 164 timer@1 { 165 compatible = "st,stm32h7-timer-trigger"; 166 reg = <1>; 167 status = "disabled"; 168 }; 169 170 counter { 171 compatible = "st,stm32-timer-counter"; 172 status = "disabled"; 173 }; 174 }; 175 176 timers3: timer@40001000 { 177 #address-cells = <1>; 178 #size-cells = <0>; 179 compatible = "st,stm32-timers"; 180 reg = <0x40001000 0x400>; 181 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 182 interrupt-names = "global"; 183 clocks = <&rcc TIM3_K>; 184 clock-names = "int"; 185 dmas = <&dmamux1 23 0x400 0x1>, 186 <&dmamux1 24 0x400 0x1>, 187 <&dmamux1 25 0x400 0x1>, 188 <&dmamux1 26 0x400 0x1>, 189 <&dmamux1 27 0x400 0x1>, 190 <&dmamux1 28 0x400 0x1>; 191 dma-names = "ch1", "ch2", "ch3", "ch4", "up", "trig"; 192 status = "disabled"; 193 194 pwm { 195 compatible = "st,stm32-pwm"; 196 #pwm-cells = <3>; 197 status = "disabled"; 198 }; 199 200 timer@2 { 201 compatible = "st,stm32h7-timer-trigger"; 202 reg = <2>; 203 status = "disabled"; 204 }; 205 206 counter { 207 compatible = "st,stm32-timer-counter"; 208 status = "disabled"; 209 }; 210 }; 211 212 timers4: timer@40002000 { 213 #address-cells = <1>; 214 #size-cells = <0>; 215 compatible = "st,stm32-timers"; 216 reg = <0x40002000 0x400>; 217 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 218 interrupt-names = "global"; 219 clocks = <&rcc TIM4_K>; 220 clock-names = "int"; 221 dmas = <&dmamux1 29 0x400 0x1>, 222 <&dmamux1 30 0x400 0x1>, 223 <&dmamux1 31 0x400 0x1>, 224 <&dmamux1 32 0x400 0x1>; 225 dma-names = "ch1", "ch2", "ch3", "up"; 226 status = "disabled"; 227 228 pwm { 229 compatible = "st,stm32-pwm"; 230 #pwm-cells = <3>; 231 status = "disabled"; 232 }; 233 234 timer@3 { 235 compatible = "st,stm32h7-timer-trigger"; 236 reg = <3>; 237 status = "disabled"; 238 }; 239 240 counter { 241 compatible = "st,stm32-timer-counter"; 242 status = "disabled"; 243 }; 244 }; 245 246 timers5: timer@40003000 { 247 #address-cells = <1>; 248 #size-cells = <0>; 249 compatible = "st,stm32-timers"; 250 reg = <0x40003000 0x400>; 251 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; 252 interrupt-names = "global"; 253 clocks = <&rcc TIM5_K>; 254 clock-names = "int"; 255 dmas = <&dmamux1 55 0x400 0x1>, 256 <&dmamux1 56 0x400 0x1>, 257 <&dmamux1 57 0x400 0x1>, 258 <&dmamux1 58 0x400 0x1>, 259 <&dmamux1 59 0x400 0x1>, 260 <&dmamux1 60 0x400 0x1>; 261 dma-names = "ch1", "ch2", "ch3", "ch4", "up", "trig"; 262 status = "disabled"; 263 264 pwm { 265 compatible = "st,stm32-pwm"; 266 #pwm-cells = <3>; 267 status = "disabled"; 268 }; 269 270 timer@4 { 271 compatible = "st,stm32h7-timer-trigger"; 272 reg = <4>; 273 status = "disabled"; 274 }; 275 276 counter { 277 compatible = "st,stm32-timer-counter"; 278 status = "disabled"; 279 }; 280 }; 281 282 timers6: timer@40004000 { 283 #address-cells = <1>; 284 #size-cells = <0>; 285 compatible = "st,stm32-timers"; 286 reg = <0x40004000 0x400>; 287 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; 288 interrupt-names = "global"; 289 clocks = <&rcc TIM6_K>; 290 clock-names = "int"; 291 dmas = <&dmamux1 69 0x400 0x1>; 292 dma-names = "up"; 293 status = "disabled"; 294 295 counter { 296 compatible = "st,stm32-timer-counter"; 297 status = "disabled"; 298 }; 299 300 timer@5 { 301 compatible = "st,stm32h7-timer-trigger"; 302 reg = <5>; 303 status = "disabled"; 304 }; 305 }; 306 307 timers7: timer@40005000 { 308 #address-cells = <1>; 309 #size-cells = <0>; 310 compatible = "st,stm32-timers"; 311 reg = <0x40005000 0x400>; 312 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; 313 interrupt-names = "global"; 314 clocks = <&rcc TIM7_K>; 315 clock-names = "int"; 316 dmas = <&dmamux1 70 0x400 0x1>; 317 dma-names = "up"; 318 status = "disabled"; 319 320 counter { 321 compatible = "st,stm32-timer-counter"; 322 status = "disabled"; 323 }; 324 325 timer@6 { 326 compatible = "st,stm32h7-timer-trigger"; 327 reg = <6>; 328 status = "disabled"; 329 }; 330 }; 331 332 lptimer1: timer@40009000 { 333 #address-cells = <1>; 334 #size-cells = <0>; 335 compatible = "st,stm32-lptimer"; 336 reg = <0x40009000 0x400>; 337 interrupts-extended = <&exti 47 IRQ_TYPE_LEVEL_HIGH>; 338 clocks = <&rcc LPTIM1_K>; 339 clock-names = "mux"; 340 wakeup-source; 341 status = "disabled"; 342 343 pwm { 344 compatible = "st,stm32-pwm-lp"; 345 #pwm-cells = <3>; 346 status = "disabled"; 347 }; 348 349 trigger@0 { 350 compatible = "st,stm32-lptimer-trigger"; 351 reg = <0>; 352 status = "disabled"; 353 }; 354 355 counter { 356 compatible = "st,stm32-lptimer-counter"; 357 status = "disabled"; 358 }; 359 360 timer { 361 compatible = "st,stm32-lptimer-timer"; 362 status = "disabled"; 363 }; 364 }; 365 366 i2s2: audio-controller@4000b000 { 367 compatible = "st,stm32h7-i2s"; 368 reg = <0x4000b000 0x400>; 369 #sound-dai-cells = <0>; 370 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 371 dmas = <&dmamux1 39 0x400 0x01>, 372 <&dmamux1 40 0x400 0x01>; 373 dma-names = "rx", "tx"; 374 status = "disabled"; 375 }; 376 377 spi2: spi@4000b000 { 378 compatible = "st,stm32h7-spi"; 379 reg = <0x4000b000 0x400>; 380 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 381 clocks = <&rcc SPI2_K>; 382 resets = <&rcc SPI2_R>; 383 #address-cells = <1>; 384 #size-cells = <0>; 385 dmas = <&dmamux1 39 0x400 0x01>, 386 <&dmamux1 40 0x400 0x01>; 387 dma-names = "rx", "tx"; 388 status = "disabled"; 389 }; 390 391 i2s3: audio-controller@4000c000 { 392 compatible = "st,stm32h7-i2s"; 393 reg = <0x4000c000 0x400>; 394 #sound-dai-cells = <0>; 395 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; 396 dmas = <&dmamux1 61 0x400 0x01>, 397 <&dmamux1 62 0x400 0x01>; 398 dma-names = "rx", "tx"; 399 status = "disabled"; 400 }; 401 402 spi3: spi@4000c000 { 403 compatible = "st,stm32h7-spi"; 404 reg = <0x4000c000 0x400>; 405 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; 406 clocks = <&rcc SPI3_K>; 407 resets = <&rcc SPI3_R>; 408 #address-cells = <1>; 409 #size-cells = <0>; 410 dmas = <&dmamux1 61 0x400 0x01>, 411 <&dmamux1 62 0x400 0x01>; 412 dma-names = "rx", "tx"; 413 status = "disabled"; 414 }; 415 416 spdifrx: audio-controller@4000d000 { 417 compatible = "st,stm32h7-spdifrx"; 418 reg = <0x4000d000 0x400>; 419 #sound-dai-cells = <0>; 420 clocks = <&rcc SPDIF_K>; 421 clock-names = "kclk"; 422 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 423 dmas = <&dmamux1 93 0x400 0x01>, 424 <&dmamux1 94 0x400 0x01>; 425 dma-names = "rx", "rx-ctrl"; 426 status = "disabled"; 427 }; 428 429 usart3: serial@4000f000 { 430 compatible = "st,stm32h7-uart"; 431 reg = <0x4000f000 0x400>; 432 interrupts-extended = <&exti 28 IRQ_TYPE_LEVEL_HIGH>; 433 clocks = <&rcc USART3_K>; 434 resets = <&rcc USART3_R>; 435 wakeup-source; 436 dmas = <&dmamux1 45 0x400 0x5>, 437 <&dmamux1 46 0x400 0x1>; 438 dma-names = "rx", "tx"; 439 status = "disabled"; 440 }; 441 442 uart4: serial@40010000 { 443 compatible = "st,stm32h7-uart"; 444 reg = <0x40010000 0x400>; 445 interrupts-extended = <&exti 30 IRQ_TYPE_LEVEL_HIGH>; 446 clocks = <&rcc UART4_K>; 447 resets = <&rcc UART4_R>; 448 wakeup-source; 449 dmas = <&dmamux1 63 0x400 0x5>, 450 <&dmamux1 64 0x400 0x1>; 451 dma-names = "rx", "tx"; 452 status = "disabled"; 453 }; 454 455 uart5: serial@40011000 { 456 compatible = "st,stm32h7-uart"; 457 reg = <0x40011000 0x400>; 458 interrupts-extended = <&exti 31 IRQ_TYPE_LEVEL_HIGH>; 459 clocks = <&rcc UART5_K>; 460 resets = <&rcc UART5_R>; 461 wakeup-source; 462 dmas = <&dmamux1 65 0x400 0x5>, 463 <&dmamux1 66 0x400 0x1>; 464 dma-names = "rx", "tx"; 465 status = "disabled"; 466 }; 467 468 i2c1: i2c@40012000 { 469 compatible = "st,stm32mp13-i2c"; 470 reg = <0x40012000 0x400>; 471 interrupt-names = "event", "error"; 472 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, 473 <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 474 clocks = <&rcc I2C1_K>; 475 resets = <&rcc I2C1_R>; 476 #address-cells = <1>; 477 #size-cells = <0>; 478 dmas = <&dmamux1 33 0x400 0x1>, 479 <&dmamux1 34 0x400 0x1>; 480 dma-names = "rx", "tx"; 481 st,syscfg-fmp = <&syscfg 0x4 0x1>; 482 i2c-analog-filter; 483 status = "disabled"; 484 }; 485 486 i2c2: i2c@40013000 { 487 compatible = "st,stm32mp13-i2c"; 488 reg = <0x40013000 0x400>; 489 interrupt-names = "event", "error"; 490 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>, 491 <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 492 clocks = <&rcc I2C2_K>; 493 resets = <&rcc I2C2_R>; 494 #address-cells = <1>; 495 #size-cells = <0>; 496 dmas = <&dmamux1 35 0x400 0x1>, 497 <&dmamux1 36 0x400 0x1>; 498 dma-names = "rx", "tx"; 499 st,syscfg-fmp = <&syscfg 0x4 0x2>; 500 i2c-analog-filter; 501 status = "disabled"; 502 }; 503 504 uart7: serial@40018000 { 505 compatible = "st,stm32h7-uart"; 506 reg = <0x40018000 0x400>; 507 interrupts-extended = <&exti 32 IRQ_TYPE_LEVEL_HIGH>; 508 clocks = <&rcc UART7_K>; 509 resets = <&rcc UART7_R>; 510 wakeup-source; 511 dmas = <&dmamux1 79 0x400 0x5>, 512 <&dmamux1 80 0x400 0x1>; 513 dma-names = "rx", "tx"; 514 status = "disabled"; 515 }; 516 517 uart8: serial@40019000 { 518 compatible = "st,stm32h7-uart"; 519 reg = <0x40019000 0x400>; 520 interrupts-extended = <&exti 33 IRQ_TYPE_LEVEL_HIGH>; 521 clocks = <&rcc UART8_K>; 522 resets = <&rcc UART8_R>; 523 wakeup-source; 524 dmas = <&dmamux1 81 0x400 0x5>, 525 <&dmamux1 82 0x400 0x1>; 526 dma-names = "rx", "tx"; 527 status = "disabled"; 528 }; 529 530 timers1: timer@44000000 { 531 #address-cells = <1>; 532 #size-cells = <0>; 533 compatible = "st,stm32-timers"; 534 reg = <0x44000000 0x400>; 535 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>, 536 <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>, 537 <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>, 538 <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 539 interrupt-names = "brk", "up", "trg-com", "cc"; 540 clocks = <&rcc TIM1_K>; 541 clock-names = "int"; 542 dmas = <&dmamux1 11 0x400 0x1>, 543 <&dmamux1 12 0x400 0x1>, 544 <&dmamux1 13 0x400 0x1>, 545 <&dmamux1 14 0x400 0x1>, 546 <&dmamux1 15 0x400 0x1>, 547 <&dmamux1 16 0x400 0x1>, 548 <&dmamux1 17 0x400 0x1>; 549 dma-names = "ch1", "ch2", "ch3", "ch4", 550 "up", "trig", "com"; 551 status = "disabled"; 552 553 pwm { 554 compatible = "st,stm32-pwm"; 555 #pwm-cells = <3>; 556 status = "disabled"; 557 }; 558 559 timer@0 { 560 compatible = "st,stm32h7-timer-trigger"; 561 reg = <0>; 562 status = "disabled"; 563 }; 564 565 counter { 566 compatible = "st,stm32-timer-counter"; 567 status = "disabled"; 568 }; 569 }; 570 571 timers8: timer@44001000 { 572 #address-cells = <1>; 573 #size-cells = <0>; 574 compatible = "st,stm32-timers"; 575 reg = <0x44001000 0x400>; 576 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>, 577 <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>, 578 <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>, 579 <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; 580 interrupt-names = "brk", "up", "trg-com", "cc"; 581 clocks = <&rcc TIM8_K>; 582 clock-names = "int"; 583 dmas = <&dmamux1 47 0x400 0x1>, 584 <&dmamux1 48 0x400 0x1>, 585 <&dmamux1 49 0x400 0x1>, 586 <&dmamux1 50 0x400 0x1>, 587 <&dmamux1 51 0x400 0x1>, 588 <&dmamux1 52 0x400 0x1>, 589 <&dmamux1 53 0x400 0x1>; 590 dma-names = "ch1", "ch2", "ch3", "ch4", 591 "up", "trig", "com"; 592 status = "disabled"; 593 594 pwm { 595 compatible = "st,stm32-pwm"; 596 #pwm-cells = <3>; 597 status = "disabled"; 598 }; 599 600 timer@7 { 601 compatible = "st,stm32h7-timer-trigger"; 602 reg = <7>; 603 status = "disabled"; 604 }; 605 606 counter { 607 compatible = "st,stm32-timer-counter"; 608 status = "disabled"; 609 }; 610 }; 611 612 usart6: serial@44003000 { 613 compatible = "st,stm32h7-uart"; 614 reg = <0x44003000 0x400>; 615 interrupts-extended = <&exti 29 IRQ_TYPE_LEVEL_HIGH>; 616 clocks = <&rcc USART6_K>; 617 resets = <&rcc USART6_R>; 618 wakeup-source; 619 dmas = <&dmamux1 71 0x400 0x5>, 620 <&dmamux1 72 0x400 0x1>; 621 dma-names = "rx", "tx"; 622 status = "disabled"; 623 }; 624 625 i2s1: audio-controller@44004000 { 626 compatible = "st,stm32h7-i2s"; 627 reg = <0x44004000 0x400>; 628 #sound-dai-cells = <0>; 629 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 630 dmas = <&dmamux1 37 0x400 0x01>, 631 <&dmamux1 38 0x400 0x01>; 632 dma-names = "rx", "tx"; 633 status = "disabled"; 634 }; 635 636 spi1: spi@44004000 { 637 compatible = "st,stm32h7-spi"; 638 reg = <0x44004000 0x400>; 639 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 640 clocks = <&rcc SPI1_K>; 641 resets = <&rcc SPI1_R>; 642 #address-cells = <1>; 643 #size-cells = <0>; 644 dmas = <&dmamux1 37 0x400 0x01>, 645 <&dmamux1 38 0x400 0x01>; 646 dma-names = "rx", "tx"; 647 status = "disabled"; 648 }; 649 650 sai1: sai@4400a000 { 651 compatible = "st,stm32h7-sai"; 652 reg = <0x4400a000 0x4>, <0x4400a3f0 0x10>; 653 ranges = <0 0x4400a000 0x400>; 654 #address-cells = <1>; 655 #size-cells = <1>; 656 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; 657 resets = <&rcc SAI1_R>; 658 status = "disabled"; 659 660 sai1a: audio-controller@4400a004 { 661 compatible = "st,stm32-sai-sub-a"; 662 reg = <0x4 0x20>; 663 #sound-dai-cells = <0>; 664 clocks = <&rcc SAI1_K>; 665 clock-names = "sai_ck"; 666 dmas = <&dmamux1 87 0x400 0x01>; 667 status = "disabled"; 668 }; 669 670 sai1b: audio-controller@4400a024 { 671 compatible = "st,stm32-sai-sub-b"; 672 reg = <0x24 0x20>; 673 #sound-dai-cells = <0>; 674 clocks = <&rcc SAI1_K>; 675 clock-names = "sai_ck"; 676 dmas = <&dmamux1 88 0x400 0x01>; 677 status = "disabled"; 678 }; 679 }; 680 681 sai2: sai@4400b000 { 682 compatible = "st,stm32h7-sai"; 683 reg = <0x4400b000 0x4>, <0x4400b3f0 0x10>; 684 ranges = <0 0x4400b000 0x400>; 685 #address-cells = <1>; 686 #size-cells = <1>; 687 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; 688 resets = <&rcc SAI2_R>; 689 status = "disabled"; 690 691 sai2a: audio-controller@4400b004 { 692 compatible = "st,stm32-sai-sub-a"; 693 reg = <0x4 0x20>; 694 #sound-dai-cells = <0>; 695 clocks = <&rcc SAI2_K>; 696 clock-names = "sai_ck"; 697 dmas = <&dmamux1 89 0x400 0x01>; 698 status = "disabled"; 699 }; 700 701 sai2b: audio-controller@4400b024 { 702 compatible = "st,stm32-sai-sub-b"; 703 reg = <0x24 0x20>; 704 #sound-dai-cells = <0>; 705 clocks = <&rcc SAI2_K>; 706 clock-names = "sai_ck"; 707 dmas = <&dmamux1 90 0x400 0x01>; 708 status = "disabled"; 709 }; 710 }; 711 712 dfsdm: dfsdm@4400d000 { 713 compatible = "st,stm32mp1-dfsdm"; 714 reg = <0x4400d000 0x800>; 715 clocks = <&rcc DFSDM_K>; 716 clock-names = "dfsdm"; 717 #address-cells = <1>; 718 #size-cells = <0>; 719 status = "disabled"; 720 721 dfsdm0: filter@0 { 722 compatible = "st,stm32-dfsdm-adc"; 723 reg = <0>; 724 #io-channel-cells = <1>; 725 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; 726 dmas = <&dmamux1 101 0x400 0x01>; 727 dma-names = "rx"; 728 status = "disabled"; 729 }; 730 731 dfsdm1: filter@1 { 732 compatible = "st,stm32-dfsdm-adc"; 733 reg = <1>; 734 #io-channel-cells = <1>; 735 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>; 736 dmas = <&dmamux1 102 0x400 0x01>; 737 dma-names = "rx"; 738 status = "disabled"; 739 }; 740 }; 741 742 dma1: dma-controller@48000000 { 743 compatible = "st,stm32-dma"; 744 reg = <0x48000000 0x400>; 745 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, 746 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 747 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, 748 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, 749 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, 750 <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, 751 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, 752 <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; 753 clocks = <&rcc DMA1>; 754 resets = <&rcc DMA1_R>; 755 #dma-cells = <4>; 756 st,mem2mem; 757 dma-requests = <8>; 758 }; 759 760 dma2: dma-controller@48001000 { 761 compatible = "st,stm32-dma"; 762 reg = <0x48001000 0x400>; 763 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, 764 <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>, 765 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, 766 <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>, 767 <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>, 768 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>, 769 <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, 770 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 771 clocks = <&rcc DMA2>; 772 resets = <&rcc DMA2_R>; 773 #dma-cells = <4>; 774 st,mem2mem; 775 dma-requests = <8>; 776 }; 777 778 dmamux1: dma-router@48002000 { 779 compatible = "st,stm32h7-dmamux"; 780 reg = <0x48002000 0x40>; 781 clocks = <&rcc DMAMUX1>; 782 resets = <&rcc DMAMUX1_R>; 783 #dma-cells = <3>; 784 dma-masters = <&dma1 &dma2>; 785 dma-requests = <128>; 786 dma-channels = <16>; 787 }; 788 789 rcc: rcc@50000000 { 790 compatible = "st,stm32mp13-rcc", "syscon"; 791 reg = <0x50000000 0x1000>; 792 #clock-cells = <1>; 793 #reset-cells = <1>; 794 clock-names = "hse", "hsi", "csi", "lse", "lsi"; 795 clocks = <&scmi_clk CK_SCMI_HSE>, 796 <&scmi_clk CK_SCMI_HSI>, 797 <&scmi_clk CK_SCMI_CSI>, 798 <&scmi_clk CK_SCMI_LSE>, 799 <&scmi_clk CK_SCMI_LSI>; 800 }; 801 802 pwr_regulators: pwr@50001000 { 803 compatible = "st,stm32mp1,pwr-reg"; 804 reg = <0x50001000 0x10>; 805 status = "disabled"; 806 807 reg11: reg11 { 808 regulator-name = "reg11"; 809 regulator-min-microvolt = <1100000>; 810 regulator-max-microvolt = <1100000>; 811 }; 812 813 reg18: reg18 { 814 regulator-name = "reg18"; 815 regulator-min-microvolt = <1800000>; 816 regulator-max-microvolt = <1800000>; 817 }; 818 819 usb33: usb33 { 820 regulator-name = "usb33"; 821 regulator-min-microvolt = <3300000>; 822 regulator-max-microvolt = <3300000>; 823 }; 824 }; 825 826 exti: interrupt-controller@5000d000 { 827 compatible = "st,stm32mp1-exti", "syscon"; 828 interrupt-controller; 829 #interrupt-cells = <2>; 830 reg = <0x5000d000 0x400>; 831 interrupts-extended = 832 <&intc GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, /* EXTI_0 */ 833 <&intc GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 834 <&intc GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 835 <&intc GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, 836 <&intc GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, 837 <&intc GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>, 838 <&intc GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 839 <&intc GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>, 840 <&intc GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>, 841 <&intc GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, 842 <&intc GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, /* EXTI_10 */ 843 <&intc GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>, 844 <&intc GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>, 845 <&intc GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>, 846 <&intc GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 847 <&intc GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 848 <&intc GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 849 <0>, 850 <0>, 851 <&intc GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 852 <0>, /* EXTI_20 */ 853 <&intc GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, 854 <&intc GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>, 855 <&intc GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>, 856 <&intc GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>, 857 <&intc GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 858 <&intc GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>, 859 <&intc GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, 860 <&intc GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, 861 <&intc GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, 862 <&intc GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, /* EXTI_30 */ 863 <&intc GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>, 864 <&intc GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>, 865 <&intc GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, 866 <0>, 867 <0>, 868 <0>, 869 <0>, 870 <0>, 871 <0>, 872 <0>, /* EXTI_40 */ 873 <0>, 874 <0>, 875 <0>, 876 <&intc GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, 877 <0>, 878 <0>, 879 <&intc GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>, 880 <&intc GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 881 <0>, 882 <&intc GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, /* EXTI_50 */ 883 <0>, 884 <&intc GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 885 <&intc GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, 886 <0>, 887 <0>, 888 <0>, 889 <0>, 890 <0>, 891 <0>, 892 <0>, /* EXTI_60 */ 893 <0>, 894 <0>, 895 <0>, 896 <0>, 897 <0>, 898 <0>, 899 <0>, 900 <&intc GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>, 901 <0>, 902 <&intc GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; /* EXTI_70 */ 903 }; 904 905 syscfg: syscon@50020000 { 906 compatible = "st,stm32mp157-syscfg", "syscon"; 907 reg = <0x50020000 0x400>; 908 clocks = <&rcc SYSCFG>; 909 }; 910 911 lptimer4: timer@50023000 { 912 compatible = "st,stm32-lptimer"; 913 reg = <0x50023000 0x400>; 914 interrupts-extended = <&exti 52 IRQ_TYPE_LEVEL_HIGH>; 915 clocks = <&rcc LPTIM4_K>; 916 clock-names = "mux"; 917 wakeup-source; 918 status = "disabled"; 919 920 pwm { 921 compatible = "st,stm32-pwm-lp"; 922 #pwm-cells = <3>; 923 status = "disabled"; 924 }; 925 926 timer { 927 compatible = "st,stm32-lptimer-timer"; 928 status = "disabled"; 929 }; 930 }; 931 932 lptimer5: timer@50024000 { 933 compatible = "st,stm32-lptimer"; 934 reg = <0x50024000 0x400>; 935 interrupts-extended = <&exti 53 IRQ_TYPE_LEVEL_HIGH>; 936 clocks = <&rcc LPTIM5_K>; 937 clock-names = "mux"; 938 wakeup-source; 939 status = "disabled"; 940 941 pwm { 942 compatible = "st,stm32-pwm-lp"; 943 #pwm-cells = <3>; 944 status = "disabled"; 945 }; 946 947 timer { 948 compatible = "st,stm32-lptimer-timer"; 949 status = "disabled"; 950 }; 951 }; 952 953 dts: thermal@50028000 { 954 compatible = "st,stm32-thermal"; 955 reg = <0x50028000 0x100>; 956 interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>; 957 clocks = <&rcc DTS>; 958 clock-names = "pclk"; 959 #thermal-sensor-cells = <0>; 960 status = "disabled"; 961 }; 962 963 hdp: pinctrl@5002a000 { 964 compatible = "st,stm32mp131-hdp"; 965 reg = <0x5002a000 0x400>; 966 clocks = <&rcc HDP>; 967 status = "disabled"; 968 }; 969 970 mdma: dma-controller@58000000 { 971 compatible = "st,stm32h7-mdma"; 972 reg = <0x58000000 0x1000>; 973 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; 974 clocks = <&rcc MDMA>; 975 #dma-cells = <5>; 976 dma-channels = <32>; 977 dma-requests = <48>; 978 }; 979 980 crc1: crc@58009000 { 981 compatible = "st,stm32f7-crc"; 982 reg = <0x58009000 0x400>; 983 clocks = <&rcc CRC1>; 984 status = "disabled"; 985 }; 986 987 usbh_ohci: usb@5800c000 { 988 compatible = "generic-ohci"; 989 reg = <0x5800c000 0x1000>; 990 clocks = <&usbphyc>, <&rcc USBH>; 991 resets = <&rcc USBH_R>; 992 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 993 status = "disabled"; 994 }; 995 996 usbh_ehci: usb@5800d000 { 997 compatible = "generic-ehci"; 998 reg = <0x5800d000 0x1000>; 999 clocks = <&usbphyc>, <&rcc USBH>; 1000 resets = <&rcc USBH_R>; 1001 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; 1002 companion = <&usbh_ohci>; 1003 status = "disabled"; 1004 }; 1005 1006 iwdg2: watchdog@5a002000 { 1007 compatible = "st,stm32mp1-iwdg"; 1008 reg = <0x5a002000 0x400>; 1009 interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; 1010 clocks = <&rcc IWDG2>, <&scmi_clk CK_SCMI_LSI>; 1011 clock-names = "pclk", "lsi"; 1012 status = "disabled"; 1013 }; 1014 1015 rtc: rtc@5c004000 { 1016 compatible = "st,stm32mp1-rtc"; 1017 reg = <0x5c004000 0x400>; 1018 interrupts-extended = <&exti 19 IRQ_TYPE_LEVEL_HIGH>; 1019 clocks = <&scmi_clk CK_SCMI_RTCAPB>, 1020 <&scmi_clk CK_SCMI_RTC>; 1021 clock-names = "pclk", "rtc_ck"; 1022 status = "disabled"; 1023 }; 1024 1025 bsec: efuse@5c005000 { 1026 compatible = "st,stm32mp13-bsec"; 1027 reg = <0x5c005000 0x400>; 1028 #address-cells = <1>; 1029 #size-cells = <1>; 1030 1031 part_number_otp: part_number_otp@4 { 1032 reg = <0x4 0x2>; 1033 bits = <0 12>; 1034 }; 1035 vrefint: vrefin-cal@52 { 1036 reg = <0x52 0x2>; 1037 }; 1038 ts_cal1: calib@5c { 1039 reg = <0x5c 0x2>; 1040 }; 1041 ts_cal2: calib@5e { 1042 reg = <0x5e 0x2>; 1043 }; 1044 ethernet_mac1_address: mac1@e4 { 1045 reg = <0xe4 0x6>; 1046 }; 1047 ethernet_mac2_address: mac2@ea { 1048 reg = <0xea 0x6>; 1049 }; 1050 }; 1051 1052 etzpc: bus@5c007000 { 1053 compatible = "st,stm32-etzpc", "simple-bus"; 1054 reg = <0x5c007000 0x400>; 1055 #address-cells = <1>; 1056 #size-cells = <1>; 1057 #access-controller-cells = <1>; 1058 ranges; 1059 1060 adc_2: adc@48004000 { 1061 compatible = "st,stm32mp13-adc-core"; 1062 reg = <0x48004000 0x400>; 1063 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 1064 clocks = <&rcc ADC2>, <&rcc ADC2_K>; 1065 clock-names = "bus", "adc"; 1066 interrupt-controller; 1067 #interrupt-cells = <1>; 1068 #address-cells = <1>; 1069 #size-cells = <0>; 1070 access-controllers = <&etzpc 33>; 1071 status = "disabled"; 1072 1073 adc2: adc@0 { 1074 compatible = "st,stm32mp13-adc"; 1075 #io-channel-cells = <1>; 1076 #address-cells = <1>; 1077 #size-cells = <0>; 1078 reg = <0x0>; 1079 interrupt-parent = <&adc_2>; 1080 interrupts = <0>; 1081 dmas = <&dmamux1 10 0x400 0x80000001>; 1082 dma-names = "rx"; 1083 nvmem-cells = <&vrefint>; 1084 nvmem-cell-names = "vrefint"; 1085 status = "disabled"; 1086 1087 channel@13 { 1088 reg = <13>; 1089 label = "vrefint"; 1090 }; 1091 channel@14 { 1092 reg = <14>; 1093 label = "vddcore"; 1094 }; 1095 channel@16 { 1096 reg = <16>; 1097 label = "vddcpu"; 1098 }; 1099 channel@17 { 1100 reg = <17>; 1101 label = "vddq_ddr"; 1102 }; 1103 }; 1104 }; 1105 1106 usbotg_hs: usb@49000000 { 1107 compatible = "st,stm32mp15-hsotg", "snps,dwc2"; 1108 reg = <0x49000000 0x40000>; 1109 clocks = <&rcc USBO_K>; 1110 clock-names = "otg"; 1111 resets = <&rcc USBO_R>; 1112 reset-names = "dwc2"; 1113 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 1114 g-rx-fifo-size = <512>; 1115 g-np-tx-fifo-size = <32>; 1116 g-tx-fifo-size = <256 16 16 16 16 16 16 16>; 1117 dr_mode = "otg"; 1118 otg-rev = <0x200>; 1119 usb33d-supply = <&scmi_usb33>; 1120 access-controllers = <&etzpc 34>; 1121 status = "disabled"; 1122 }; 1123 1124 usart1: serial@4c000000 { 1125 compatible = "st,stm32h7-uart"; 1126 reg = <0x4c000000 0x400>; 1127 interrupts-extended = <&exti 26 IRQ_TYPE_LEVEL_HIGH>; 1128 clocks = <&rcc USART1_K>; 1129 resets = <&rcc USART1_R>; 1130 wakeup-source; 1131 dmas = <&dmamux1 41 0x400 0x5>, 1132 <&dmamux1 42 0x400 0x1>; 1133 dma-names = "rx", "tx"; 1134 access-controllers = <&etzpc 16>; 1135 status = "disabled"; 1136 }; 1137 1138 usart2: serial@4c001000 { 1139 compatible = "st,stm32h7-uart"; 1140 reg = <0x4c001000 0x400>; 1141 interrupts-extended = <&exti 27 IRQ_TYPE_LEVEL_HIGH>; 1142 clocks = <&rcc USART2_K>; 1143 resets = <&rcc USART2_R>; 1144 wakeup-source; 1145 dmas = <&dmamux1 43 0x400 0x5>, 1146 <&dmamux1 44 0x400 0x1>; 1147 dma-names = "rx", "tx"; 1148 access-controllers = <&etzpc 17>; 1149 status = "disabled"; 1150 }; 1151 1152 i2s4: audio-controller@4c002000 { 1153 compatible = "st,stm32h7-i2s"; 1154 reg = <0x4c002000 0x400>; 1155 #sound-dai-cells = <0>; 1156 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; 1157 dmas = <&dmamux1 83 0x400 0x01>, 1158 <&dmamux1 84 0x400 0x01>; 1159 dma-names = "rx", "tx"; 1160 access-controllers = <&etzpc 13>; 1161 status = "disabled"; 1162 }; 1163 1164 spi4: spi@4c002000 { 1165 compatible = "st,stm32h7-spi"; 1166 reg = <0x4c002000 0x400>; 1167 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; 1168 clocks = <&rcc SPI4_K>; 1169 resets = <&rcc SPI4_R>; 1170 #address-cells = <1>; 1171 #size-cells = <0>; 1172 dmas = <&dmamux1 83 0x400 0x01>, 1173 <&dmamux1 84 0x400 0x01>; 1174 dma-names = "rx", "tx"; 1175 access-controllers = <&etzpc 18>; 1176 status = "disabled"; 1177 }; 1178 1179 spi5: spi@4c003000 { 1180 compatible = "st,stm32h7-spi"; 1181 reg = <0x4c003000 0x400>; 1182 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 1183 clocks = <&rcc SPI5_K>; 1184 resets = <&rcc SPI5_R>; 1185 #address-cells = <1>; 1186 #size-cells = <0>; 1187 dmas = <&dmamux1 85 0x400 0x01>, 1188 <&dmamux1 86 0x400 0x01>; 1189 dma-names = "rx", "tx"; 1190 access-controllers = <&etzpc 19>; 1191 status = "disabled"; 1192 }; 1193 1194 i2c3: i2c@4c004000 { 1195 compatible = "st,stm32mp13-i2c"; 1196 reg = <0x4c004000 0x400>; 1197 interrupt-names = "event", "error"; 1198 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>, 1199 <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 1200 clocks = <&rcc I2C3_K>; 1201 resets = <&rcc I2C3_R>; 1202 #address-cells = <1>; 1203 #size-cells = <0>; 1204 dmas = <&dmamux1 73 0x400 0x1>, 1205 <&dmamux1 74 0x400 0x1>; 1206 dma-names = "rx", "tx"; 1207 st,syscfg-fmp = <&syscfg 0x4 0x4>; 1208 i2c-analog-filter; 1209 access-controllers = <&etzpc 20>; 1210 status = "disabled"; 1211 }; 1212 1213 i2c4: i2c@4c005000 { 1214 compatible = "st,stm32mp13-i2c"; 1215 reg = <0x4c005000 0x400>; 1216 interrupt-names = "event", "error"; 1217 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>, 1218 <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; 1219 clocks = <&rcc I2C4_K>; 1220 resets = <&rcc I2C4_R>; 1221 #address-cells = <1>; 1222 #size-cells = <0>; 1223 dmas = <&dmamux1 75 0x400 0x1>, 1224 <&dmamux1 76 0x400 0x1>; 1225 dma-names = "rx", "tx"; 1226 st,syscfg-fmp = <&syscfg 0x4 0x8>; 1227 i2c-analog-filter; 1228 access-controllers = <&etzpc 21>; 1229 status = "disabled"; 1230 }; 1231 1232 i2c5: i2c@4c006000 { 1233 compatible = "st,stm32mp13-i2c"; 1234 reg = <0x4c006000 0x400>; 1235 interrupt-names = "event", "error"; 1236 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 1237 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; 1238 clocks = <&rcc I2C5_K>; 1239 resets = <&rcc I2C5_R>; 1240 #address-cells = <1>; 1241 #size-cells = <0>; 1242 dmas = <&dmamux1 115 0x400 0x1>, 1243 <&dmamux1 116 0x400 0x1>; 1244 dma-names = "rx", "tx"; 1245 st,syscfg-fmp = <&syscfg 0x4 0x10>; 1246 i2c-analog-filter; 1247 access-controllers = <&etzpc 22>; 1248 status = "disabled"; 1249 }; 1250 1251 timers12: timer@4c007000 { 1252 #address-cells = <1>; 1253 #size-cells = <0>; 1254 compatible = "st,stm32-timers"; 1255 reg = <0x4c007000 0x400>; 1256 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>; 1257 interrupt-names = "global"; 1258 clocks = <&rcc TIM12_K>; 1259 clock-names = "int"; 1260 access-controllers = <&etzpc 23>; 1261 status = "disabled"; 1262 1263 counter { 1264 compatible = "st,stm32-timer-counter"; 1265 status = "disabled"; 1266 }; 1267 1268 pwm { 1269 compatible = "st,stm32-pwm"; 1270 #pwm-cells = <3>; 1271 status = "disabled"; 1272 }; 1273 1274 timer@11 { 1275 compatible = "st,stm32h7-timer-trigger"; 1276 reg = <11>; 1277 status = "disabled"; 1278 }; 1279 }; 1280 1281 timers13: timer@4c008000 { 1282 #address-cells = <1>; 1283 #size-cells = <0>; 1284 compatible = "st,stm32-timers"; 1285 reg = <0x4c008000 0x400>; 1286 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>; 1287 interrupt-names = "global"; 1288 clocks = <&rcc TIM13_K>; 1289 clock-names = "int"; 1290 access-controllers = <&etzpc 24>; 1291 status = "disabled"; 1292 1293 counter { 1294 compatible = "st,stm32-timer-counter"; 1295 status = "disabled"; 1296 }; 1297 1298 pwm { 1299 compatible = "st,stm32-pwm"; 1300 #pwm-cells = <3>; 1301 status = "disabled"; 1302 }; 1303 1304 timer@12 { 1305 compatible = "st,stm32h7-timer-trigger"; 1306 reg = <12>; 1307 status = "disabled"; 1308 }; 1309 }; 1310 1311 timers14: timer@4c009000 { 1312 #address-cells = <1>; 1313 #size-cells = <0>; 1314 compatible = "st,stm32-timers"; 1315 reg = <0x4c009000 0x400>; 1316 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 1317 interrupt-names = "global"; 1318 clocks = <&rcc TIM14_K>; 1319 clock-names = "int"; 1320 access-controllers = <&etzpc 25>; 1321 status = "disabled"; 1322 1323 counter { 1324 compatible = "st,stm32-timer-counter"; 1325 status = "disabled"; 1326 }; 1327 1328 pwm { 1329 compatible = "st,stm32-pwm"; 1330 #pwm-cells = <3>; 1331 status = "disabled"; 1332 }; 1333 1334 timer@13 { 1335 compatible = "st,stm32h7-timer-trigger"; 1336 reg = <13>; 1337 status = "disabled"; 1338 }; 1339 }; 1340 1341 timers15: timer@4c00a000 { 1342 #address-cells = <1>; 1343 #size-cells = <0>; 1344 compatible = "st,stm32-timers"; 1345 reg = <0x4c00a000 0x400>; 1346 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; 1347 interrupt-names = "global"; 1348 clocks = <&rcc TIM15_K>; 1349 clock-names = "int"; 1350 dmas = <&dmamux1 105 0x400 0x1>, 1351 <&dmamux1 106 0x400 0x1>, 1352 <&dmamux1 107 0x400 0x1>, 1353 <&dmamux1 108 0x400 0x1>; 1354 dma-names = "ch1", "up", "trig", "com"; 1355 access-controllers = <&etzpc 26>; 1356 status = "disabled"; 1357 1358 counter { 1359 compatible = "st,stm32-timer-counter"; 1360 status = "disabled"; 1361 }; 1362 1363 pwm { 1364 compatible = "st,stm32-pwm"; 1365 #pwm-cells = <3>; 1366 status = "disabled"; 1367 }; 1368 1369 timer@14 { 1370 compatible = "st,stm32h7-timer-trigger"; 1371 reg = <14>; 1372 status = "disabled"; 1373 }; 1374 }; 1375 1376 timers16: timer@4c00b000 { 1377 #address-cells = <1>; 1378 #size-cells = <0>; 1379 compatible = "st,stm32-timers"; 1380 reg = <0x4c00b000 0x400>; 1381 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; 1382 interrupt-names = "global"; 1383 clocks = <&rcc TIM16_K>; 1384 clock-names = "int"; 1385 dmas = <&dmamux1 109 0x400 0x1>, 1386 <&dmamux1 110 0x400 0x1>; 1387 dma-names = "ch1", "up"; 1388 access-controllers = <&etzpc 27>; 1389 status = "disabled"; 1390 1391 counter { 1392 compatible = "st,stm32-timer-counter"; 1393 status = "disabled"; 1394 }; 1395 1396 pwm { 1397 compatible = "st,stm32-pwm"; 1398 #pwm-cells = <3>; 1399 status = "disabled"; 1400 }; 1401 1402 timer@15 { 1403 compatible = "st,stm32h7-timer-trigger"; 1404 reg = <15>; 1405 status = "disabled"; 1406 }; 1407 }; 1408 1409 timers17: timer@4c00c000 { 1410 #address-cells = <1>; 1411 #size-cells = <0>; 1412 compatible = "st,stm32-timers"; 1413 reg = <0x4c00c000 0x400>; 1414 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 1415 interrupt-names = "global"; 1416 clocks = <&rcc TIM17_K>; 1417 clock-names = "int"; 1418 dmas = <&dmamux1 111 0x400 0x1>, 1419 <&dmamux1 112 0x400 0x1>; 1420 dma-names = "ch1", "up"; 1421 access-controllers = <&etzpc 28>; 1422 status = "disabled"; 1423 1424 counter { 1425 compatible = "st,stm32-timer-counter"; 1426 status = "disabled"; 1427 }; 1428 1429 pwm { 1430 compatible = "st,stm32-pwm"; 1431 #pwm-cells = <3>; 1432 status = "disabled"; 1433 }; 1434 1435 timer@16 { 1436 compatible = "st,stm32h7-timer-trigger"; 1437 reg = <16>; 1438 status = "disabled"; 1439 }; 1440 }; 1441 1442 lptimer2: timer@50021000 { 1443 #address-cells = <1>; 1444 #size-cells = <0>; 1445 compatible = "st,stm32-lptimer"; 1446 reg = <0x50021000 0x400>; 1447 interrupts-extended = <&exti 48 IRQ_TYPE_LEVEL_HIGH>; 1448 clocks = <&rcc LPTIM2_K>; 1449 clock-names = "mux"; 1450 wakeup-source; 1451 access-controllers = <&etzpc 1>; 1452 status = "disabled"; 1453 1454 pwm { 1455 compatible = "st,stm32-pwm-lp"; 1456 #pwm-cells = <3>; 1457 status = "disabled"; 1458 }; 1459 1460 trigger@1 { 1461 compatible = "st,stm32-lptimer-trigger"; 1462 reg = <1>; 1463 status = "disabled"; 1464 }; 1465 1466 counter { 1467 compatible = "st,stm32-lptimer-counter"; 1468 status = "disabled"; 1469 }; 1470 1471 timer { 1472 compatible = "st,stm32-lptimer-timer"; 1473 status = "disabled"; 1474 }; 1475 }; 1476 1477 lptimer3: timer@50022000 { 1478 #address-cells = <1>; 1479 #size-cells = <0>; 1480 compatible = "st,stm32-lptimer"; 1481 reg = <0x50022000 0x400>; 1482 interrupts-extended = <&exti 50 IRQ_TYPE_LEVEL_HIGH>; 1483 clocks = <&rcc LPTIM3_K>; 1484 clock-names = "mux"; 1485 wakeup-source; 1486 access-controllers = <&etzpc 2>; 1487 status = "disabled"; 1488 1489 pwm { 1490 compatible = "st,stm32-pwm-lp"; 1491 #pwm-cells = <3>; 1492 status = "disabled"; 1493 }; 1494 1495 trigger@2 { 1496 compatible = "st,stm32-lptimer-trigger"; 1497 reg = <2>; 1498 status = "disabled"; 1499 }; 1500 1501 timer { 1502 compatible = "st,stm32-lptimer-timer"; 1503 status = "disabled"; 1504 }; 1505 }; 1506 1507 hash: hash@54003000 { 1508 compatible = "st,stm32mp13-hash"; 1509 reg = <0x54003000 0x400>; 1510 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 1511 clocks = <&rcc HASH1>; 1512 resets = <&rcc HASH1_R>; 1513 dmas = <&mdma 30 0x2 0x1000a02 0x0 0x0>; 1514 dma-names = "in"; 1515 access-controllers = <&etzpc 41>; 1516 status = "disabled"; 1517 }; 1518 1519 rng: rng@54004000 { 1520 compatible = "st,stm32mp13-rng"; 1521 reg = <0x54004000 0x400>; 1522 clocks = <&rcc RNG1_K>; 1523 resets = <&rcc RNG1_R>; 1524 access-controllers = <&etzpc 40>; 1525 status = "disabled"; 1526 }; 1527 1528 fmc: memory-controller@58002000 { 1529 compatible = "st,stm32mp1-fmc2-ebi"; 1530 reg = <0x58002000 0x1000>; 1531 ranges = <0 0 0x60000000 0x04000000>, /* EBI CS 1 */ 1532 <1 0 0x64000000 0x04000000>, /* EBI CS 2 */ 1533 <2 0 0x68000000 0x04000000>, /* EBI CS 3 */ 1534 <3 0 0x6c000000 0x04000000>, /* EBI CS 4 */ 1535 <4 0 0x80000000 0x10000000>; /* NAND */ 1536 #address-cells = <2>; 1537 #size-cells = <1>; 1538 clocks = <&rcc FMC_K>; 1539 resets = <&rcc FMC_R>; 1540 access-controllers = <&etzpc 54>; 1541 status = "disabled"; 1542 1543 nand-controller@4,0 { 1544 compatible = "st,stm32mp1-fmc2-nfc"; 1545 reg = <4 0x00000000 0x1000>, 1546 <4 0x08010000 0x1000>, 1547 <4 0x08020000 0x1000>, 1548 <4 0x01000000 0x1000>, 1549 <4 0x09010000 0x1000>, 1550 <4 0x09020000 0x1000>; 1551 #address-cells = <1>; 1552 #size-cells = <0>; 1553 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; 1554 dmas = <&mdma 24 0x2 0x12000a02 0x0 0x0>, 1555 <&mdma 24 0x2 0x12000a08 0x0 0x0>, 1556 <&mdma 25 0x2 0x12000a0a 0x0 0x0>; 1557 dma-names = "tx", "rx", "ecc"; 1558 status = "disabled"; 1559 }; 1560 }; 1561 1562 qspi: spi@58003000 { 1563 compatible = "st,stm32f469-qspi"; 1564 reg = <0x58003000 0x1000>, <0x70000000 0x10000000>; 1565 reg-names = "qspi", "qspi_mm"; 1566 #address-cells = <1>; 1567 #size-cells = <0>; 1568 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; 1569 dmas = <&mdma 26 0x2 0x10100002 0x0 0x0>, 1570 <&mdma 26 0x2 0x10100008 0x0 0x0>; 1571 dma-names = "tx", "rx"; 1572 clocks = <&rcc QSPI_K>; 1573 resets = <&rcc QSPI_R>; 1574 access-controllers = <&etzpc 55>; 1575 status = "disabled"; 1576 }; 1577 1578 sdmmc1: mmc@58005000 { 1579 compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell"; 1580 arm,primecell-periphid = <0x20253180>; 1581 reg = <0x58005000 0x1000>, <0x58006000 0x1000>; 1582 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; 1583 clocks = <&rcc SDMMC1_K>; 1584 clock-names = "apb_pclk"; 1585 resets = <&rcc SDMMC1_R>; 1586 cap-sd-highspeed; 1587 cap-mmc-highspeed; 1588 max-frequency = <130000000>; 1589 access-controllers = <&etzpc 50>; 1590 status = "disabled"; 1591 }; 1592 1593 sdmmc2: mmc@58007000 { 1594 compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell"; 1595 arm,primecell-periphid = <0x20253180>; 1596 reg = <0x58007000 0x1000>, <0x58008000 0x1000>; 1597 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 1598 clocks = <&rcc SDMMC2_K>; 1599 clock-names = "apb_pclk"; 1600 resets = <&rcc SDMMC2_R>; 1601 cap-sd-highspeed; 1602 cap-mmc-highspeed; 1603 max-frequency = <130000000>; 1604 access-controllers = <&etzpc 51>; 1605 status = "disabled"; 1606 }; 1607 1608 ethernet1: ethernet@5800a000 { 1609 compatible = "st,stm32mp13-dwmac", "snps,dwmac-4.20a"; 1610 reg = <0x5800a000 0x2000>; 1611 reg-names = "stmmaceth"; 1612 interrupts-extended = <&intc GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>, 1613 <&exti 68 1>; 1614 interrupt-names = "macirq", "eth_wake_irq"; 1615 clock-names = "stmmaceth", 1616 "mac-clk-tx", 1617 "mac-clk-rx", 1618 "ethstp", 1619 "ptp_ref", 1620 "eth-ck"; 1621 clocks = <&rcc ETH1MAC>, 1622 <&rcc ETH1TX>, 1623 <&rcc ETH1RX>, 1624 <&rcc ETH1STP>, 1625 <&rcc ETH1PTP_K>, 1626 <&rcc ETH1CK_K>; 1627 st,syscon = <&syscfg 0x4 0xff0000>; 1628 snps,mixed-burst; 1629 snps,pbl = <2>; 1630 snps,axi-config = <&stmmac_axi_config_1>; 1631 snps,tso; 1632 access-controllers = <&etzpc 48>; 1633 nvmem-cells = <ðernet_mac1_address>; 1634 nvmem-cell-names = "mac-address"; 1635 status = "disabled"; 1636 1637 stmmac_axi_config_1: stmmac-axi-config { 1638 snps,blen = <0 0 0 0 16 8 4>; 1639 snps,rd_osr_lmt = <0x7>; 1640 snps,wr_osr_lmt = <0x7>; 1641 }; 1642 }; 1643 1644 usbphyc: usbphyc@5a006000 { 1645 #address-cells = <1>; 1646 #size-cells = <0>; 1647 #clock-cells = <0>; 1648 compatible = "st,stm32mp1-usbphyc"; 1649 reg = <0x5a006000 0x1000>; 1650 clocks = <&rcc USBPHY_K>; 1651 resets = <&rcc USBPHY_R>; 1652 vdda1v1-supply = <&scmi_reg11>; 1653 vdda1v8-supply = <&scmi_reg18>; 1654 access-controllers = <&etzpc 5>; 1655 status = "disabled"; 1656 1657 usbphyc_port0: usb-phy@0 { 1658 #phy-cells = <0>; 1659 reg = <0>; 1660 }; 1661 1662 usbphyc_port1: usb-phy@1 { 1663 #phy-cells = <1>; 1664 reg = <1>; 1665 }; 1666 }; 1667 1668 iwdg1: watchdog@5c003000 { 1669 compatible = "st,stm32mp1-iwdg"; 1670 reg = <0x5c003000 0x400>; 1671 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>; 1672 clocks = <&rcc IWDG1>, <&scmi_clk CK_SCMI_LSI>; 1673 clock-names = "pclk", "lsi"; 1674 access-controllers = <&etzpc 12>; 1675 status = "disabled"; 1676 }; 1677 }; 1678 1679 /* 1680 * Break node order to solve dependency probe issue between 1681 * pinctrl and exti. 1682 */ 1683 pinctrl: pinctrl@50002000 { 1684 #address-cells = <1>; 1685 #size-cells = <1>; 1686 compatible = "st,stm32mp135-pinctrl"; 1687 ranges = <0 0x50002000 0x8400>; 1688 interrupt-parent = <&exti>; 1689 st,syscfg = <&exti 0x60 0xff>; 1690 1691 gpioa: gpio@50002000 { 1692 gpio-controller; 1693 #gpio-cells = <2>; 1694 interrupt-controller; 1695 #interrupt-cells = <2>; 1696 reg = <0x0 0x400>; 1697 clocks = <&rcc GPIOA>; 1698 st,bank-name = "GPIOA"; 1699 ngpios = <16>; 1700 gpio-ranges = <&pinctrl 0 0 16>; 1701 }; 1702 1703 gpiob: gpio@50003000 { 1704 gpio-controller; 1705 #gpio-cells = <2>; 1706 interrupt-controller; 1707 #interrupt-cells = <2>; 1708 reg = <0x1000 0x400>; 1709 clocks = <&rcc GPIOB>; 1710 st,bank-name = "GPIOB"; 1711 ngpios = <16>; 1712 gpio-ranges = <&pinctrl 0 16 16>; 1713 }; 1714 1715 gpioc: gpio@50004000 { 1716 gpio-controller; 1717 #gpio-cells = <2>; 1718 interrupt-controller; 1719 #interrupt-cells = <2>; 1720 reg = <0x2000 0x400>; 1721 clocks = <&rcc GPIOC>; 1722 st,bank-name = "GPIOC"; 1723 ngpios = <16>; 1724 gpio-ranges = <&pinctrl 0 32 16>; 1725 }; 1726 1727 gpiod: gpio@50005000 { 1728 gpio-controller; 1729 #gpio-cells = <2>; 1730 interrupt-controller; 1731 #interrupt-cells = <2>; 1732 reg = <0x3000 0x400>; 1733 clocks = <&rcc GPIOD>; 1734 st,bank-name = "GPIOD"; 1735 ngpios = <16>; 1736 gpio-ranges = <&pinctrl 0 48 16>; 1737 }; 1738 1739 gpioe: gpio@50006000 { 1740 gpio-controller; 1741 #gpio-cells = <2>; 1742 interrupt-controller; 1743 #interrupt-cells = <2>; 1744 reg = <0x4000 0x400>; 1745 clocks = <&rcc GPIOE>; 1746 st,bank-name = "GPIOE"; 1747 ngpios = <16>; 1748 gpio-ranges = <&pinctrl 0 64 16>; 1749 }; 1750 1751 gpiof: gpio@50007000 { 1752 gpio-controller; 1753 #gpio-cells = <2>; 1754 interrupt-controller; 1755 #interrupt-cells = <2>; 1756 reg = <0x5000 0x400>; 1757 clocks = <&rcc GPIOF>; 1758 st,bank-name = "GPIOF"; 1759 ngpios = <16>; 1760 gpio-ranges = <&pinctrl 0 80 16>; 1761 }; 1762 1763 gpiog: gpio@50008000 { 1764 gpio-controller; 1765 #gpio-cells = <2>; 1766 interrupt-controller; 1767 #interrupt-cells = <2>; 1768 reg = <0x6000 0x400>; 1769 clocks = <&rcc GPIOG>; 1770 st,bank-name = "GPIOG"; 1771 ngpios = <16>; 1772 gpio-ranges = <&pinctrl 0 96 16>; 1773 }; 1774 1775 gpioh: gpio@50009000 { 1776 gpio-controller; 1777 #gpio-cells = <2>; 1778 interrupt-controller; 1779 #interrupt-cells = <2>; 1780 reg = <0x7000 0x400>; 1781 clocks = <&rcc GPIOH>; 1782 st,bank-name = "GPIOH"; 1783 ngpios = <15>; 1784 gpio-ranges = <&pinctrl 0 112 15>; 1785 }; 1786 1787 gpioi: gpio@5000a000 { 1788 gpio-controller; 1789 #gpio-cells = <2>; 1790 interrupt-controller; 1791 #interrupt-cells = <2>; 1792 reg = <0x8000 0x400>; 1793 clocks = <&rcc GPIOI>; 1794 st,bank-name = "GPIOI"; 1795 ngpios = <8>; 1796 gpio-ranges = <&pinctrl 0 128 8>; 1797 }; 1798 }; 1799 }; 1800};
~/
Read-only file preview.