FILE
rk3288.dtsi
File preview with syntax highlighting.
linux-6.19.14/arch/arm/boot/dts/rockchip/rk3288.dtsi
1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2 3#include <dt-bindings/gpio/gpio.h> 4#include <dt-bindings/interrupt-controller/irq.h> 5#include <dt-bindings/interrupt-controller/arm-gic.h> 6#include <dt-bindings/pinctrl/rockchip.h> 7#include <dt-bindings/clock/rk3288-cru.h> 8#include <dt-bindings/power/rk3288-power.h> 9#include <dt-bindings/thermal/thermal.h> 10#include <dt-bindings/soc/rockchip,boot-mode.h> 11 12/ { 13 #address-cells = <2>; 14 #size-cells = <2>; 15 16 compatible = "rockchip,rk3288"; 17 18 interrupt-parent = <&gic>; 19 20 aliases { 21 ethernet0 = &gmac; 22 gpio0 = &gpio0; 23 gpio1 = &gpio1; 24 gpio2 = &gpio2; 25 gpio3 = &gpio3; 26 gpio4 = &gpio4; 27 gpio5 = &gpio5; 28 gpio6 = &gpio6; 29 gpio7 = &gpio7; 30 gpio8 = &gpio8; 31 i2c0 = &i2c0; 32 i2c1 = &i2c1; 33 i2c2 = &i2c2; 34 i2c3 = &i2c3; 35 i2c4 = &i2c4; 36 i2c5 = &i2c5; 37 serial0 = &uart0; 38 serial1 = &uart1; 39 serial2 = &uart2; 40 serial3 = &uart3; 41 serial4 = &uart4; 42 spi0 = &spi0; 43 spi1 = &spi1; 44 spi2 = &spi2; 45 }; 46 47 arm-pmu { 48 compatible = "arm,cortex-a12-pmu"; 49 interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>, 50 <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>, 51 <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, 52 <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; 53 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; 54 }; 55 56 cpus { 57 #address-cells = <1>; 58 #size-cells = <0>; 59 enable-method = "rockchip,rk3066-smp"; 60 rockchip,pmu = <&pmu>; 61 62 cpu0: cpu@500 { 63 device_type = "cpu"; 64 compatible = "arm,cortex-a12"; 65 reg = <0x500>; 66 resets = <&cru SRST_CORE0>; 67 operating-points-v2 = <&cpu_opp_table>; 68 #cooling-cells = <2>; /* min followed by max */ 69 clocks = <&cru ARMCLK>; 70 dynamic-power-coefficient = <370>; 71 }; 72 cpu1: cpu@501 { 73 device_type = "cpu"; 74 compatible = "arm,cortex-a12"; 75 reg = <0x501>; 76 resets = <&cru SRST_CORE1>; 77 operating-points-v2 = <&cpu_opp_table>; 78 #cooling-cells = <2>; /* min followed by max */ 79 clocks = <&cru ARMCLK>; 80 dynamic-power-coefficient = <370>; 81 }; 82 cpu2: cpu@502 { 83 device_type = "cpu"; 84 compatible = "arm,cortex-a12"; 85 reg = <0x502>; 86 resets = <&cru SRST_CORE2>; 87 operating-points-v2 = <&cpu_opp_table>; 88 #cooling-cells = <2>; /* min followed by max */ 89 clocks = <&cru ARMCLK>; 90 dynamic-power-coefficient = <370>; 91 }; 92 cpu3: cpu@503 { 93 device_type = "cpu"; 94 compatible = "arm,cortex-a12"; 95 reg = <0x503>; 96 resets = <&cru SRST_CORE3>; 97 operating-points-v2 = <&cpu_opp_table>; 98 #cooling-cells = <2>; /* min followed by max */ 99 clocks = <&cru ARMCLK>; 100 dynamic-power-coefficient = <370>; 101 }; 102 }; 103 104 cpu_opp_table: opp-table-0 { 105 compatible = "operating-points-v2"; 106 opp-shared; 107 108 opp-126000000 { 109 opp-hz = /bits/ 64 <126000000>; 110 opp-microvolt = <900000>; 111 clock-latency-ns = <40000>; 112 }; 113 opp-216000000 { 114 opp-hz = /bits/ 64 <216000000>; 115 opp-microvolt = <900000>; 116 }; 117 opp-312000000 { 118 opp-hz = /bits/ 64 <312000000>; 119 opp-microvolt = <900000>; 120 }; 121 opp-408000000 { 122 opp-hz = /bits/ 64 <408000000>; 123 opp-microvolt = <900000>; 124 }; 125 opp-600000000 { 126 opp-hz = /bits/ 64 <600000000>; 127 opp-microvolt = <900000>; 128 }; 129 opp-696000000 { 130 opp-hz = /bits/ 64 <696000000>; 131 opp-microvolt = <950000>; 132 }; 133 opp-816000000 { 134 opp-hz = /bits/ 64 <816000000>; 135 opp-microvolt = <1000000>; 136 }; 137 opp-1008000000 { 138 opp-hz = /bits/ 64 <1008000000>; 139 opp-microvolt = <1050000>; 140 }; 141 opp-1200000000 { 142 opp-hz = /bits/ 64 <1200000000>; 143 opp-microvolt = <1100000>; 144 }; 145 opp-1416000000 { 146 opp-hz = /bits/ 64 <1416000000>; 147 opp-microvolt = <1200000>; 148 }; 149 opp-1512000000 { 150 opp-hz = /bits/ 64 <1512000000>; 151 opp-microvolt = <1300000>; 152 }; 153 opp-1608000000 { 154 opp-hz = /bits/ 64 <1608000000>; 155 opp-microvolt = <1350000>; 156 }; 157 }; 158 159 reserved-memory { 160 #address-cells = <2>; 161 #size-cells = <2>; 162 ranges; 163 164 /* 165 * The rk3288 cannot use the memory area above 0xfe000000 166 * for dma operations for some reason. While there is 167 * probably a better solution available somewhere, we 168 * haven't found it yet and while devices with 2GB of ram 169 * are not affected, this issue prevents 4GB from booting. 170 * So to make these devices at least bootable, block 171 * this area for the time being until the real solution 172 * is found. 173 */ 174 dma-unusable@fe000000 { 175 reg = <0x0 0xfe000000 0x0 0x1000000>; 176 }; 177 }; 178 179 xin24m: oscillator { 180 compatible = "fixed-clock"; 181 clock-frequency = <24000000>; 182 clock-output-names = "xin24m"; 183 #clock-cells = <0>; 184 }; 185 186 timer { 187 compatible = "arm,armv7-timer"; 188 arm,cpu-registers-not-fw-configured; 189 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 190 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 191 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 192 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 193 clock-frequency = <24000000>; 194 arm,no-tick-in-suspend; 195 }; 196 197 timer: timer@ff810000 { 198 compatible = "rockchip,rk3288-timer"; 199 reg = <0x0 0xff810000 0x0 0x20>; 200 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 201 clocks = <&cru PCLK_TIMER>, <&xin24m>; 202 clock-names = "pclk", "timer"; 203 }; 204 205 display-subsystem { 206 compatible = "rockchip,display-subsystem"; 207 ports = <&vopl_out>, <&vopb_out>; 208 }; 209 210 sdmmc: mmc@ff0c0000 { 211 compatible = "rockchip,rk3288-dw-mshc"; 212 max-frequency = <150000000>; 213 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>, 214 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>; 215 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 216 fifo-depth = <0x100>; 217 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 218 reg = <0x0 0xff0c0000 0x0 0x4000>; 219 resets = <&cru SRST_MMC0>; 220 reset-names = "reset"; 221 status = "disabled"; 222 }; 223 224 sdio0: mmc@ff0d0000 { 225 compatible = "rockchip,rk3288-dw-mshc"; 226 max-frequency = <150000000>; 227 clocks = <&cru HCLK_SDIO0>, <&cru SCLK_SDIO0>, 228 <&cru SCLK_SDIO0_DRV>, <&cru SCLK_SDIO0_SAMPLE>; 229 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 230 fifo-depth = <0x100>; 231 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 232 reg = <0x0 0xff0d0000 0x0 0x4000>; 233 resets = <&cru SRST_SDIO0>; 234 reset-names = "reset"; 235 status = "disabled"; 236 }; 237 238 sdio1: mmc@ff0e0000 { 239 compatible = "rockchip,rk3288-dw-mshc"; 240 max-frequency = <150000000>; 241 clocks = <&cru HCLK_SDIO1>, <&cru SCLK_SDIO1>, 242 <&cru SCLK_SDIO1_DRV>, <&cru SCLK_SDIO1_SAMPLE>; 243 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 244 fifo-depth = <0x100>; 245 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 246 reg = <0x0 0xff0e0000 0x0 0x4000>; 247 resets = <&cru SRST_SDIO1>; 248 reset-names = "reset"; 249 status = "disabled"; 250 }; 251 252 emmc: mmc@ff0f0000 { 253 compatible = "rockchip,rk3288-dw-mshc"; 254 max-frequency = <150000000>; 255 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>, 256 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>; 257 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 258 fifo-depth = <0x100>; 259 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 260 reg = <0x0 0xff0f0000 0x0 0x4000>; 261 resets = <&cru SRST_EMMC>; 262 reset-names = "reset"; 263 status = "disabled"; 264 }; 265 266 saradc: saradc@ff100000 { 267 compatible = "rockchip,saradc"; 268 reg = <0x0 0xff100000 0x0 0x100>; 269 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 270 #io-channel-cells = <1>; 271 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>; 272 clock-names = "saradc", "apb_pclk"; 273 resets = <&cru SRST_SARADC>; 274 reset-names = "saradc-apb"; 275 status = "disabled"; 276 }; 277 278 spi0: spi@ff110000 { 279 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi"; 280 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>; 281 clock-names = "spiclk", "apb_pclk"; 282 dmas = <&dmac_peri 11>, <&dmac_peri 12>; 283 dma-names = "tx", "rx"; 284 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; 285 pinctrl-names = "default"; 286 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>; 287 reg = <0x0 0xff110000 0x0 0x1000>; 288 #address-cells = <1>; 289 #size-cells = <0>; 290 status = "disabled"; 291 }; 292 293 spi1: spi@ff120000 { 294 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi"; 295 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>; 296 clock-names = "spiclk", "apb_pclk"; 297 dmas = <&dmac_peri 13>, <&dmac_peri 14>; 298 dma-names = "tx", "rx"; 299 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 300 pinctrl-names = "default"; 301 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>; 302 reg = <0x0 0xff120000 0x0 0x1000>; 303 #address-cells = <1>; 304 #size-cells = <0>; 305 status = "disabled"; 306 }; 307 308 spi2: spi@ff130000 { 309 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi"; 310 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>; 311 clock-names = "spiclk", "apb_pclk"; 312 dmas = <&dmac_peri 15>, <&dmac_peri 16>; 313 dma-names = "tx", "rx"; 314 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; 315 pinctrl-names = "default"; 316 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>; 317 reg = <0x0 0xff130000 0x0 0x1000>; 318 #address-cells = <1>; 319 #size-cells = <0>; 320 status = "disabled"; 321 }; 322 323 i2c1: i2c@ff140000 { 324 compatible = "rockchip,rk3288-i2c"; 325 reg = <0x0 0xff140000 0x0 0x1000>; 326 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 327 #address-cells = <1>; 328 #size-cells = <0>; 329 clock-names = "i2c"; 330 clocks = <&cru PCLK_I2C1>; 331 pinctrl-names = "default"; 332 pinctrl-0 = <&i2c1_xfer>; 333 status = "disabled"; 334 }; 335 336 i2c3: i2c@ff150000 { 337 compatible = "rockchip,rk3288-i2c"; 338 reg = <0x0 0xff150000 0x0 0x1000>; 339 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 340 #address-cells = <1>; 341 #size-cells = <0>; 342 clock-names = "i2c"; 343 clocks = <&cru PCLK_I2C3>; 344 pinctrl-names = "default"; 345 pinctrl-0 = <&i2c3_xfer>; 346 status = "disabled"; 347 }; 348 349 i2c4: i2c@ff160000 { 350 compatible = "rockchip,rk3288-i2c"; 351 reg = <0x0 0xff160000 0x0 0x1000>; 352 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 353 #address-cells = <1>; 354 #size-cells = <0>; 355 clock-names = "i2c"; 356 clocks = <&cru PCLK_I2C4>; 357 pinctrl-names = "default"; 358 pinctrl-0 = <&i2c4_xfer>; 359 status = "disabled"; 360 }; 361 362 i2c5: i2c@ff170000 { 363 compatible = "rockchip,rk3288-i2c"; 364 reg = <0x0 0xff170000 0x0 0x1000>; 365 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 366 #address-cells = <1>; 367 #size-cells = <0>; 368 clock-names = "i2c"; 369 clocks = <&cru PCLK_I2C5>; 370 pinctrl-names = "default"; 371 pinctrl-0 = <&i2c5_xfer>; 372 status = "disabled"; 373 }; 374 375 uart0: serial@ff180000 { 376 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart"; 377 reg = <0x0 0xff180000 0x0 0x100>; 378 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; 379 reg-shift = <2>; 380 reg-io-width = <4>; 381 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; 382 clock-names = "baudclk", "apb_pclk"; 383 dmas = <&dmac_peri 1>, <&dmac_peri 2>; 384 dma-names = "tx", "rx"; 385 pinctrl-names = "default"; 386 pinctrl-0 = <&uart0_xfer>; 387 status = "disabled"; 388 }; 389 390 uart1: serial@ff190000 { 391 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart"; 392 reg = <0x0 0xff190000 0x0 0x100>; 393 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; 394 reg-shift = <2>; 395 reg-io-width = <4>; 396 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; 397 clock-names = "baudclk", "apb_pclk"; 398 dmas = <&dmac_peri 3>, <&dmac_peri 4>; 399 dma-names = "tx", "rx"; 400 pinctrl-names = "default"; 401 pinctrl-0 = <&uart1_xfer>; 402 status = "disabled"; 403 }; 404 405 uart2: serial@ff690000 { 406 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart"; 407 reg = <0x0 0xff690000 0x0 0x100>; 408 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; 409 reg-shift = <2>; 410 reg-io-width = <4>; 411 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; 412 clock-names = "baudclk", "apb_pclk"; 413 pinctrl-names = "default"; 414 pinctrl-0 = <&uart2_xfer>; 415 status = "disabled"; 416 }; 417 418 uart3: serial@ff1b0000 { 419 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart"; 420 reg = <0x0 0xff1b0000 0x0 0x100>; 421 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>; 422 reg-shift = <2>; 423 reg-io-width = <4>; 424 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>; 425 clock-names = "baudclk", "apb_pclk"; 426 dmas = <&dmac_peri 7>, <&dmac_peri 8>; 427 dma-names = "tx", "rx"; 428 pinctrl-names = "default"; 429 pinctrl-0 = <&uart3_xfer>; 430 status = "disabled"; 431 }; 432 433 uart4: serial@ff1c0000 { 434 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart"; 435 reg = <0x0 0xff1c0000 0x0 0x100>; 436 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; 437 reg-shift = <2>; 438 reg-io-width = <4>; 439 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>; 440 clock-names = "baudclk", "apb_pclk"; 441 dmas = <&dmac_peri 9>, <&dmac_peri 10>; 442 dma-names = "tx", "rx"; 443 pinctrl-names = "default"; 444 pinctrl-0 = <&uart4_xfer>; 445 status = "disabled"; 446 }; 447 448 dmac_peri: dma-controller@ff250000 { 449 compatible = "arm,pl330", "arm,primecell"; 450 reg = <0x0 0xff250000 0x0 0x4000>; 451 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 452 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 453 #dma-cells = <1>; 454 arm,pl330-broken-no-flushp; 455 arm,pl330-periph-burst; 456 clocks = <&cru ACLK_DMAC2>; 457 clock-names = "apb_pclk"; 458 }; 459 460 thermal-zones { 461 reserve_thermal: reserve-thermal { 462 polling-delay-passive = <1000>; /* milliseconds */ 463 polling-delay = <5000>; /* milliseconds */ 464 465 thermal-sensors = <&tsadc 0>; 466 }; 467 468 cpu_thermal: cpu-thermal { 469 polling-delay-passive = <100>; /* milliseconds */ 470 polling-delay = <5000>; /* milliseconds */ 471 472 thermal-sensors = <&tsadc 1>; 473 474 trips { 475 cpu_alert0: cpu_alert0 { 476 temperature = <70000>; /* millicelsius */ 477 hysteresis = <2000>; /* millicelsius */ 478 type = "passive"; 479 }; 480 cpu_alert1: cpu_alert1 { 481 temperature = <75000>; /* millicelsius */ 482 hysteresis = <2000>; /* millicelsius */ 483 type = "passive"; 484 }; 485 cpu_crit: cpu_crit { 486 temperature = <90000>; /* millicelsius */ 487 hysteresis = <2000>; /* millicelsius */ 488 type = "critical"; 489 }; 490 }; 491 492 cooling-maps { 493 map0 { 494 trip = <&cpu_alert0>; 495 cooling-device = 496 <&cpu0 THERMAL_NO_LIMIT 6>, 497 <&cpu1 THERMAL_NO_LIMIT 6>, 498 <&cpu2 THERMAL_NO_LIMIT 6>, 499 <&cpu3 THERMAL_NO_LIMIT 6>; 500 }; 501 map1 { 502 trip = <&cpu_alert1>; 503 cooling-device = 504 <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 505 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 506 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 507 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 508 }; 509 }; 510 }; 511 512 gpu_thermal: gpu-thermal { 513 polling-delay-passive = <100>; /* milliseconds */ 514 polling-delay = <5000>; /* milliseconds */ 515 516 thermal-sensors = <&tsadc 2>; 517 518 trips { 519 gpu_alert0: gpu_alert0 { 520 temperature = <70000>; /* millicelsius */ 521 hysteresis = <2000>; /* millicelsius */ 522 type = "passive"; 523 }; 524 gpu_crit: gpu_crit { 525 temperature = <90000>; /* millicelsius */ 526 hysteresis = <2000>; /* millicelsius */ 527 type = "critical"; 528 }; 529 }; 530 531 cooling-maps { 532 map0 { 533 trip = <&gpu_alert0>; 534 cooling-device = 535 <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 536 }; 537 }; 538 }; 539 }; 540 541 tsadc: tsadc@ff280000 { 542 compatible = "rockchip,rk3288-tsadc"; 543 reg = <0x0 0xff280000 0x0 0x100>; 544 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 545 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>; 546 clock-names = "tsadc", "apb_pclk"; 547 resets = <&cru SRST_TSADC>; 548 reset-names = "tsadc-apb"; 549 pinctrl-names = "init", "default", "sleep"; 550 pinctrl-0 = <&otp_pin>; 551 pinctrl-1 = <&otp_out>; 552 pinctrl-2 = <&otp_pin>; 553 #thermal-sensor-cells = <1>; 554 rockchip,grf = <&grf>; 555 rockchip,hw-tshut-temp = <95000>; 556 status = "disabled"; 557 }; 558 559 gmac: ethernet@ff290000 { 560 compatible = "rockchip,rk3288-gmac"; 561 reg = <0x0 0xff290000 0x0 0x10000>; 562 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>, 563 <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 564 interrupt-names = "macirq", "eth_wake_irq"; 565 rockchip,grf = <&grf>; 566 clocks = <&cru SCLK_MAC>, 567 <&cru SCLK_MAC_RX>, <&cru SCLK_MAC_TX>, 568 <&cru SCLK_MACREF>, <&cru SCLK_MACREF_OUT>, 569 <&cru ACLK_GMAC>, <&cru PCLK_GMAC>; 570 clock-names = "stmmaceth", 571 "mac_clk_rx", "mac_clk_tx", 572 "clk_mac_ref", "clk_mac_refout", 573 "aclk_mac", "pclk_mac"; 574 resets = <&cru SRST_MAC>; 575 reset-names = "stmmaceth"; 576 status = "disabled"; 577 }; 578 579 usb_host0_ehci: usb@ff500000 { 580 compatible = "generic-ehci"; 581 reg = <0x0 0xff500000 0x0 0x100>; 582 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; 583 clocks = <&cru HCLK_USBHOST0>; 584 phys = <&usbphy1>; 585 phy-names = "usb"; 586 status = "disabled"; 587 }; 588 589 /* NOTE: doesn't work on RK3288, but was fixed on RK3288W */ 590 usb_host0_ohci: usb@ff520000 { 591 compatible = "generic-ohci"; 592 reg = <0x0 0xff520000 0x0 0x100>; 593 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; 594 clocks = <&cru HCLK_USBHOST0>; 595 phys = <&usbphy1>; 596 phy-names = "usb"; 597 status = "disabled"; 598 }; 599 600 usb_host1: usb@ff540000 { 601 compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb", 602 "snps,dwc2"; 603 reg = <0x0 0xff540000 0x0 0x40000>; 604 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 605 clocks = <&cru HCLK_USBHOST1>; 606 clock-names = "otg"; 607 dr_mode = "host"; 608 phys = <&usbphy2>; 609 phy-names = "usb2-phy"; 610 snps,reset-phy-on-wake; 611 status = "disabled"; 612 }; 613 614 usb_otg: usb@ff580000 { 615 compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb", 616 "snps,dwc2"; 617 reg = <0x0 0xff580000 0x0 0x40000>; 618 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 619 clocks = <&cru HCLK_OTG0>; 620 clock-names = "otg"; 621 dr_mode = "otg"; 622 g-np-tx-fifo-size = <16>; 623 g-rx-fifo-size = <275>; 624 g-tx-fifo-size = <256 128 128 64 64 32>; 625 phys = <&usbphy0>; 626 phy-names = "usb2-phy"; 627 status = "disabled"; 628 }; 629 630 usb_hsic: usb@ff5c0000 { 631 compatible = "generic-ehci"; 632 reg = <0x0 0xff5c0000 0x0 0x100>; 633 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 634 clocks = <&cru HCLK_HSIC>; 635 status = "disabled"; 636 }; 637 638 dmac_bus_ns: dma-controller@ff600000 { 639 compatible = "arm,pl330", "arm,primecell"; 640 reg = <0x0 0xff600000 0x0 0x4000>; 641 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 642 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; 643 #dma-cells = <1>; 644 arm,pl330-broken-no-flushp; 645 arm,pl330-periph-burst; 646 clocks = <&cru ACLK_DMAC1>; 647 clock-names = "apb_pclk"; 648 status = "disabled"; 649 }; 650 651 i2c0: i2c@ff650000 { 652 compatible = "rockchip,rk3288-i2c"; 653 reg = <0x0 0xff650000 0x0 0x1000>; 654 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; 655 #address-cells = <1>; 656 #size-cells = <0>; 657 clock-names = "i2c"; 658 clocks = <&cru PCLK_I2C0>; 659 pinctrl-names = "default"; 660 pinctrl-0 = <&i2c0_xfer>; 661 status = "disabled"; 662 }; 663 664 i2c2: i2c@ff660000 { 665 compatible = "rockchip,rk3288-i2c"; 666 reg = <0x0 0xff660000 0x0 0x1000>; 667 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; 668 #address-cells = <1>; 669 #size-cells = <0>; 670 clock-names = "i2c"; 671 clocks = <&cru PCLK_I2C2>; 672 pinctrl-names = "default"; 673 pinctrl-0 = <&i2c2_xfer>; 674 status = "disabled"; 675 }; 676 677 pwm0: pwm@ff680000 { 678 compatible = "rockchip,rk3288-pwm"; 679 reg = <0x0 0xff680000 0x0 0x10>; 680 #pwm-cells = <3>; 681 pinctrl-names = "default"; 682 pinctrl-0 = <&pwm0_pin>; 683 clocks = <&cru PCLK_RKPWM>; 684 status = "disabled"; 685 }; 686 687 pwm1: pwm@ff680010 { 688 compatible = "rockchip,rk3288-pwm"; 689 reg = <0x0 0xff680010 0x0 0x10>; 690 #pwm-cells = <3>; 691 pinctrl-names = "default"; 692 pinctrl-0 = <&pwm1_pin>; 693 clocks = <&cru PCLK_RKPWM>; 694 status = "disabled"; 695 }; 696 697 pwm2: pwm@ff680020 { 698 compatible = "rockchip,rk3288-pwm"; 699 reg = <0x0 0xff680020 0x0 0x10>; 700 #pwm-cells = <3>; 701 pinctrl-names = "default"; 702 pinctrl-0 = <&pwm2_pin>; 703 clocks = <&cru PCLK_RKPWM>; 704 status = "disabled"; 705 }; 706 707 pwm3: pwm@ff680030 { 708 compatible = "rockchip,rk3288-pwm"; 709 reg = <0x0 0xff680030 0x0 0x10>; 710 #pwm-cells = <3>; 711 pinctrl-names = "default"; 712 pinctrl-0 = <&pwm3_pin>; 713 clocks = <&cru PCLK_RKPWM>; 714 status = "disabled"; 715 }; 716 717 bus_intmem: sram@ff700000 { 718 compatible = "mmio-sram"; 719 reg = <0x0 0xff700000 0x0 0x18000>; 720 #address-cells = <1>; 721 #size-cells = <1>; 722 ranges = <0 0x0 0xff700000 0x18000>; 723 smp-sram@0 { 724 compatible = "rockchip,rk3066-smp-sram"; 725 reg = <0x00 0x10>; 726 }; 727 }; 728 729 pmu_sram: sram@ff720000 { 730 compatible = "rockchip,rk3288-pmu-sram", "mmio-sram"; 731 reg = <0x0 0xff720000 0x0 0x1000>; 732 }; 733 734 pmu: power-management@ff730000 { 735 compatible = "rockchip,rk3288-pmu", "syscon", "simple-mfd"; 736 reg = <0x0 0xff730000 0x0 0x100>; 737 738 power: power-controller { 739 compatible = "rockchip,rk3288-power-controller"; 740 #power-domain-cells = <1>; 741 #address-cells = <1>; 742 #size-cells = <0>; 743 744 /* 745 * Note: Although SCLK_* are the working clocks 746 * of device without including on the NOC, needed for 747 * synchronous reset. 748 * 749 * The clocks on the which NOC: 750 * ACLK_IEP/ACLK_VIP/ACLK_VOP0 are on ACLK_VIO0_NIU. 751 * ACLK_ISP/ACLK_VOP1 are on ACLK_VIO1_NIU. 752 * ACLK_RGA is on ACLK_RGA_NIU. 753 * The others (HCLK_*,PLCK_*) are on HCLK_VIO_NIU. 754 * 755 * Which clock are device clocks: 756 * clocks devices 757 * *_IEP IEP:Image Enhancement Processor 758 * *_ISP ISP:Image Signal Processing 759 * *_VIP VIP:Video Input Processor 760 * *_VOP* VOP:Visual Output Processor 761 * *_RGA RGA 762 * *_EDP* EDP 763 * *_LVDS_* LVDS 764 * *_HDMI HDMI 765 * *_MIPI_* MIPI 766 */ 767 power-domain@RK3288_PD_VIO { 768 reg = <RK3288_PD_VIO>; 769 clocks = <&cru ACLK_IEP>, 770 <&cru ACLK_ISP>, 771 <&cru ACLK_RGA>, 772 <&cru ACLK_VIP>, 773 <&cru ACLK_VOP0>, 774 <&cru ACLK_VOP1>, 775 <&cru DCLK_VOP0>, 776 <&cru DCLK_VOP1>, 777 <&cru HCLK_IEP>, 778 <&cru HCLK_ISP>, 779 <&cru HCLK_RGA>, 780 <&cru HCLK_VIP>, 781 <&cru HCLK_VOP0>, 782 <&cru HCLK_VOP1>, 783 <&cru PCLK_EDP_CTRL>, 784 <&cru PCLK_HDMI_CTRL>, 785 <&cru PCLK_LVDS_PHY>, 786 <&cru PCLK_MIPI_CSI>, 787 <&cru PCLK_MIPI_DSI0>, 788 <&cru PCLK_MIPI_DSI1>, 789 <&cru SCLK_EDP_24M>, 790 <&cru SCLK_EDP>, 791 <&cru SCLK_ISP_JPE>, 792 <&cru SCLK_ISP>, 793 <&cru SCLK_RGA>; 794 pm_qos = <&qos_vio0_iep>, 795 <&qos_vio1_vop>, 796 <&qos_vio1_isp_w0>, 797 <&qos_vio1_isp_w1>, 798 <&qos_vio0_vop>, 799 <&qos_vio0_vip>, 800 <&qos_vio2_rga_r>, 801 <&qos_vio2_rga_w>, 802 <&qos_vio1_isp_r>; 803 #power-domain-cells = <0>; 804 }; 805 806 /* 807 * Note: The following 3 are HEVC(H.265) clocks, 808 * and on the ACLK_HEVC_NIU (NOC). 809 */ 810 power-domain@RK3288_PD_HEVC { 811 reg = <RK3288_PD_HEVC>; 812 clocks = <&cru ACLK_HEVC>, 813 <&cru SCLK_HEVC_CABAC>, 814 <&cru SCLK_HEVC_CORE>; 815 pm_qos = <&qos_hevc_r>, 816 <&qos_hevc_w>; 817 #power-domain-cells = <0>; 818 }; 819 820 /* 821 * Note: ACLK_VCODEC/HCLK_VCODEC are VCODEC 822 * (video endecoder & decoder) clocks that on the 823 * ACLK_VCODEC_NIU and HCLK_VCODEC_NIU (NOC). 824 */ 825 power-domain@RK3288_PD_VIDEO { 826 reg = <RK3288_PD_VIDEO>; 827 clocks = <&cru ACLK_VCODEC>, 828 <&cru HCLK_VCODEC>; 829 pm_qos = <&qos_video>; 830 #power-domain-cells = <0>; 831 }; 832 833 /* 834 * Note: ACLK_GPU is the GPU clock, 835 * and on the ACLK_GPU_NIU (NOC). 836 */ 837 power-domain@RK3288_PD_GPU { 838 reg = <RK3288_PD_GPU>; 839 clocks = <&cru ACLK_GPU>; 840 pm_qos = <&qos_gpu_r>, 841 <&qos_gpu_w>; 842 #power-domain-cells = <0>; 843 }; 844 }; 845 846 reboot-mode { 847 compatible = "syscon-reboot-mode"; 848 offset = <0x94>; 849 mode-normal = <BOOT_NORMAL>; 850 mode-recovery = <BOOT_RECOVERY>; 851 mode-bootloader = <BOOT_FASTBOOT>; 852 mode-loader = <BOOT_BL_DOWNLOAD>; 853 }; 854 }; 855 856 sgrf: syscon@ff740000 { 857 compatible = "rockchip,rk3288-sgrf", "syscon"; 858 reg = <0x0 0xff740000 0x0 0x1000>; 859 }; 860 861 cru: clock-controller@ff760000 { 862 compatible = "rockchip,rk3288-cru"; 863 reg = <0x0 0xff760000 0x0 0x1000>; 864 clocks = <&xin24m>; 865 clock-names = "xin24m"; 866 rockchip,grf = <&grf>; 867 #clock-cells = <1>; 868 #reset-cells = <1>; 869 assigned-clocks = <&cru PLL_GPLL>, <&cru PLL_CPLL>, 870 <&cru PLL_NPLL>, <&cru ACLK_CPU>, 871 <&cru HCLK_CPU>, <&cru PCLK_CPU>, 872 <&cru ACLK_PERI>, <&cru HCLK_PERI>, 873 <&cru PCLK_PERI>; 874 assigned-clock-rates = <594000000>, <400000000>, 875 <500000000>, <300000000>, 876 <150000000>, <75000000>, 877 <300000000>, <150000000>, 878 <75000000>; 879 }; 880 881 grf: syscon@ff770000 { 882 compatible = "rockchip,rk3288-grf", "syscon", "simple-mfd"; 883 reg = <0x0 0xff770000 0x0 0x1000>; 884 885 edp_phy: edp-phy { 886 compatible = "rockchip,rk3288-dp-phy"; 887 clocks = <&cru SCLK_EDP_24M>; 888 clock-names = "24m"; 889 #phy-cells = <0>; 890 status = "disabled"; 891 }; 892 893 io_domains: io-domains { 894 compatible = "rockchip,rk3288-io-voltage-domain"; 895 status = "disabled"; 896 }; 897 898 usbphy: usbphy { 899 compatible = "rockchip,rk3288-usb-phy"; 900 #address-cells = <1>; 901 #size-cells = <0>; 902 status = "disabled"; 903 904 usbphy0: usb-phy@320 { 905 #phy-cells = <0>; 906 reg = <0x320>; 907 clocks = <&cru SCLK_OTGPHY0>; 908 clock-names = "phyclk"; 909 #clock-cells = <0>; 910 resets = <&cru SRST_USBOTG_PHY>; 911 reset-names = "phy-reset"; 912 }; 913 914 usbphy1: usb-phy@334 { 915 #phy-cells = <0>; 916 reg = <0x334>; 917 clocks = <&cru SCLK_OTGPHY1>; 918 clock-names = "phyclk"; 919 #clock-cells = <0>; 920 resets = <&cru SRST_USBHOST0_PHY>; 921 reset-names = "phy-reset"; 922 }; 923 924 usbphy2: usb-phy@348 { 925 #phy-cells = <0>; 926 reg = <0x348>; 927 clocks = <&cru SCLK_OTGPHY2>; 928 clock-names = "phyclk"; 929 #clock-cells = <0>; 930 resets = <&cru SRST_USBHOST1_PHY>; 931 reset-names = "phy-reset"; 932 }; 933 }; 934 }; 935 936 wdt: watchdog@ff800000 { 937 compatible = "rockchip,rk3288-wdt", "snps,dw-wdt"; 938 reg = <0x0 0xff800000 0x0 0x100>; 939 clocks = <&cru PCLK_WDT>; 940 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; 941 status = "disabled"; 942 }; 943 944 spdif: sound@ff8b0000 { 945 compatible = "rockchip,rk3288-spdif", "rockchip,rk3066-spdif"; 946 reg = <0x0 0xff8b0000 0x0 0x10000>; 947 #sound-dai-cells = <0>; 948 clocks = <&cru SCLK_SPDIF8CH>, <&cru HCLK_SPDIF8CH>; 949 clock-names = "mclk", "hclk"; 950 dmas = <&dmac_bus_s 3>; 951 dma-names = "tx"; 952 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; 953 pinctrl-names = "default"; 954 pinctrl-0 = <&spdif_tx>; 955 rockchip,grf = <&grf>; 956 status = "disabled"; 957 }; 958 959 i2s: i2s@ff890000 { 960 compatible = "rockchip,rk3288-i2s", "rockchip,rk3066-i2s"; 961 reg = <0x0 0xff890000 0x0 0x10000>; 962 #sound-dai-cells = <0>; 963 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 964 clocks = <&cru SCLK_I2S0>, <&cru HCLK_I2S0>; 965 clock-names = "i2s_clk", "i2s_hclk"; 966 dmas = <&dmac_bus_s 0>, <&dmac_bus_s 1>; 967 dma-names = "tx", "rx"; 968 pinctrl-names = "default"; 969 pinctrl-0 = <&i2s0_bus>; 970 rockchip,playback-channels = <8>; 971 rockchip,capture-channels = <2>; 972 status = "disabled"; 973 }; 974 975 crypto: crypto@ff8a0000 { 976 compatible = "rockchip,rk3288-crypto"; 977 reg = <0x0 0xff8a0000 0x0 0x4000>; 978 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; 979 clocks = <&cru ACLK_CRYPTO>, <&cru HCLK_CRYPTO>, 980 <&cru SCLK_CRYPTO>, <&cru ACLK_DMAC1>; 981 clock-names = "aclk", "hclk", "sclk", "apb_pclk"; 982 resets = <&cru SRST_CRYPTO>; 983 reset-names = "crypto-rst"; 984 }; 985 986 iep_mmu: iommu@ff900800 { 987 compatible = "rockchip,iommu"; 988 reg = <0x0 0xff900800 0x0 0x40>; 989 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 990 clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>; 991 clock-names = "aclk", "iface"; 992 #iommu-cells = <0>; 993 status = "disabled"; 994 }; 995 996 isp_mmu: iommu@ff914000 { 997 compatible = "rockchip,iommu"; 998 reg = <0x0 0xff914000 0x0 0x100>, <0x0 0xff915000 0x0 0x100>; 999 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 1000 clocks = <&cru ACLK_ISP>, <&cru HCLK_ISP>; 1001 clock-names = "aclk", "iface"; 1002 #iommu-cells = <0>; 1003 rockchip,disable-mmu-reset; 1004 status = "disabled"; 1005 }; 1006 1007 rga: rga@ff920000 { 1008 compatible = "rockchip,rk3288-rga"; 1009 reg = <0x0 0xff920000 0x0 0x180>; 1010 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>; 1011 clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru SCLK_RGA>; 1012 clock-names = "aclk", "hclk", "sclk"; 1013 power-domains = <&power RK3288_PD_VIO>; 1014 resets = <&cru SRST_RGA_CORE>, <&cru SRST_RGA_AXI>, <&cru SRST_RGA_AHB>; 1015 reset-names = "core", "axi", "ahb"; 1016 }; 1017 1018 vopb: vop@ff930000 { 1019 compatible = "rockchip,rk3288-vop"; 1020 reg = <0x0 0xff930000 0x0 0x19c>, <0x0 0xff931000 0x0 0x1000>; 1021 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 1022 clocks = <&cru ACLK_VOP0>, <&cru DCLK_VOP0>, <&cru HCLK_VOP0>; 1023 clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; 1024 power-domains = <&power RK3288_PD_VIO>; 1025 resets = <&cru SRST_LCDC0_AXI>, <&cru SRST_LCDC0_AHB>, <&cru SRST_LCDC0_DCLK>; 1026 reset-names = "axi", "ahb", "dclk"; 1027 iommus = <&vopb_mmu>; 1028 status = "disabled"; 1029 1030 vopb_out: port { 1031 #address-cells = <1>; 1032 #size-cells = <0>; 1033 1034 vopb_out_hdmi: endpoint@0 { 1035 reg = <0>; 1036 remote-endpoint = <&hdmi_in_vopb>; 1037 }; 1038 1039 vopb_out_edp: endpoint@1 { 1040 reg = <1>; 1041 remote-endpoint = <&edp_in_vopb>; 1042 }; 1043 1044 vopb_out_mipi: endpoint@2 { 1045 reg = <2>; 1046 remote-endpoint = <&mipi_in_vopb>; 1047 }; 1048 1049 vopb_out_lvds: endpoint@3 { 1050 reg = <3>; 1051 remote-endpoint = <&lvds_in_vopb>; 1052 }; 1053 }; 1054 }; 1055 1056 vopb_mmu: iommu@ff930300 { 1057 compatible = "rockchip,iommu"; 1058 reg = <0x0 0xff930300 0x0 0x100>; 1059 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 1060 clocks = <&cru ACLK_VOP0>, <&cru HCLK_VOP0>; 1061 clock-names = "aclk", "iface"; 1062 power-domains = <&power RK3288_PD_VIO>; 1063 #iommu-cells = <0>; 1064 status = "disabled"; 1065 }; 1066 1067 vopl: vop@ff940000 { 1068 compatible = "rockchip,rk3288-vop"; 1069 reg = <0x0 0xff940000 0x0 0x19c>, <0x0 0xff941000 0x0 0x1000>; 1070 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 1071 clocks = <&cru ACLK_VOP1>, <&cru DCLK_VOP1>, <&cru HCLK_VOP1>; 1072 clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; 1073 power-domains = <&power RK3288_PD_VIO>; 1074 resets = <&cru SRST_LCDC1_AXI>, <&cru SRST_LCDC1_AHB>, <&cru SRST_LCDC1_DCLK>; 1075 reset-names = "axi", "ahb", "dclk"; 1076 iommus = <&vopl_mmu>; 1077 status = "disabled"; 1078 1079 vopl_out: port { 1080 #address-cells = <1>; 1081 #size-cells = <0>; 1082 1083 vopl_out_hdmi: endpoint@0 { 1084 reg = <0>; 1085 remote-endpoint = <&hdmi_in_vopl>; 1086 }; 1087 1088 vopl_out_edp: endpoint@1 { 1089 reg = <1>; 1090 remote-endpoint = <&edp_in_vopl>; 1091 }; 1092 1093 vopl_out_mipi: endpoint@2 { 1094 reg = <2>; 1095 remote-endpoint = <&mipi_in_vopl>; 1096 }; 1097 1098 vopl_out_lvds: endpoint@3 { 1099 reg = <3>; 1100 remote-endpoint = <&lvds_in_vopl>; 1101 }; 1102 }; 1103 }; 1104 1105 vopl_mmu: iommu@ff940300 { 1106 compatible = "rockchip,iommu"; 1107 reg = <0x0 0xff940300 0x0 0x100>; 1108 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 1109 clocks = <&cru ACLK_VOP1>, <&cru HCLK_VOP1>; 1110 clock-names = "aclk", "iface"; 1111 power-domains = <&power RK3288_PD_VIO>; 1112 #iommu-cells = <0>; 1113 status = "disabled"; 1114 }; 1115 1116 mipi_dsi: dsi@ff960000 { 1117 compatible = "rockchip,rk3288-mipi-dsi", "snps,dw-mipi-dsi"; 1118 reg = <0x0 0xff960000 0x0 0x4000>; 1119 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 1120 clocks = <&cru SCLK_MIPIDSI_24M>, <&cru PCLK_MIPI_DSI0>; 1121 clock-names = "ref", "pclk"; 1122 power-domains = <&power RK3288_PD_VIO>; 1123 rockchip,grf = <&grf>; 1124 status = "disabled"; 1125 1126 ports { 1127 #address-cells = <1>; 1128 #size-cells = <0>; 1129 1130 mipi_in: port@0 { 1131 reg = <0>; 1132 #address-cells = <1>; 1133 #size-cells = <0>; 1134 1135 mipi_in_vopb: endpoint@0 { 1136 reg = <0>; 1137 remote-endpoint = <&vopb_out_mipi>; 1138 }; 1139 1140 mipi_in_vopl: endpoint@1 { 1141 reg = <1>; 1142 remote-endpoint = <&vopl_out_mipi>; 1143 }; 1144 }; 1145 1146 mipi_out: port@1 { 1147 reg = <1>; 1148 }; 1149 }; 1150 }; 1151 1152 lvds: lvds@ff96c000 { 1153 compatible = "rockchip,rk3288-lvds"; 1154 reg = <0x0 0xff96c000 0x0 0x4000>; 1155 clocks = <&cru PCLK_LVDS_PHY>; 1156 clock-names = "pclk_lvds"; 1157 pinctrl-names = "lcdc"; 1158 pinctrl-0 = <&lcdc_ctl>; 1159 power-domains = <&power RK3288_PD_VIO>; 1160 rockchip,grf = <&grf>; 1161 status = "disabled"; 1162 1163 ports { 1164 #address-cells = <1>; 1165 #size-cells = <0>; 1166 1167 lvds_in: port@0 { 1168 reg = <0>; 1169 #address-cells = <1>; 1170 #size-cells = <0>; 1171 1172 lvds_in_vopb: endpoint@0 { 1173 reg = <0>; 1174 remote-endpoint = <&vopb_out_lvds>; 1175 }; 1176 1177 lvds_in_vopl: endpoint@1 { 1178 reg = <1>; 1179 remote-endpoint = <&vopl_out_lvds>; 1180 }; 1181 }; 1182 1183 lvds_out: port@1 { 1184 reg = <1>; 1185 }; 1186 }; 1187 }; 1188 1189 edp: dp@ff970000 { 1190 compatible = "rockchip,rk3288-dp"; 1191 reg = <0x0 0xff970000 0x0 0x4000>; 1192 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 1193 assigned-clocks = <&cru SCLK_EDP_24M>; 1194 assigned-clock-parents = <&xin24m>; 1195 clocks = <&cru SCLK_EDP>, <&cru PCLK_EDP_CTRL>; 1196 clock-names = "dp", "pclk"; 1197 phys = <&edp_phy>; 1198 phy-names = "dp"; 1199 power-domains = <&power RK3288_PD_VIO>; 1200 resets = <&cru SRST_EDP>; 1201 reset-names = "dp"; 1202 rockchip,grf = <&grf>; 1203 status = "disabled"; 1204 1205 ports { 1206 #address-cells = <1>; 1207 #size-cells = <0>; 1208 1209 edp_in: port@0 { 1210 reg = <0>; 1211 #address-cells = <1>; 1212 #size-cells = <0>; 1213 1214 edp_in_vopb: endpoint@0 { 1215 reg = <0>; 1216 remote-endpoint = <&vopb_out_edp>; 1217 }; 1218 1219 edp_in_vopl: endpoint@1 { 1220 reg = <1>; 1221 remote-endpoint = <&vopl_out_edp>; 1222 }; 1223 }; 1224 1225 edp_out: port@1 { 1226 reg = <1>; 1227 }; 1228 }; 1229 }; 1230 1231 hdmi: hdmi@ff980000 { 1232 compatible = "rockchip,rk3288-dw-hdmi"; 1233 reg = <0x0 0xff980000 0x0 0x20000>; 1234 reg-io-width = <4>; 1235 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 1236 clocks = <&cru PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_HDCP>, <&cru SCLK_HDMI_CEC>; 1237 clock-names = "iahb", "isfr", "cec"; 1238 power-domains = <&power RK3288_PD_VIO>; 1239 rockchip,grf = <&grf>; 1240 #sound-dai-cells = <0>; 1241 status = "disabled"; 1242 1243 ports { 1244 #address-cells = <1>; 1245 #size-cells = <0>; 1246 1247 hdmi_in: port@0 { 1248 reg = <0>; 1249 #address-cells = <1>; 1250 #size-cells = <0>; 1251 1252 hdmi_in_vopb: endpoint@0 { 1253 reg = <0>; 1254 remote-endpoint = <&vopb_out_hdmi>; 1255 }; 1256 1257 hdmi_in_vopl: endpoint@1 { 1258 reg = <1>; 1259 remote-endpoint = <&vopl_out_hdmi>; 1260 }; 1261 }; 1262 1263 hdmi_out: port@1 { 1264 reg = <1>; 1265 }; 1266 }; 1267 }; 1268 1269 vpu: video-codec@ff9a0000 { 1270 compatible = "rockchip,rk3288-vpu"; 1271 reg = <0x0 0xff9a0000 0x0 0x800>; 1272 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, 1273 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 1274 interrupt-names = "vepu", "vdpu"; 1275 clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>; 1276 clock-names = "aclk", "hclk"; 1277 iommus = <&vpu_mmu>; 1278 power-domains = <&power RK3288_PD_VIDEO>; 1279 }; 1280 1281 vpu_mmu: iommu@ff9a0800 { 1282 compatible = "rockchip,iommu"; 1283 reg = <0x0 0xff9a0800 0x0 0x100>; 1284 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 1285 clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>; 1286 clock-names = "aclk", "iface"; 1287 #iommu-cells = <0>; 1288 power-domains = <&power RK3288_PD_VIDEO>; 1289 }; 1290 1291 hevc_mmu: iommu@ff9c0440 { 1292 compatible = "rockchip,iommu"; 1293 reg = <0x0 0xff9c0440 0x0 0x40>, <0x0 0xff9c0480 0x0 0x40>; 1294 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>; 1295 clocks = <&cru ACLK_HEVC>, <&cru HCLK_HEVC>; 1296 clock-names = "aclk", "iface"; 1297 #iommu-cells = <0>; 1298 status = "disabled"; 1299 }; 1300 1301 gpu: gpu@ffa30000 { 1302 compatible = "rockchip,rk3288-mali", "arm,mali-t760"; 1303 reg = <0x0 0xffa30000 0x0 0x10000>; 1304 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, 1305 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 1306 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 1307 interrupt-names = "job", "mmu", "gpu"; 1308 clocks = <&cru ACLK_GPU>; 1309 operating-points-v2 = <&gpu_opp_table>; 1310 #cooling-cells = <2>; /* min followed by max */ 1311 power-domains = <&power RK3288_PD_GPU>; 1312 status = "disabled"; 1313 }; 1314 1315 gpu_opp_table: opp-table-1 { 1316 compatible = "operating-points-v2"; 1317 1318 opp-100000000 { 1319 opp-hz = /bits/ 64 <100000000>; 1320 opp-microvolt = <950000>; 1321 }; 1322 opp-200000000 { 1323 opp-hz = /bits/ 64 <200000000>; 1324 opp-microvolt = <950000>; 1325 }; 1326 opp-300000000 { 1327 opp-hz = /bits/ 64 <300000000>; 1328 opp-microvolt = <1000000>; 1329 }; 1330 opp-400000000 { 1331 opp-hz = /bits/ 64 <400000000>; 1332 opp-microvolt = <1100000>; 1333 }; 1334 opp-600000000 { 1335 opp-hz = /bits/ 64 <600000000>; 1336 opp-microvolt = <1250000>; 1337 }; 1338 }; 1339 1340 qos_gpu_r: qos@ffaa0000 { 1341 compatible = "rockchip,rk3288-qos", "syscon"; 1342 reg = <0x0 0xffaa0000 0x0 0x20>; 1343 }; 1344 1345 qos_gpu_w: qos@ffaa0080 { 1346 compatible = "rockchip,rk3288-qos", "syscon"; 1347 reg = <0x0 0xffaa0080 0x0 0x20>; 1348 }; 1349 1350 qos_vio1_vop: qos@ffad0000 { 1351 compatible = "rockchip,rk3288-qos", "syscon"; 1352 reg = <0x0 0xffad0000 0x0 0x20>; 1353 }; 1354 1355 qos_vio1_isp_w0: qos@ffad0100 { 1356 compatible = "rockchip,rk3288-qos", "syscon"; 1357 reg = <0x0 0xffad0100 0x0 0x20>; 1358 }; 1359 1360 qos_vio1_isp_w1: qos@ffad0180 { 1361 compatible = "rockchip,rk3288-qos", "syscon"; 1362 reg = <0x0 0xffad0180 0x0 0x20>; 1363 }; 1364 1365 qos_vio0_vop: qos@ffad0400 { 1366 compatible = "rockchip,rk3288-qos", "syscon"; 1367 reg = <0x0 0xffad0400 0x0 0x20>; 1368 }; 1369 1370 qos_vio0_vip: qos@ffad0480 { 1371 compatible = "rockchip,rk3288-qos", "syscon"; 1372 reg = <0x0 0xffad0480 0x0 0x20>; 1373 }; 1374 1375 qos_vio0_iep: qos@ffad0500 { 1376 compatible = "rockchip,rk3288-qos", "syscon"; 1377 reg = <0x0 0xffad0500 0x0 0x20>; 1378 }; 1379 1380 qos_vio2_rga_r: qos@ffad0800 { 1381 compatible = "rockchip,rk3288-qos", "syscon"; 1382 reg = <0x0 0xffad0800 0x0 0x20>; 1383 }; 1384 1385 qos_vio2_rga_w: qos@ffad0880 { 1386 compatible = "rockchip,rk3288-qos", "syscon"; 1387 reg = <0x0 0xffad0880 0x0 0x20>; 1388 }; 1389 1390 qos_vio1_isp_r: qos@ffad0900 { 1391 compatible = "rockchip,rk3288-qos", "syscon"; 1392 reg = <0x0 0xffad0900 0x0 0x20>; 1393 }; 1394 1395 qos_video: qos@ffae0000 { 1396 compatible = "rockchip,rk3288-qos", "syscon"; 1397 reg = <0x0 0xffae0000 0x0 0x20>; 1398 }; 1399 1400 qos_hevc_r: qos@ffaf0000 { 1401 compatible = "rockchip,rk3288-qos", "syscon"; 1402 reg = <0x0 0xffaf0000 0x0 0x20>; 1403 }; 1404 1405 qos_hevc_w: qos@ffaf0080 { 1406 compatible = "rockchip,rk3288-qos", "syscon"; 1407 reg = <0x0 0xffaf0080 0x0 0x20>; 1408 }; 1409 1410 dmac_bus_s: dma-controller@ffb20000 { 1411 compatible = "arm,pl330", "arm,primecell"; 1412 reg = <0x0 0xffb20000 0x0 0x4000>; 1413 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 1414 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; 1415 #dma-cells = <1>; 1416 arm,pl330-broken-no-flushp; 1417 arm,pl330-periph-burst; 1418 clocks = <&cru ACLK_DMAC1>; 1419 clock-names = "apb_pclk"; 1420 }; 1421 1422 efuse: efuse@ffb40000 { 1423 compatible = "rockchip,rk3288-efuse"; 1424 reg = <0x0 0xffb40000 0x0 0x20>; 1425 #address-cells = <1>; 1426 #size-cells = <1>; 1427 clocks = <&cru PCLK_EFUSE256>; 1428 clock-names = "pclk_efuse"; 1429 1430 cpu_id: cpu-id@7 { 1431 reg = <0x07 0x10>; 1432 }; 1433 cpu_leakage: cpu_leakage@17 { 1434 reg = <0x17 0x1>; 1435 }; 1436 }; 1437 1438 gic: interrupt-controller@ffc01000 { 1439 compatible = "arm,gic-400"; 1440 interrupt-controller; 1441 #interrupt-cells = <3>; 1442 #address-cells = <0>; 1443 1444 reg = <0x0 0xffc01000 0x0 0x1000>, 1445 <0x0 0xffc02000 0x0 0x2000>, 1446 <0x0 0xffc04000 0x0 0x2000>, 1447 <0x0 0xffc06000 0x0 0x2000>; 1448 interrupts = <GIC_PPI 9 0xf04>; 1449 }; 1450 1451 pinctrl: pinctrl { 1452 compatible = "rockchip,rk3288-pinctrl"; 1453 rockchip,grf = <&grf>; 1454 rockchip,pmu = <&pmu>; 1455 #address-cells = <2>; 1456 #size-cells = <2>; 1457 ranges; 1458 1459 gpio0: gpio@ff750000 { 1460 compatible = "rockchip,gpio-bank"; 1461 reg = <0x0 0xff750000 0x0 0x100>; 1462 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 1463 clocks = <&cru PCLK_GPIO0>; 1464 1465 gpio-controller; 1466 #gpio-cells = <2>; 1467 1468 interrupt-controller; 1469 #interrupt-cells = <2>; 1470 }; 1471 1472 gpio1: gpio@ff780000 { 1473 compatible = "rockchip,gpio-bank"; 1474 reg = <0x0 0xff780000 0x0 0x100>; 1475 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 1476 clocks = <&cru PCLK_GPIO1>; 1477 1478 gpio-controller; 1479 #gpio-cells = <2>; 1480 1481 interrupt-controller; 1482 #interrupt-cells = <2>; 1483 }; 1484 1485 gpio2: gpio@ff790000 { 1486 compatible = "rockchip,gpio-bank"; 1487 reg = <0x0 0xff790000 0x0 0x100>; 1488 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 1489 clocks = <&cru PCLK_GPIO2>; 1490 1491 gpio-controller; 1492 #gpio-cells = <2>; 1493 1494 interrupt-controller; 1495 #interrupt-cells = <2>; 1496 }; 1497 1498 gpio3: gpio@ff7a0000 { 1499 compatible = "rockchip,gpio-bank"; 1500 reg = <0x0 0xff7a0000 0x0 0x100>; 1501 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 1502 clocks = <&cru PCLK_GPIO3>; 1503 1504 gpio-controller; 1505 #gpio-cells = <2>; 1506 1507 interrupt-controller; 1508 #interrupt-cells = <2>; 1509 }; 1510 1511 gpio4: gpio@ff7b0000 { 1512 compatible = "rockchip,gpio-bank"; 1513 reg = <0x0 0xff7b0000 0x0 0x100>; 1514 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; 1515 clocks = <&cru PCLK_GPIO4>; 1516 1517 gpio-controller; 1518 #gpio-cells = <2>; 1519 1520 interrupt-controller; 1521 #interrupt-cells = <2>; 1522 }; 1523 1524 gpio5: gpio@ff7c0000 { 1525 compatible = "rockchip,gpio-bank"; 1526 reg = <0x0 0xff7c0000 0x0 0x100>; 1527 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 1528 clocks = <&cru PCLK_GPIO5>; 1529 1530 gpio-controller; 1531 #gpio-cells = <2>; 1532 1533 interrupt-controller; 1534 #interrupt-cells = <2>; 1535 }; 1536 1537 gpio6: gpio@ff7d0000 { 1538 compatible = "rockchip,gpio-bank"; 1539 reg = <0x0 0xff7d0000 0x0 0x100>; 1540 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; 1541 clocks = <&cru PCLK_GPIO6>; 1542 1543 gpio-controller; 1544 #gpio-cells = <2>; 1545 1546 interrupt-controller; 1547 #interrupt-cells = <2>; 1548 }; 1549 1550 gpio7: gpio@ff7e0000 { 1551 compatible = "rockchip,gpio-bank"; 1552 reg = <0x0 0xff7e0000 0x0 0x100>; 1553 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>; 1554 clocks = <&cru PCLK_GPIO7>; 1555 1556 gpio-controller; 1557 #gpio-cells = <2>; 1558 1559 interrupt-controller; 1560 #interrupt-cells = <2>; 1561 }; 1562 1563 gpio8: gpio@ff7f0000 { 1564 compatible = "rockchip,gpio-bank"; 1565 reg = <0x0 0xff7f0000 0x0 0x100>; 1566 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; 1567 clocks = <&cru PCLK_GPIO8>; 1568 1569 gpio-controller; 1570 #gpio-cells = <2>; 1571 1572 interrupt-controller; 1573 #interrupt-cells = <2>; 1574 }; 1575 1576 hdmi { 1577 hdmi_cec_c0: hdmi-cec-c0 { 1578 rockchip,pins = <7 RK_PC0 2 &pcfg_pull_none>; 1579 }; 1580 1581 hdmi_cec_c7: hdmi-cec-c7 { 1582 rockchip,pins = <7 RK_PC7 4 &pcfg_pull_none>; 1583 }; 1584 1585 hdmi_ddc: hdmi-ddc { 1586 rockchip,pins = <7 RK_PC3 2 &pcfg_pull_none>, 1587 <7 RK_PC4 2 &pcfg_pull_none>; 1588 }; 1589 1590 hdmi_ddc_unwedge: hdmi-ddc-unwedge { 1591 rockchip,pins = <7 RK_PC3 RK_FUNC_GPIO &pcfg_output_low>, 1592 <7 RK_PC4 2 &pcfg_pull_none>; 1593 }; 1594 }; 1595 1596 pcfg_output_low: pcfg-output-low { 1597 output-low; 1598 }; 1599 1600 pcfg_pull_up: pcfg-pull-up { 1601 bias-pull-up; 1602 }; 1603 1604 pcfg_pull_down: pcfg-pull-down { 1605 bias-pull-down; 1606 }; 1607 1608 pcfg_pull_none: pcfg-pull-none { 1609 bias-disable; 1610 }; 1611 1612 pcfg_pull_none_12ma: pcfg-pull-none-12ma { 1613 bias-disable; 1614 drive-strength = <12>; 1615 }; 1616 1617 suspend { 1618 global_pwroff: global-pwroff { 1619 rockchip,pins = <0 RK_PA0 1 &pcfg_pull_none>; 1620 }; 1621 1622 ddrio_pwroff: ddrio-pwroff { 1623 rockchip,pins = <0 RK_PA1 1 &pcfg_pull_none>; 1624 }; 1625 1626 ddr0_retention: ddr0-retention { 1627 rockchip,pins = <0 RK_PA2 1 &pcfg_pull_up>; 1628 }; 1629 1630 ddr1_retention: ddr1-retention { 1631 rockchip,pins = <0 RK_PA3 1 &pcfg_pull_up>; 1632 }; 1633 }; 1634 1635 edp { 1636 edp_hpd: edp-hpd { 1637 rockchip,pins = <7 RK_PB3 2 &pcfg_pull_down>; 1638 }; 1639 }; 1640 1641 i2c0 { 1642 i2c0_xfer: i2c0-xfer { 1643 rockchip,pins = <0 RK_PB7 1 &pcfg_pull_none>, 1644 <0 RK_PC0 1 &pcfg_pull_none>; 1645 }; 1646 }; 1647 1648 i2c1 { 1649 i2c1_xfer: i2c1-xfer { 1650 rockchip,pins = <8 RK_PA4 1 &pcfg_pull_none>, 1651 <8 RK_PA5 1 &pcfg_pull_none>; 1652 }; 1653 }; 1654 1655 i2c2 { 1656 i2c2_xfer: i2c2-xfer { 1657 rockchip,pins = <6 RK_PB1 1 &pcfg_pull_none>, 1658 <6 RK_PB2 1 &pcfg_pull_none>; 1659 }; 1660 }; 1661 1662 i2c3 { 1663 i2c3_xfer: i2c3-xfer { 1664 rockchip,pins = <2 RK_PC0 1 &pcfg_pull_none>, 1665 <2 RK_PC1 1 &pcfg_pull_none>; 1666 }; 1667 }; 1668 1669 i2c4 { 1670 i2c4_xfer: i2c4-xfer { 1671 rockchip,pins = <7 RK_PC1 1 &pcfg_pull_none>, 1672 <7 RK_PC2 1 &pcfg_pull_none>; 1673 }; 1674 }; 1675 1676 i2c5 { 1677 i2c5_xfer: i2c5-xfer { 1678 rockchip,pins = <7 RK_PC3 1 &pcfg_pull_none>, 1679 <7 RK_PC4 1 &pcfg_pull_none>; 1680 }; 1681 }; 1682 1683 i2s0 { 1684 i2s0_bus: i2s0-bus { 1685 rockchip,pins = <6 RK_PA0 1 &pcfg_pull_none>, 1686 <6 RK_PA1 1 &pcfg_pull_none>, 1687 <6 RK_PA2 1 &pcfg_pull_none>, 1688 <6 RK_PA3 1 &pcfg_pull_none>, 1689 <6 RK_PA4 1 &pcfg_pull_none>, 1690 <6 RK_PB0 1 &pcfg_pull_none>; 1691 }; 1692 }; 1693 1694 lcdc { 1695 lcdc_ctl: lcdc-ctl { 1696 rockchip,pins = <1 RK_PD0 1 &pcfg_pull_none>, 1697 <1 RK_PD1 1 &pcfg_pull_none>, 1698 <1 RK_PD2 1 &pcfg_pull_none>, 1699 <1 RK_PD3 1 &pcfg_pull_none>; 1700 }; 1701 }; 1702 1703 sdmmc { 1704 sdmmc_clk: sdmmc-clk { 1705 rockchip,pins = <6 RK_PC4 1 &pcfg_pull_none>; 1706 }; 1707 1708 sdmmc_cmd: sdmmc-cmd { 1709 rockchip,pins = <6 RK_PC5 1 &pcfg_pull_up>; 1710 }; 1711 1712 sdmmc_cd: sdmmc-cd { 1713 rockchip,pins = <6 RK_PC6 1 &pcfg_pull_up>; 1714 }; 1715 1716 sdmmc_bus1: sdmmc-bus1 { 1717 rockchip,pins = <6 RK_PC0 1 &pcfg_pull_up>; 1718 }; 1719 1720 sdmmc_bus4: sdmmc-bus4 { 1721 rockchip,pins = <6 RK_PC0 1 &pcfg_pull_up>, 1722 <6 RK_PC1 1 &pcfg_pull_up>, 1723 <6 RK_PC2 1 &pcfg_pull_up>, 1724 <6 RK_PC3 1 &pcfg_pull_up>; 1725 }; 1726 }; 1727 1728 sdio0 { 1729 sdio0_bus1: sdio0-bus1 { 1730 rockchip,pins = <4 RK_PC4 1 &pcfg_pull_up>; 1731 }; 1732 1733 sdio0_bus4: sdio0-bus4 { 1734 rockchip,pins = <4 RK_PC4 1 &pcfg_pull_up>, 1735 <4 RK_PC5 1 &pcfg_pull_up>, 1736 <4 RK_PC6 1 &pcfg_pull_up>, 1737 <4 RK_PC7 1 &pcfg_pull_up>; 1738 }; 1739 1740 sdio0_cmd: sdio0-cmd { 1741 rockchip,pins = <4 RK_PD0 1 &pcfg_pull_up>; 1742 }; 1743 1744 sdio0_clk: sdio0-clk { 1745 rockchip,pins = <4 RK_PD1 1 &pcfg_pull_none>; 1746 }; 1747 1748 sdio0_cd: sdio0-cd { 1749 rockchip,pins = <4 RK_PD2 1 &pcfg_pull_up>; 1750 }; 1751 1752 sdio0_wp: sdio0-wp { 1753 rockchip,pins = <4 RK_PD3 1 &pcfg_pull_up>; 1754 }; 1755 1756 sdio0_pwr: sdio0-pwr { 1757 rockchip,pins = <4 RK_PD4 1 &pcfg_pull_up>; 1758 }; 1759 1760 sdio0_bkpwr: sdio0-bkpwr { 1761 rockchip,pins = <4 RK_PD5 1 &pcfg_pull_up>; 1762 }; 1763 1764 sdio0_int: sdio0-int { 1765 rockchip,pins = <4 RK_PD6 1 &pcfg_pull_up>; 1766 }; 1767 }; 1768 1769 sdio1 { 1770 sdio1_bus1: sdio1-bus1 { 1771 rockchip,pins = <3 RK_PD0 4 &pcfg_pull_up>; 1772 }; 1773 1774 sdio1_bus4: sdio1-bus4 { 1775 rockchip,pins = <3 RK_PD0 4 &pcfg_pull_up>, 1776 <3 RK_PD1 4 &pcfg_pull_up>, 1777 <3 RK_PD2 4 &pcfg_pull_up>, 1778 <3 RK_PD3 4 &pcfg_pull_up>; 1779 }; 1780 1781 sdio1_cd: sdio1-cd { 1782 rockchip,pins = <3 RK_PD4 4 &pcfg_pull_up>; 1783 }; 1784 1785 sdio1_wp: sdio1-wp { 1786 rockchip,pins = <3 RK_PD5 4 &pcfg_pull_up>; 1787 }; 1788 1789 sdio1_bkpwr: sdio1-bkpwr { 1790 rockchip,pins = <3 RK_PD6 4 &pcfg_pull_up>; 1791 }; 1792 1793 sdio1_int: sdio1-int { 1794 rockchip,pins = <3 RK_PD7 4 &pcfg_pull_up>; 1795 }; 1796 1797 sdio1_cmd: sdio1-cmd { 1798 rockchip,pins = <4 RK_PA6 4 &pcfg_pull_up>; 1799 }; 1800 1801 sdio1_clk: sdio1-clk { 1802 rockchip,pins = <4 RK_PA7 4 &pcfg_pull_none>; 1803 }; 1804 1805 sdio1_pwr: sdio1-pwr { 1806 rockchip,pins = <4 RK_PB1 4 &pcfg_pull_up>; 1807 }; 1808 }; 1809 1810 emmc { 1811 emmc_clk: emmc-clk { 1812 rockchip,pins = <3 RK_PC2 2 &pcfg_pull_none>; 1813 }; 1814 1815 emmc_cmd: emmc-cmd { 1816 rockchip,pins = <3 RK_PC0 2 &pcfg_pull_up>; 1817 }; 1818 1819 emmc_pwr: emmc-pwr { 1820 rockchip,pins = <3 RK_PB1 2 &pcfg_pull_up>; 1821 }; 1822 1823 emmc_bus1: emmc-bus1 { 1824 rockchip,pins = <3 RK_PA0 2 &pcfg_pull_up>; 1825 }; 1826 1827 emmc_bus4: emmc-bus4 { 1828 rockchip,pins = <3 RK_PA0 2 &pcfg_pull_up>, 1829 <3 RK_PA1 2 &pcfg_pull_up>, 1830 <3 RK_PA2 2 &pcfg_pull_up>, 1831 <3 RK_PA3 2 &pcfg_pull_up>; 1832 }; 1833 1834 emmc_bus8: emmc-bus8 { 1835 rockchip,pins = <3 RK_PA0 2 &pcfg_pull_up>, 1836 <3 RK_PA1 2 &pcfg_pull_up>, 1837 <3 RK_PA2 2 &pcfg_pull_up>, 1838 <3 RK_PA3 2 &pcfg_pull_up>, 1839 <3 RK_PA4 2 &pcfg_pull_up>, 1840 <3 RK_PA5 2 &pcfg_pull_up>, 1841 <3 RK_PA6 2 &pcfg_pull_up>, 1842 <3 RK_PA7 2 &pcfg_pull_up>; 1843 }; 1844 }; 1845 1846 spi0 { 1847 spi0_clk: spi0-clk { 1848 rockchip,pins = <5 RK_PB4 1 &pcfg_pull_up>; 1849 }; 1850 spi0_cs0: spi0-cs0 { 1851 rockchip,pins = <5 RK_PB5 1 &pcfg_pull_up>; 1852 }; 1853 spi0_tx: spi0-tx { 1854 rockchip,pins = <5 RK_PB6 1 &pcfg_pull_up>; 1855 }; 1856 spi0_rx: spi0-rx { 1857 rockchip,pins = <5 RK_PB7 1 &pcfg_pull_up>; 1858 }; 1859 spi0_cs1: spi0-cs1 { 1860 rockchip,pins = <5 RK_PC0 1 &pcfg_pull_up>; 1861 }; 1862 }; 1863 spi1 { 1864 spi1_clk: spi1-clk { 1865 rockchip,pins = <7 RK_PB4 2 &pcfg_pull_up>; 1866 }; 1867 spi1_cs0: spi1-cs0 { 1868 rockchip,pins = <7 RK_PB5 2 &pcfg_pull_up>; 1869 }; 1870 spi1_rx: spi1-rx { 1871 rockchip,pins = <7 RK_PB6 2 &pcfg_pull_up>; 1872 }; 1873 spi1_tx: spi1-tx { 1874 rockchip,pins = <7 RK_PB7 2 &pcfg_pull_up>; 1875 }; 1876 }; 1877 1878 spi2 { 1879 spi2_cs1: spi2-cs1 { 1880 rockchip,pins = <8 RK_PA3 1 &pcfg_pull_up>; 1881 }; 1882 spi2_clk: spi2-clk { 1883 rockchip,pins = <8 RK_PA6 1 &pcfg_pull_up>; 1884 }; 1885 spi2_cs0: spi2-cs0 { 1886 rockchip,pins = <8 RK_PA7 1 &pcfg_pull_up>; 1887 }; 1888 spi2_rx: spi2-rx { 1889 rockchip,pins = <8 RK_PB0 1 &pcfg_pull_up>; 1890 }; 1891 spi2_tx: spi2-tx { 1892 rockchip,pins = <8 RK_PB1 1 &pcfg_pull_up>; 1893 }; 1894 }; 1895 1896 uart0 { 1897 uart0_xfer: uart0-xfer { 1898 rockchip,pins = <4 RK_PC0 1 &pcfg_pull_up>, 1899 <4 RK_PC1 1 &pcfg_pull_none>; 1900 }; 1901 1902 uart0_cts: uart0-cts { 1903 rockchip,pins = <4 RK_PC2 1 &pcfg_pull_up>; 1904 }; 1905 1906 uart0_rts: uart0-rts { 1907 rockchip,pins = <4 RK_PC3 1 &pcfg_pull_none>; 1908 }; 1909 }; 1910 1911 uart1 { 1912 uart1_xfer: uart1-xfer { 1913 rockchip,pins = <5 RK_PB0 1 &pcfg_pull_up>, 1914 <5 RK_PB1 1 &pcfg_pull_none>; 1915 }; 1916 1917 uart1_cts: uart1-cts { 1918 rockchip,pins = <5 RK_PB2 1 &pcfg_pull_up>; 1919 }; 1920 1921 uart1_rts: uart1-rts { 1922 rockchip,pins = <5 RK_PB3 1 &pcfg_pull_none>; 1923 }; 1924 }; 1925 1926 uart2 { 1927 uart2_xfer: uart2-xfer { 1928 rockchip,pins = <7 RK_PC6 1 &pcfg_pull_up>, 1929 <7 RK_PC7 1 &pcfg_pull_none>; 1930 }; 1931 /* no rts / cts for uart2 */ 1932 }; 1933 1934 uart3 { 1935 uart3_xfer: uart3-xfer { 1936 rockchip,pins = <7 RK_PA7 1 &pcfg_pull_up>, 1937 <7 RK_PB0 1 &pcfg_pull_none>; 1938 }; 1939 1940 uart3_cts: uart3-cts { 1941 rockchip,pins = <7 RK_PB1 1 &pcfg_pull_up>; 1942 }; 1943 1944 uart3_rts: uart3-rts { 1945 rockchip,pins = <7 RK_PB2 1 &pcfg_pull_none>; 1946 }; 1947 }; 1948 1949 uart4 { 1950 uart4_xfer: uart4-xfer { 1951 rockchip,pins = <5 RK_PB7 3 &pcfg_pull_up>, 1952 <5 RK_PB6 3 &pcfg_pull_none>; 1953 }; 1954 1955 uart4_cts: uart4-cts { 1956 rockchip,pins = <5 RK_PB4 3 &pcfg_pull_up>; 1957 }; 1958 1959 uart4_rts: uart4-rts { 1960 rockchip,pins = <5 RK_PB5 3 &pcfg_pull_none>; 1961 }; 1962 }; 1963 1964 tsadc { 1965 otp_pin: otp-pin { 1966 rockchip,pins = <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; 1967 }; 1968 1969 otp_out: otp-out { 1970 rockchip,pins = <0 RK_PB2 1 &pcfg_pull_none>; 1971 }; 1972 }; 1973 1974 pwm0 { 1975 pwm0_pin: pwm0-pin { 1976 rockchip,pins = <7 RK_PA0 1 &pcfg_pull_none>; 1977 }; 1978 }; 1979 1980 pwm1 { 1981 pwm1_pin: pwm1-pin { 1982 rockchip,pins = <7 RK_PA1 1 &pcfg_pull_none>; 1983 }; 1984 }; 1985 1986 pwm2 { 1987 pwm2_pin: pwm2-pin { 1988 rockchip,pins = <7 RK_PC6 3 &pcfg_pull_none>; 1989 }; 1990 }; 1991 1992 pwm3 { 1993 pwm3_pin: pwm3-pin { 1994 rockchip,pins = <7 RK_PC7 3 &pcfg_pull_none>; 1995 }; 1996 }; 1997 1998 gmac { 1999 rgmii_pins: rgmii-pins { 2000 rockchip,pins = <3 RK_PD6 3 &pcfg_pull_none>, 2001 <3 RK_PD7 3 &pcfg_pull_none>, 2002 <3 RK_PD2 3 &pcfg_pull_none>, 2003 <3 RK_PD3 3 &pcfg_pull_none>, 2004 <3 RK_PD4 3 &pcfg_pull_none_12ma>, 2005 <3 RK_PD5 3 &pcfg_pull_none_12ma>, 2006 <3 RK_PD0 3 &pcfg_pull_none_12ma>, 2007 <3 RK_PD1 3 &pcfg_pull_none_12ma>, 2008 <4 RK_PA0 3 &pcfg_pull_none>, 2009 <4 RK_PA5 3 &pcfg_pull_none>, 2010 <4 RK_PA6 3 &pcfg_pull_none>, 2011 <4 RK_PB1 3 &pcfg_pull_none_12ma>, 2012 <4 RK_PA4 3 &pcfg_pull_none_12ma>, 2013 <4 RK_PA1 3 &pcfg_pull_none>, 2014 <4 RK_PA3 3 &pcfg_pull_none>; 2015 }; 2016 2017 rmii_pins: rmii-pins { 2018 rockchip,pins = <3 RK_PD6 3 &pcfg_pull_none>, 2019 <3 RK_PD7 3 &pcfg_pull_none>, 2020 <3 RK_PD4 3 &pcfg_pull_none>, 2021 <3 RK_PD5 3 &pcfg_pull_none>, 2022 <4 RK_PA0 3 &pcfg_pull_none>, 2023 <4 RK_PA5 3 &pcfg_pull_none>, 2024 <4 RK_PA4 3 &pcfg_pull_none>, 2025 <4 RK_PA1 3 &pcfg_pull_none>, 2026 <4 RK_PA2 3 &pcfg_pull_none>, 2027 <4 RK_PA3 3 &pcfg_pull_none>; 2028 }; 2029 }; 2030 2031 spdif { 2032 spdif_tx: spdif-tx { 2033 rockchip,pins = <6 RK_PB3 1 &pcfg_pull_none>; 2034 }; 2035 }; 2036 }; 2037};
~/
Read-only file preview.