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rk322x.dtsi
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linux-6.19.14/arch/arm/boot/dts/rockchip/rk322x.dtsi
1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2 3#include <dt-bindings/gpio/gpio.h> 4#include <dt-bindings/interrupt-controller/irq.h> 5#include <dt-bindings/interrupt-controller/arm-gic.h> 6#include <dt-bindings/pinctrl/rockchip.h> 7#include <dt-bindings/clock/rk3228-cru.h> 8#include <dt-bindings/thermal/thermal.h> 9#include <dt-bindings/power/rk3228-power.h> 10 11/ { 12 #address-cells = <1>; 13 #size-cells = <1>; 14 15 interrupt-parent = <&gic>; 16 17 aliases { 18 gpio0 = &gpio0; 19 gpio1 = &gpio1; 20 gpio2 = &gpio2; 21 gpio3 = &gpio3; 22 serial0 = &uart0; 23 serial1 = &uart1; 24 serial2 = &uart2; 25 spi0 = &spi0; 26 }; 27 28 cpus { 29 #address-cells = <1>; 30 #size-cells = <0>; 31 32 cpu0: cpu@f00 { 33 device_type = "cpu"; 34 compatible = "arm,cortex-a7"; 35 reg = <0xf00>; 36 resets = <&cru SRST_CORE0>; 37 operating-points-v2 = <&cpu0_opp_table>; 38 #cooling-cells = <2>; /* min followed by max */ 39 clocks = <&cru ARMCLK>; 40 enable-method = "psci"; 41 }; 42 43 cpu1: cpu@f01 { 44 device_type = "cpu"; 45 compatible = "arm,cortex-a7"; 46 reg = <0xf01>; 47 resets = <&cru SRST_CORE1>; 48 operating-points-v2 = <&cpu0_opp_table>; 49 #cooling-cells = <2>; /* min followed by max */ 50 enable-method = "psci"; 51 }; 52 53 cpu2: cpu@f02 { 54 device_type = "cpu"; 55 compatible = "arm,cortex-a7"; 56 reg = <0xf02>; 57 resets = <&cru SRST_CORE2>; 58 operating-points-v2 = <&cpu0_opp_table>; 59 #cooling-cells = <2>; /* min followed by max */ 60 enable-method = "psci"; 61 }; 62 63 cpu3: cpu@f03 { 64 device_type = "cpu"; 65 compatible = "arm,cortex-a7"; 66 reg = <0xf03>; 67 resets = <&cru SRST_CORE3>; 68 operating-points-v2 = <&cpu0_opp_table>; 69 #cooling-cells = <2>; /* min followed by max */ 70 enable-method = "psci"; 71 }; 72 }; 73 74 cpu0_opp_table: opp-table-0 { 75 compatible = "operating-points-v2"; 76 opp-shared; 77 78 opp-408000000 { 79 opp-hz = /bits/ 64 <408000000>; 80 opp-microvolt = <950000>; 81 clock-latency-ns = <40000>; 82 opp-suspend; 83 }; 84 opp-600000000 { 85 opp-hz = /bits/ 64 <600000000>; 86 opp-microvolt = <975000>; 87 }; 88 opp-816000000 { 89 opp-hz = /bits/ 64 <816000000>; 90 opp-microvolt = <1000000>; 91 }; 92 opp-1008000000 { 93 opp-hz = /bits/ 64 <1008000000>; 94 opp-microvolt = <1175000>; 95 }; 96 opp-1200000000 { 97 opp-hz = /bits/ 64 <1200000000>; 98 opp-microvolt = <1275000>; 99 }; 100 }; 101 102 arm-pmu { 103 compatible = "arm,cortex-a7-pmu"; 104 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>, 105 <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>, 106 <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>, 107 <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; 108 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; 109 }; 110 111 psci { 112 compatible = "arm,psci-1.0", "arm,psci-0.2"; 113 method = "smc"; 114 }; 115 116 timer { 117 compatible = "arm,armv7-timer"; 118 arm,cpu-registers-not-fw-configured; 119 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 120 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 121 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 122 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 123 clock-frequency = <24000000>; 124 }; 125 126 xin24m: oscillator { 127 compatible = "fixed-clock"; 128 clock-frequency = <24000000>; 129 clock-output-names = "xin24m"; 130 #clock-cells = <0>; 131 }; 132 133 display_subsystem: display-subsystem { 134 compatible = "rockchip,display-subsystem"; 135 ports = <&vop_out>; 136 }; 137 138 i2s1: i2s1@100b0000 { 139 compatible = "rockchip,rk3228-i2s", "rockchip,rk3066-i2s"; 140 reg = <0x100b0000 0x4000>; 141 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 142 clock-names = "i2s_clk", "i2s_hclk"; 143 clocks = <&cru SCLK_I2S1>, <&cru HCLK_I2S1_8CH>; 144 dmas = <&pdma 14>, <&pdma 15>; 145 dma-names = "tx", "rx"; 146 pinctrl-names = "default"; 147 pinctrl-0 = <&i2s1_bus>; 148 status = "disabled"; 149 }; 150 151 i2s0: i2s0@100c0000 { 152 compatible = "rockchip,rk3228-i2s", "rockchip,rk3066-i2s"; 153 reg = <0x100c0000 0x4000>; 154 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 155 clock-names = "i2s_clk", "i2s_hclk"; 156 clocks = <&cru SCLK_I2S0>, <&cru HCLK_I2S0_8CH>; 157 dmas = <&pdma 11>, <&pdma 12>; 158 dma-names = "tx", "rx"; 159 status = "disabled"; 160 }; 161 162 spdif: spdif@100d0000 { 163 compatible = "rockchip,rk3228-spdif"; 164 reg = <0x100d0000 0x1000>; 165 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 166 clocks = <&cru SCLK_SPDIF>, <&cru HCLK_SPDIF_8CH>; 167 clock-names = "mclk", "hclk"; 168 dmas = <&pdma 10>; 169 dma-names = "tx"; 170 pinctrl-names = "default"; 171 pinctrl-0 = <&spdif_tx>; 172 status = "disabled"; 173 }; 174 175 i2s2: i2s2@100e0000 { 176 compatible = "rockchip,rk3228-i2s", "rockchip,rk3066-i2s"; 177 reg = <0x100e0000 0x4000>; 178 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 179 clock-names = "i2s_clk", "i2s_hclk"; 180 clocks = <&cru SCLK_I2S2>, <&cru HCLK_I2S2_2CH>; 181 dmas = <&pdma 0>, <&pdma 1>; 182 dma-names = "tx", "rx"; 183 status = "disabled"; 184 }; 185 186 grf: syscon@11000000 { 187 compatible = "rockchip,rk3228-grf", "syscon", "simple-mfd"; 188 reg = <0x11000000 0x1000>; 189 #address-cells = <1>; 190 #size-cells = <1>; 191 192 io_domains: io-domains { 193 compatible = "rockchip,rk3228-io-voltage-domain"; 194 status = "disabled"; 195 }; 196 197 power: power-controller { 198 compatible = "rockchip,rk3228-power-controller"; 199 #power-domain-cells = <1>; 200 #address-cells = <1>; 201 #size-cells = <0>; 202 203 power-domain@RK3228_PD_VIO { 204 reg = <RK3228_PD_VIO>; 205 clocks = <&cru ACLK_HDCP>, 206 <&cru SCLK_HDCP>, 207 <&cru ACLK_IEP>, 208 <&cru HCLK_IEP>, 209 <&cru ACLK_RGA>, 210 <&cru HCLK_RGA>, 211 <&cru SCLK_RGA>; 212 pm_qos = <&qos_hdcp>, 213 <&qos_iep>, 214 <&qos_rga_r>, 215 <&qos_rga_w>; 216 #power-domain-cells = <0>; 217 }; 218 219 power-domain@RK3228_PD_VOP { 220 reg = <RK3228_PD_VOP>; 221 clocks = <&cru ACLK_VOP>, 222 <&cru DCLK_VOP>, 223 <&cru HCLK_VOP>; 224 pm_qos = <&qos_vop>; 225 #power-domain-cells = <0>; 226 }; 227 228 power-domain@RK3228_PD_VPU { 229 reg = <RK3228_PD_VPU>; 230 clocks = <&cru ACLK_VPU>, 231 <&cru HCLK_VPU>; 232 pm_qos = <&qos_vpu>; 233 #power-domain-cells = <0>; 234 }; 235 236 power-domain@RK3228_PD_RKVDEC { 237 reg = <RK3228_PD_RKVDEC>; 238 clocks = <&cru ACLK_RKVDEC>, 239 <&cru HCLK_RKVDEC>, 240 <&cru SCLK_VDEC_CABAC>, 241 <&cru SCLK_VDEC_CORE>; 242 pm_qos = <&qos_rkvdec_r>, 243 <&qos_rkvdec_w>; 244 #power-domain-cells = <0>; 245 }; 246 247 power-domain@RK3228_PD_GPU { 248 reg = <RK3228_PD_GPU>; 249 clocks = <&cru ACLK_GPU>; 250 pm_qos = <&qos_gpu>; 251 #power-domain-cells = <0>; 252 }; 253 }; 254 255 u2phy0: usb2phy@760 { 256 compatible = "rockchip,rk3228-usb2phy"; 257 reg = <0x0760 0x0c>; 258 clocks = <&cru SCLK_OTGPHY0>; 259 clock-names = "phyclk"; 260 clock-output-names = "usb480m_phy0"; 261 #clock-cells = <0>; 262 status = "disabled"; 263 264 u2phy0_otg: otg-port { 265 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, 266 <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>, 267 <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; 268 interrupt-names = "otg-bvalid", "otg-id", 269 "linestate"; 270 #phy-cells = <0>; 271 status = "disabled"; 272 }; 273 274 u2phy0_host: host-port { 275 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 276 interrupt-names = "linestate"; 277 #phy-cells = <0>; 278 status = "disabled"; 279 }; 280 }; 281 282 u2phy1: usb2phy@800 { 283 compatible = "rockchip,rk3228-usb2phy"; 284 reg = <0x0800 0x0c>; 285 clocks = <&cru SCLK_OTGPHY1>; 286 clock-names = "phyclk"; 287 clock-output-names = "usb480m_phy1"; 288 #clock-cells = <0>; 289 status = "disabled"; 290 291 u2phy1_otg: otg-port { 292 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>; 293 interrupt-names = "linestate"; 294 #phy-cells = <0>; 295 status = "disabled"; 296 }; 297 298 u2phy1_host: host-port { 299 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; 300 interrupt-names = "linestate"; 301 #phy-cells = <0>; 302 status = "disabled"; 303 }; 304 }; 305 }; 306 307 uart0: serial@11010000 { 308 compatible = "snps,dw-apb-uart"; 309 reg = <0x11010000 0x100>; 310 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; 311 clock-frequency = <24000000>; 312 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; 313 clock-names = "baudclk", "apb_pclk"; 314 pinctrl-names = "default"; 315 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>; 316 reg-shift = <2>; 317 reg-io-width = <4>; 318 status = "disabled"; 319 }; 320 321 uart1: serial@11020000 { 322 compatible = "snps,dw-apb-uart"; 323 reg = <0x11020000 0x100>; 324 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; 325 clock-frequency = <24000000>; 326 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; 327 clock-names = "baudclk", "apb_pclk"; 328 pinctrl-names = "default"; 329 pinctrl-0 = <&uart1_xfer>; 330 reg-shift = <2>; 331 reg-io-width = <4>; 332 status = "disabled"; 333 }; 334 335 uart2: serial@11030000 { 336 compatible = "snps,dw-apb-uart"; 337 reg = <0x11030000 0x100>; 338 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; 339 clock-frequency = <24000000>; 340 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; 341 clock-names = "baudclk", "apb_pclk"; 342 pinctrl-names = "default"; 343 pinctrl-0 = <&uart2_xfer>; 344 reg-shift = <2>; 345 reg-io-width = <4>; 346 status = "disabled"; 347 }; 348 349 efuse: efuse@11040000 { 350 compatible = "rockchip,rk3228-efuse"; 351 reg = <0x11040000 0x20>; 352 clocks = <&cru PCLK_EFUSE_256>; 353 clock-names = "pclk_efuse"; 354 #address-cells = <1>; 355 #size-cells = <1>; 356 357 /* Data cells */ 358 efuse_id: id@7 { 359 reg = <0x7 0x10>; 360 }; 361 cpu_leakage: cpu_leakage@17 { 362 reg = <0x17 0x1>; 363 }; 364 }; 365 366 i2c0: i2c@11050000 { 367 compatible = "rockchip,rk3228-i2c"; 368 reg = <0x11050000 0x1000>; 369 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 370 #address-cells = <1>; 371 #size-cells = <0>; 372 clock-names = "i2c"; 373 clocks = <&cru PCLK_I2C0>; 374 pinctrl-names = "default"; 375 pinctrl-0 = <&i2c0_xfer>; 376 status = "disabled"; 377 }; 378 379 i2c1: i2c@11060000 { 380 compatible = "rockchip,rk3228-i2c"; 381 reg = <0x11060000 0x1000>; 382 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 383 #address-cells = <1>; 384 #size-cells = <0>; 385 clock-names = "i2c"; 386 clocks = <&cru PCLK_I2C1>; 387 pinctrl-names = "default"; 388 pinctrl-0 = <&i2c1_xfer>; 389 status = "disabled"; 390 }; 391 392 i2c2: i2c@11070000 { 393 compatible = "rockchip,rk3228-i2c"; 394 reg = <0x11070000 0x1000>; 395 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 396 #address-cells = <1>; 397 #size-cells = <0>; 398 clock-names = "i2c"; 399 clocks = <&cru PCLK_I2C2>; 400 pinctrl-names = "default"; 401 pinctrl-0 = <&i2c2_xfer>; 402 status = "disabled"; 403 }; 404 405 i2c3: i2c@11080000 { 406 compatible = "rockchip,rk3228-i2c"; 407 reg = <0x11080000 0x1000>; 408 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; 409 #address-cells = <1>; 410 #size-cells = <0>; 411 clock-names = "i2c"; 412 clocks = <&cru PCLK_I2C3>; 413 pinctrl-names = "default"; 414 pinctrl-0 = <&i2c3_xfer>; 415 status = "disabled"; 416 }; 417 418 spi0: spi@11090000 { 419 compatible = "rockchip,rk3228-spi"; 420 reg = <0x11090000 0x1000>; 421 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; 422 #address-cells = <1>; 423 #size-cells = <0>; 424 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>; 425 clock-names = "spiclk", "apb_pclk"; 426 pinctrl-names = "default"; 427 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0 &spi0_cs1>; 428 status = "disabled"; 429 }; 430 431 wdt: watchdog@110a0000 { 432 compatible = "rockchip,rk3228-wdt", "snps,dw-wdt"; 433 reg = <0x110a0000 0x100>; 434 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; 435 clocks = <&cru PCLK_CPU>; 436 status = "disabled"; 437 }; 438 439 pwm0: pwm@110b0000 { 440 compatible = "rockchip,rk3288-pwm"; 441 reg = <0x110b0000 0x10>; 442 #pwm-cells = <3>; 443 clocks = <&cru PCLK_PWM>; 444 pinctrl-names = "default"; 445 pinctrl-0 = <&pwm0_pin>; 446 status = "disabled"; 447 }; 448 449 pwm1: pwm@110b0010 { 450 compatible = "rockchip,rk3288-pwm"; 451 reg = <0x110b0010 0x10>; 452 #pwm-cells = <3>; 453 clocks = <&cru PCLK_PWM>; 454 pinctrl-names = "default"; 455 pinctrl-0 = <&pwm1_pin>; 456 status = "disabled"; 457 }; 458 459 pwm2: pwm@110b0020 { 460 compatible = "rockchip,rk3288-pwm"; 461 reg = <0x110b0020 0x10>; 462 #pwm-cells = <3>; 463 clocks = <&cru PCLK_PWM>; 464 pinctrl-names = "default"; 465 pinctrl-0 = <&pwm2_pin>; 466 status = "disabled"; 467 }; 468 469 pwm3: pwm@110b0030 { 470 compatible = "rockchip,rk3288-pwm"; 471 reg = <0x110b0030 0x10>; 472 #pwm-cells = <2>; 473 clocks = <&cru PCLK_PWM>; 474 pinctrl-names = "default"; 475 pinctrl-0 = <&pwm3_pin>; 476 status = "disabled"; 477 }; 478 479 timer: timer@110c0000 { 480 compatible = "rockchip,rk3228-timer", "rockchip,rk3288-timer"; 481 reg = <0x110c0000 0x20>; 482 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; 483 clocks = <&cru PCLK_TIMER>, <&xin24m>; 484 clock-names = "pclk", "timer"; 485 }; 486 487 cru: clock-controller@110e0000 { 488 compatible = "rockchip,rk3228-cru"; 489 reg = <0x110e0000 0x1000>; 490 clocks = <&xin24m>; 491 clock-names = "xin24m"; 492 rockchip,grf = <&grf>; 493 #clock-cells = <1>; 494 #reset-cells = <1>; 495 assigned-clocks = 496 <&cru PLL_GPLL>, <&cru ARMCLK>, 497 <&cru PLL_CPLL>, <&cru ACLK_PERI>, 498 <&cru HCLK_PERI>, <&cru PCLK_PERI>, 499 <&cru ACLK_CPU>, <&cru HCLK_CPU>, 500 <&cru PCLK_CPU>; 501 assigned-clock-rates = 502 <594000000>, <816000000>, 503 <500000000>, <150000000>, 504 <150000000>, <75000000>, 505 <150000000>, <150000000>, 506 <75000000>; 507 }; 508 509 pdma: dma-controller@110f0000 { 510 compatible = "arm,pl330", "arm,primecell"; 511 reg = <0x110f0000 0x4000>; 512 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 513 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; 514 #dma-cells = <1>; 515 arm,pl330-periph-burst; 516 clocks = <&cru ACLK_DMAC>; 517 clock-names = "apb_pclk"; 518 }; 519 520 thermal-zones { 521 cpu_thermal: cpu-thermal { 522 polling-delay-passive = <100>; /* milliseconds */ 523 polling-delay = <5000>; /* milliseconds */ 524 525 thermal-sensors = <&tsadc 0>; 526 527 trips { 528 cpu_alert0: cpu_alert0 { 529 temperature = <70000>; /* millicelsius */ 530 hysteresis = <2000>; /* millicelsius */ 531 type = "passive"; 532 }; 533 cpu_alert1: cpu_alert1 { 534 temperature = <75000>; /* millicelsius */ 535 hysteresis = <2000>; /* millicelsius */ 536 type = "passive"; 537 }; 538 cpu_crit: cpu_crit { 539 temperature = <90000>; /* millicelsius */ 540 hysteresis = <2000>; /* millicelsius */ 541 type = "critical"; 542 }; 543 }; 544 545 cooling-maps { 546 map0 { 547 trip = <&cpu_alert0>; 548 cooling-device = 549 <&cpu0 THERMAL_NO_LIMIT 6>, 550 <&cpu1 THERMAL_NO_LIMIT 6>, 551 <&cpu2 THERMAL_NO_LIMIT 6>, 552 <&cpu3 THERMAL_NO_LIMIT 6>; 553 }; 554 map1 { 555 trip = <&cpu_alert1>; 556 cooling-device = 557 <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 558 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 559 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 560 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 561 }; 562 }; 563 }; 564 }; 565 566 tsadc: tsadc@11150000 { 567 compatible = "rockchip,rk3228-tsadc"; 568 reg = <0x11150000 0x100>; 569 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>; 570 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>; 571 clock-names = "tsadc", "apb_pclk"; 572 assigned-clocks = <&cru SCLK_TSADC>; 573 assigned-clock-rates = <32768>; 574 resets = <&cru SRST_TSADC>; 575 reset-names = "tsadc-apb"; 576 pinctrl-names = "init", "default", "sleep"; 577 pinctrl-0 = <&otp_pin>; 578 pinctrl-1 = <&otp_out>; 579 pinctrl-2 = <&otp_pin>; 580 #thermal-sensor-cells = <1>; 581 rockchip,hw-tshut-temp = <95000>; 582 status = "disabled"; 583 }; 584 585 hdmi_phy: hdmi-phy@12030000 { 586 compatible = "rockchip,rk3228-hdmi-phy"; 587 reg = <0x12030000 0x10000>; 588 clocks = <&cru PCLK_HDMI_PHY>, <&xin24m>, <&cru DCLK_HDMI_PHY>; 589 clock-names = "sysclk", "refoclk", "refpclk"; 590 #clock-cells = <0>; 591 clock-output-names = "hdmiphy_phy"; 592 #phy-cells = <0>; 593 status = "disabled"; 594 }; 595 596 gpu: gpu@20000000 { 597 compatible = "rockchip,rk3228-mali", "arm,mali-400"; 598 reg = <0x20000000 0x10000>; 599 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, 600 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, 601 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 602 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, 603 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 604 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 605 interrupt-names = "gp", 606 "gpmmu", 607 "pp0", 608 "ppmmu0", 609 "pp1", 610 "ppmmu1"; 611 clocks = <&cru ACLK_GPU>, <&cru ACLK_GPU>; 612 clock-names = "bus", "core"; 613 power-domains = <&power RK3228_PD_GPU>; 614 resets = <&cru SRST_GPU_A>; 615 status = "disabled"; 616 }; 617 618 vpu: video-codec@20020000 { 619 compatible = "rockchip,rk3228-vpu", "rockchip,rk3399-vpu"; 620 reg = <0x20020000 0x800>; 621 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, 622 <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 623 interrupt-names = "vepu", "vdpu"; 624 clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>; 625 clock-names = "aclk", "hclk"; 626 iommus = <&vpu_mmu>; 627 power-domains = <&power RK3228_PD_VPU>; 628 }; 629 630 vpu_mmu: iommu@20020800 { 631 compatible = "rockchip,iommu"; 632 reg = <0x20020800 0x100>; 633 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 634 clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>; 635 clock-names = "aclk", "iface"; 636 power-domains = <&power RK3228_PD_VPU>; 637 #iommu-cells = <0>; 638 }; 639 640 vdec: video-codec@20030000 { 641 compatible = "rockchip,rk3228-vdec", "rockchip,rk3399-vdec"; 642 reg = <0x20030000 0x480>; 643 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 644 clocks = <&cru ACLK_RKVDEC>, <&cru HCLK_RKVDEC>, 645 <&cru SCLK_VDEC_CABAC>, <&cru SCLK_VDEC_CORE>; 646 clock-names = "axi", "ahb", "cabac", "core"; 647 assigned-clocks = <&cru SCLK_VDEC_CABAC>, <&cru SCLK_VDEC_CORE>; 648 assigned-clock-rates = <300000000>, <300000000>; 649 iommus = <&vdec_mmu>; 650 power-domains = <&power RK3228_PD_RKVDEC>; 651 }; 652 653 vdec_mmu: iommu@20030480 { 654 compatible = "rockchip,iommu"; 655 reg = <0x20030480 0x40>, <0x200304c0 0x40>; 656 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 657 clocks = <&cru ACLK_RKVDEC>, <&cru HCLK_RKVDEC>; 658 clock-names = "aclk", "iface"; 659 power-domains = <&power RK3228_PD_RKVDEC>; 660 #iommu-cells = <0>; 661 }; 662 663 vop: vop@20050000 { 664 compatible = "rockchip,rk3228-vop"; 665 reg = <0x20050000 0x1ffc>; 666 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 667 clocks = <&cru ACLK_VOP>, <&cru DCLK_VOP>, <&cru HCLK_VOP>; 668 clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; 669 resets = <&cru SRST_VOP_A>, <&cru SRST_VOP_H>, <&cru SRST_VOP_D>; 670 reset-names = "axi", "ahb", "dclk"; 671 iommus = <&vop_mmu>; 672 power-domains = <&power RK3228_PD_VOP>; 673 status = "disabled"; 674 675 vop_out: port { 676 #address-cells = <1>; 677 #size-cells = <0>; 678 679 vop_out_hdmi: endpoint@0 { 680 reg = <0>; 681 remote-endpoint = <&hdmi_in_vop>; 682 }; 683 }; 684 }; 685 686 vop_mmu: iommu@20053f00 { 687 compatible = "rockchip,iommu"; 688 reg = <0x20053f00 0x100>; 689 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 690 clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>; 691 clock-names = "aclk", "iface"; 692 power-domains = <&power RK3228_PD_VOP>; 693 #iommu-cells = <0>; 694 status = "disabled"; 695 }; 696 697 rga: rga@20060000 { 698 compatible = "rockchip,rk3228-rga", "rockchip,rk3288-rga"; 699 reg = <0x20060000 0x1000>; 700 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 701 clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru SCLK_RGA>; 702 clock-names = "aclk", "hclk", "sclk"; 703 power-domains = <&power RK3228_PD_VIO>; 704 resets = <&cru SRST_RGA>, <&cru SRST_RGA_A>, <&cru SRST_RGA_H>; 705 reset-names = "core", "axi", "ahb"; 706 }; 707 708 iep_mmu: iommu@20070800 { 709 compatible = "rockchip,iommu"; 710 reg = <0x20070800 0x100>; 711 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 712 clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>; 713 clock-names = "aclk", "iface"; 714 power-domains = <&power RK3228_PD_VIO>; 715 #iommu-cells = <0>; 716 status = "disabled"; 717 }; 718 719 hdmi: hdmi@200a0000 { 720 compatible = "rockchip,rk3228-dw-hdmi"; 721 reg = <0x200a0000 0x20000>; 722 reg-io-width = <4>; 723 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 724 assigned-clocks = <&cru SCLK_HDMI_PHY>; 725 assigned-clock-parents = <&hdmi_phy>; 726 clocks = <&cru PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_HDCP>, <&cru SCLK_HDMI_CEC>; 727 clock-names = "iahb", "isfr", "cec"; 728 pinctrl-names = "default"; 729 pinctrl-0 = <&hdmii2c_xfer &hdmi_hpd &hdmi_cec>; 730 resets = <&cru SRST_HDMI_P>; 731 reset-names = "hdmi"; 732 phys = <&hdmi_phy>; 733 phy-names = "hdmi"; 734 rockchip,grf = <&grf>; 735 status = "disabled"; 736 737 ports { 738 #address-cells = <1>; 739 #size-cells = <0>; 740 741 hdmi_in: port@0 { 742 reg = <0>; 743 744 hdmi_in_vop: endpoint { 745 remote-endpoint = <&vop_out_hdmi>; 746 }; 747 }; 748 749 hdmi_out: port@1 { 750 reg = <1>; 751 }; 752 }; 753 }; 754 755 sdmmc: mmc@30000000 { 756 compatible = "rockchip,rk3228-dw-mshc", "rockchip,rk3288-dw-mshc"; 757 reg = <0x30000000 0x4000>; 758 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 759 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>, 760 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>; 761 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 762 fifo-depth = <0x100>; 763 pinctrl-names = "default"; 764 pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_bus4>; 765 status = "disabled"; 766 }; 767 768 sdio: mmc@30010000 { 769 compatible = "rockchip,rk3228-dw-mshc", "rockchip,rk3288-dw-mshc"; 770 reg = <0x30010000 0x4000>; 771 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 772 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>, 773 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>; 774 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 775 fifo-depth = <0x100>; 776 pinctrl-names = "default"; 777 pinctrl-0 = <&sdio_clk &sdio_cmd &sdio_bus4>; 778 status = "disabled"; 779 }; 780 781 emmc: mmc@30020000 { 782 compatible = "rockchip,rk3228-dw-mshc", "rockchip,rk3288-dw-mshc"; 783 reg = <0x30020000 0x4000>; 784 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 785 clock-frequency = <37500000>; 786 max-frequency = <37500000>; 787 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>, 788 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>; 789 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 790 bus-width = <8>; 791 rockchip,default-sample-phase = <158>; 792 fifo-depth = <0x100>; 793 pinctrl-names = "default"; 794 pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>; 795 resets = <&cru SRST_EMMC>; 796 reset-names = "reset"; 797 status = "disabled"; 798 }; 799 800 usb_otg: usb@30040000 { 801 compatible = "rockchip,rk3228-usb", "rockchip,rk3066-usb", 802 "snps,dwc2"; 803 reg = <0x30040000 0x40000>; 804 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 805 clocks = <&cru HCLK_OTG>; 806 clock-names = "otg"; 807 dr_mode = "otg"; 808 g-np-tx-fifo-size = <16>; 809 g-rx-fifo-size = <280>; 810 g-tx-fifo-size = <256 128 128 64 32 16>; 811 phys = <&u2phy0_otg>; 812 phy-names = "usb2-phy"; 813 status = "disabled"; 814 }; 815 816 usb_host0_ehci: usb@30080000 { 817 compatible = "generic-ehci"; 818 reg = <0x30080000 0x20000>; 819 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 820 clocks = <&cru HCLK_HOST0>, <&u2phy0>; 821 phys = <&u2phy0_host>; 822 phy-names = "usb"; 823 status = "disabled"; 824 }; 825 826 usb_host0_ohci: usb@300a0000 { 827 compatible = "generic-ohci"; 828 reg = <0x300a0000 0x20000>; 829 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 830 clocks = <&cru HCLK_HOST0>, <&u2phy0>; 831 phys = <&u2phy0_host>; 832 phy-names = "usb"; 833 status = "disabled"; 834 }; 835 836 usb_host1_ehci: usb@300c0000 { 837 compatible = "generic-ehci"; 838 reg = <0x300c0000 0x20000>; 839 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 840 clocks = <&cru HCLK_HOST1>, <&u2phy1>; 841 phys = <&u2phy1_otg>; 842 phy-names = "usb"; 843 status = "disabled"; 844 }; 845 846 usb_host1_ohci: usb@300e0000 { 847 compatible = "generic-ohci"; 848 reg = <0x300e0000 0x20000>; 849 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 850 clocks = <&cru HCLK_HOST1>, <&u2phy1>; 851 phys = <&u2phy1_otg>; 852 phy-names = "usb"; 853 status = "disabled"; 854 }; 855 856 usb_host2_ehci: usb@30100000 { 857 compatible = "generic-ehci"; 858 reg = <0x30100000 0x20000>; 859 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>; 860 clocks = <&cru HCLK_HOST2>, <&u2phy1>; 861 phys = <&u2phy1_host>; 862 phy-names = "usb"; 863 status = "disabled"; 864 }; 865 866 usb_host2_ohci: usb@30120000 { 867 compatible = "generic-ohci"; 868 reg = <0x30120000 0x20000>; 869 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; 870 clocks = <&cru HCLK_HOST2>, <&u2phy1>; 871 phys = <&u2phy1_host>; 872 phy-names = "usb"; 873 status = "disabled"; 874 }; 875 876 gmac: ethernet@30200000 { 877 compatible = "rockchip,rk3228-gmac"; 878 reg = <0x30200000 0x10000>; 879 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; 880 interrupt-names = "macirq"; 881 clocks = <&cru SCLK_MAC>, <&cru SCLK_MAC_RX>, 882 <&cru SCLK_MAC_TX>, <&cru SCLK_MAC_REF>, 883 <&cru SCLK_MAC_REFOUT>, <&cru ACLK_GMAC>, 884 <&cru PCLK_GMAC>; 885 clock-names = "stmmaceth", "mac_clk_rx", 886 "mac_clk_tx", "clk_mac_ref", 887 "clk_mac_refout", "aclk_mac", 888 "pclk_mac"; 889 resets = <&cru SRST_GMAC>; 890 reset-names = "stmmaceth"; 891 rockchip,grf = <&grf>; 892 status = "disabled"; 893 }; 894 895 qos_iep: qos@31030080 { 896 compatible = "rockchip,rk3228-qos", "syscon"; 897 reg = <0x31030080 0x20>; 898 }; 899 900 qos_rga_w: qos@31030100 { 901 compatible = "rockchip,rk3228-qos", "syscon"; 902 reg = <0x31030100 0x20>; 903 }; 904 905 qos_hdcp: qos@31030180 { 906 compatible = "rockchip,rk3228-qos", "syscon"; 907 reg = <0x31030180 0x20>; 908 }; 909 910 qos_rga_r: qos@31030200 { 911 compatible = "rockchip,rk3228-qos", "syscon"; 912 reg = <0x31030200 0x20>; 913 }; 914 915 qos_vpu: qos@31040000 { 916 compatible = "rockchip,rk3228-qos", "syscon"; 917 reg = <0x31040000 0x20>; 918 }; 919 920 qos_gpu: qos@31050000 { 921 compatible = "rockchip,rk3228-qos", "syscon"; 922 reg = <0x31050000 0x20>; 923 }; 924 925 qos_vop: qos@31060000 { 926 compatible = "rockchip,rk3228-qos", "syscon"; 927 reg = <0x31060000 0x20>; 928 }; 929 930 qos_rkvdec_r: qos@31070000 { 931 compatible = "rockchip,rk3228-qos", "syscon"; 932 reg = <0x31070000 0x20>; 933 }; 934 935 qos_rkvdec_w: qos@31070080 { 936 compatible = "rockchip,rk3228-qos", "syscon"; 937 reg = <0x31070080 0x20>; 938 }; 939 940 gic: interrupt-controller@32010000 { 941 compatible = "arm,gic-400"; 942 interrupt-controller; 943 #interrupt-cells = <3>; 944 #address-cells = <0>; 945 946 reg = <0x32011000 0x1000>, 947 <0x32012000 0x2000>, 948 <0x32014000 0x2000>, 949 <0x32016000 0x2000>; 950 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 951 }; 952 953 pinctrl: pinctrl { 954 compatible = "rockchip,rk3228-pinctrl"; 955 rockchip,grf = <&grf>; 956 #address-cells = <1>; 957 #size-cells = <1>; 958 ranges; 959 960 gpio0: gpio@11110000 { 961 compatible = "rockchip,gpio-bank"; 962 reg = <0x11110000 0x100>; 963 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; 964 clocks = <&cru PCLK_GPIO0>; 965 966 gpio-controller; 967 #gpio-cells = <2>; 968 969 interrupt-controller; 970 #interrupt-cells = <2>; 971 }; 972 973 gpio1: gpio@11120000 { 974 compatible = "rockchip,gpio-bank"; 975 reg = <0x11120000 0x100>; 976 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; 977 clocks = <&cru PCLK_GPIO1>; 978 979 gpio-controller; 980 #gpio-cells = <2>; 981 982 interrupt-controller; 983 #interrupt-cells = <2>; 984 }; 985 986 gpio2: gpio@11130000 { 987 compatible = "rockchip,gpio-bank"; 988 reg = <0x11130000 0x100>; 989 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 990 clocks = <&cru PCLK_GPIO2>; 991 992 gpio-controller; 993 #gpio-cells = <2>; 994 995 interrupt-controller; 996 #interrupt-cells = <2>; 997 }; 998 999 gpio3: gpio@11140000 { 1000 compatible = "rockchip,gpio-bank"; 1001 reg = <0x11140000 0x100>; 1002 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; 1003 clocks = <&cru PCLK_GPIO3>; 1004 1005 gpio-controller; 1006 #gpio-cells = <2>; 1007 1008 interrupt-controller; 1009 #interrupt-cells = <2>; 1010 }; 1011 1012 pcfg_pull_up: pcfg-pull-up { 1013 bias-pull-up; 1014 }; 1015 1016 pcfg_pull_down: pcfg-pull-down { 1017 bias-pull-down; 1018 }; 1019 1020 pcfg_pull_none: pcfg-pull-none { 1021 bias-disable; 1022 }; 1023 1024 pcfg_pull_none_drv_12ma: pcfg-pull-none-drv-12ma { 1025 drive-strength = <12>; 1026 }; 1027 1028 sdmmc { 1029 sdmmc_clk: sdmmc-clk { 1030 rockchip,pins = <1 RK_PC0 1 &pcfg_pull_none_drv_12ma>; 1031 }; 1032 1033 sdmmc_cmd: sdmmc-cmd { 1034 rockchip,pins = <1 RK_PB7 1 &pcfg_pull_none_drv_12ma>; 1035 }; 1036 1037 sdmmc_bus4: sdmmc-bus4 { 1038 rockchip,pins = <1 RK_PC2 1 &pcfg_pull_none_drv_12ma>, 1039 <1 RK_PC3 1 &pcfg_pull_none_drv_12ma>, 1040 <1 RK_PC4 1 &pcfg_pull_none_drv_12ma>, 1041 <1 RK_PC5 1 &pcfg_pull_none_drv_12ma>; 1042 }; 1043 }; 1044 1045 sdio { 1046 sdio_clk: sdio-clk { 1047 rockchip,pins = <3 RK_PA0 1 &pcfg_pull_none_drv_12ma>; 1048 }; 1049 1050 sdio_cmd: sdio-cmd { 1051 rockchip,pins = <3 RK_PA1 1 &pcfg_pull_none_drv_12ma>; 1052 }; 1053 1054 sdio_bus4: sdio-bus4 { 1055 rockchip,pins = <3 RK_PA2 1 &pcfg_pull_none_drv_12ma>, 1056 <3 RK_PA3 1 &pcfg_pull_none_drv_12ma>, 1057 <3 RK_PA4 1 &pcfg_pull_none_drv_12ma>, 1058 <3 RK_PA5 1 &pcfg_pull_none_drv_12ma>; 1059 }; 1060 }; 1061 1062 emmc { 1063 emmc_clk: emmc-clk { 1064 rockchip,pins = <2 RK_PA7 2 &pcfg_pull_none>; 1065 }; 1066 1067 emmc_cmd: emmc-cmd { 1068 rockchip,pins = <1 RK_PC6 2 &pcfg_pull_none>; 1069 }; 1070 1071 emmc_bus8: emmc-bus8 { 1072 rockchip,pins = <1 RK_PD0 2 &pcfg_pull_none>, 1073 <1 RK_PD1 2 &pcfg_pull_none>, 1074 <1 RK_PD2 2 &pcfg_pull_none>, 1075 <1 RK_PD3 2 &pcfg_pull_none>, 1076 <1 RK_PD4 2 &pcfg_pull_none>, 1077 <1 RK_PD5 2 &pcfg_pull_none>, 1078 <1 RK_PD6 2 &pcfg_pull_none>, 1079 <1 RK_PD7 2 &pcfg_pull_none>; 1080 }; 1081 }; 1082 1083 gmac { 1084 rgmii_pins: rgmii-pins { 1085 rockchip,pins = <2 RK_PB6 1 &pcfg_pull_none>, 1086 <2 RK_PB4 1 &pcfg_pull_none>, 1087 <2 RK_PD1 1 &pcfg_pull_none>, 1088 <2 RK_PC3 1 &pcfg_pull_none_drv_12ma>, 1089 <2 RK_PC2 1 &pcfg_pull_none_drv_12ma>, 1090 <2 RK_PC6 1 &pcfg_pull_none_drv_12ma>, 1091 <2 RK_PC7 1 &pcfg_pull_none_drv_12ma>, 1092 <2 RK_PB1 1 &pcfg_pull_none_drv_12ma>, 1093 <2 RK_PB5 1 &pcfg_pull_none_drv_12ma>, 1094 <2 RK_PC1 1 &pcfg_pull_none>, 1095 <2 RK_PC0 1 &pcfg_pull_none>, 1096 <2 RK_PC5 2 &pcfg_pull_none>, 1097 <2 RK_PC4 2 &pcfg_pull_none>, 1098 <2 RK_PB3 1 &pcfg_pull_none>, 1099 <2 RK_PB0 1 &pcfg_pull_none>; 1100 }; 1101 1102 rmii_pins: rmii-pins { 1103 rockchip,pins = <2 RK_PB6 1 &pcfg_pull_none>, 1104 <2 RK_PB4 1 &pcfg_pull_none>, 1105 <2 RK_PD1 1 &pcfg_pull_none>, 1106 <2 RK_PC3 1 &pcfg_pull_none_drv_12ma>, 1107 <2 RK_PC2 1 &pcfg_pull_none_drv_12ma>, 1108 <2 RK_PB5 1 &pcfg_pull_none_drv_12ma>, 1109 <2 RK_PC1 1 &pcfg_pull_none>, 1110 <2 RK_PC0 1 &pcfg_pull_none>, 1111 <2 RK_PB0 1 &pcfg_pull_none>, 1112 <2 RK_PB7 1 &pcfg_pull_none>; 1113 }; 1114 1115 phy_pins: phy-pins { 1116 rockchip,pins = <2 RK_PB6 2 &pcfg_pull_none>, 1117 <2 RK_PB0 2 &pcfg_pull_none>; 1118 }; 1119 }; 1120 1121 hdmi { 1122 hdmi_hpd: hdmi-hpd { 1123 rockchip,pins = <0 RK_PB7 1 &pcfg_pull_down>; 1124 }; 1125 1126 hdmii2c_xfer: hdmii2c-xfer { 1127 rockchip,pins = <0 RK_PA6 2 &pcfg_pull_none>, 1128 <0 RK_PA7 2 &pcfg_pull_none>; 1129 }; 1130 1131 hdmi_cec: hdmi-cec { 1132 rockchip,pins = <0 RK_PC4 1 &pcfg_pull_none>; 1133 }; 1134 }; 1135 1136 i2c0 { 1137 i2c0_xfer: i2c0-xfer { 1138 rockchip,pins = <0 RK_PA0 1 &pcfg_pull_none>, 1139 <0 RK_PA1 1 &pcfg_pull_none>; 1140 }; 1141 }; 1142 1143 i2c1 { 1144 i2c1_xfer: i2c1-xfer { 1145 rockchip,pins = <0 RK_PA2 1 &pcfg_pull_none>, 1146 <0 RK_PA3 1 &pcfg_pull_none>; 1147 }; 1148 }; 1149 1150 i2c2 { 1151 i2c2_xfer: i2c2-xfer { 1152 rockchip,pins = <2 RK_PC4 1 &pcfg_pull_none>, 1153 <2 RK_PC5 1 &pcfg_pull_none>; 1154 }; 1155 }; 1156 1157 i2c3 { 1158 i2c3_xfer: i2c3-xfer { 1159 rockchip,pins = <0 RK_PA6 1 &pcfg_pull_none>, 1160 <0 RK_PA7 1 &pcfg_pull_none>; 1161 }; 1162 }; 1163 1164 spi0 { 1165 spi0_clk: spi0-clk { 1166 rockchip,pins = <0 RK_PB1 2 &pcfg_pull_up>; 1167 }; 1168 spi0_cs0: spi0-cs0 { 1169 rockchip,pins = <0 RK_PB6 2 &pcfg_pull_up>; 1170 }; 1171 spi0_tx: spi0-tx { 1172 rockchip,pins = <0 RK_PB3 2 &pcfg_pull_up>; 1173 }; 1174 spi0_rx: spi0-rx { 1175 rockchip,pins = <0 RK_PB5 2 &pcfg_pull_up>; 1176 }; 1177 spi0_cs1: spi0-cs1 { 1178 rockchip,pins = <1 RK_PB4 1 &pcfg_pull_up>; 1179 }; 1180 }; 1181 1182 spi1 { 1183 spi1_clk: spi1-clk { 1184 rockchip,pins = <0 RK_PC7 2 &pcfg_pull_up>; 1185 }; 1186 spi1_cs0: spi1-cs0 { 1187 rockchip,pins = <2 RK_PA2 2 &pcfg_pull_up>; 1188 }; 1189 spi1_rx: spi1-rx { 1190 rockchip,pins = <2 RK_PA0 2 &pcfg_pull_up>; 1191 }; 1192 spi1_tx: spi1-tx { 1193 rockchip,pins = <2 RK_PA1 2 &pcfg_pull_up>; 1194 }; 1195 spi1_cs1: spi1-cs1 { 1196 rockchip,pins = <2 RK_PA3 2 &pcfg_pull_up>; 1197 }; 1198 }; 1199 1200 i2s1 { 1201 i2s1_bus: i2s1-bus { 1202 rockchip,pins = <0 RK_PB0 1 &pcfg_pull_none>, 1203 <0 RK_PB1 1 &pcfg_pull_none>, 1204 <0 RK_PB3 1 &pcfg_pull_none>, 1205 <0 RK_PB4 1 &pcfg_pull_none>, 1206 <0 RK_PB5 1 &pcfg_pull_none>, 1207 <0 RK_PB6 1 &pcfg_pull_none>, 1208 <1 RK_PA2 2 &pcfg_pull_none>, 1209 <1 RK_PA4 2 &pcfg_pull_none>, 1210 <1 RK_PA5 2 &pcfg_pull_none>; 1211 }; 1212 }; 1213 1214 pwm0 { 1215 pwm0_pin: pwm0-pin { 1216 rockchip,pins = <3 RK_PC5 1 &pcfg_pull_none>; 1217 }; 1218 }; 1219 1220 pwm1 { 1221 pwm1_pin: pwm1-pin { 1222 rockchip,pins = <0 RK_PD6 2 &pcfg_pull_none>; 1223 }; 1224 }; 1225 1226 pwm2 { 1227 pwm2_pin: pwm2-pin { 1228 rockchip,pins = <1 RK_PB4 2 &pcfg_pull_none>; 1229 }; 1230 }; 1231 1232 pwm3 { 1233 pwm3_pin: pwm3-pin { 1234 rockchip,pins = <1 RK_PB3 2 &pcfg_pull_none>; 1235 }; 1236 }; 1237 1238 spdif { 1239 spdif_tx: spdif-tx { 1240 rockchip,pins = <3 RK_PD7 2 &pcfg_pull_none>; 1241 }; 1242 }; 1243 1244 tsadc { 1245 otp_pin: otp-pin { 1246 rockchip,pins = <0 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>; 1247 }; 1248 1249 otp_out: otp-out { 1250 rockchip,pins = <0 RK_PD0 2 &pcfg_pull_none>; 1251 }; 1252 }; 1253 1254 uart0 { 1255 uart0_xfer: uart0-xfer { 1256 rockchip,pins = <2 RK_PD2 1 &pcfg_pull_none>, 1257 <2 RK_PD3 1 &pcfg_pull_none>; 1258 }; 1259 1260 uart0_cts: uart0-cts { 1261 rockchip,pins = <2 RK_PD5 1 &pcfg_pull_none>; 1262 }; 1263 1264 uart0_rts: uart0-rts { 1265 rockchip,pins = <0 RK_PC1 1 &pcfg_pull_none>; 1266 }; 1267 }; 1268 1269 uart1 { 1270 uart1_xfer: uart1-xfer { 1271 rockchip,pins = <1 RK_PB1 1 &pcfg_pull_none>, 1272 <1 RK_PB2 1 &pcfg_pull_none>; 1273 }; 1274 1275 uart1_cts: uart1-cts { 1276 rockchip,pins = <1 RK_PB0 1 &pcfg_pull_none>; 1277 }; 1278 1279 uart1_rts: uart1-rts { 1280 rockchip,pins = <1 RK_PB3 1 &pcfg_pull_none>; 1281 }; 1282 }; 1283 1284 uart2 { 1285 uart2_xfer: uart2-xfer { 1286 rockchip,pins = <1 RK_PC2 2 &pcfg_pull_up>, 1287 <1 RK_PC3 2 &pcfg_pull_none>; 1288 }; 1289 1290 uart21_xfer: uart21-xfer { 1291 rockchip,pins = <1 RK_PB2 2 &pcfg_pull_up>, 1292 <1 RK_PB1 2 &pcfg_pull_none>; 1293 }; 1294 1295 uart2_cts: uart2-cts { 1296 rockchip,pins = <0 RK_PD1 1 &pcfg_pull_none>; 1297 }; 1298 1299 uart2_rts: uart2-rts { 1300 rockchip,pins = <0 RK_PD0 1 &pcfg_pull_none>; 1301 }; 1302 }; 1303 }; 1304};
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