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rk3128.dtsi
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linux-6.19.14/arch/arm/boot/dts/rockchip/rk3128.dtsi
1// SPDX-License-Identifier: GPL-2.0+ 2/* 3 * (C) Copyright 2017 Rockchip Electronics Co., Ltd 4 */ 5 6#include <dt-bindings/clock/rk3128-cru.h> 7#include <dt-bindings/gpio/gpio.h> 8#include <dt-bindings/interrupt-controller/arm-gic.h> 9#include <dt-bindings/interrupt-controller/irq.h> 10#include <dt-bindings/pinctrl/rockchip.h> 11#include <dt-bindings/power/rk3128-power.h> 12 13/ { 14 compatible = "rockchip,rk3128"; 15 interrupt-parent = <&gic>; 16 #address-cells = <1>; 17 #size-cells = <1>; 18 19 aliases { 20 gpio0 = &gpio0; 21 gpio1 = &gpio1; 22 gpio2 = &gpio2; 23 gpio3 = &gpio3; 24 i2c0 = &i2c0; 25 i2c1 = &i2c1; 26 i2c2 = &i2c2; 27 i2c3 = &i2c3; 28 serial0 = &uart0; 29 serial1 = &uart1; 30 serial2 = &uart2; 31 }; 32 33 arm-pmu { 34 compatible = "arm,cortex-a7-pmu"; 35 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>, 36 <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>, 37 <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>, 38 <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; 39 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; 40 }; 41 42 cpus { 43 #address-cells = <1>; 44 #size-cells = <0>; 45 enable-method = "rockchip,rk3036-smp"; 46 47 cpu0: cpu@f00 { 48 device_type = "cpu"; 49 compatible = "arm,cortex-a7"; 50 reg = <0xf00>; 51 clocks = <&cru ARMCLK>; 52 resets = <&cru SRST_CORE0>; 53 operating-points-v2 = <&cpu_opp_table>; 54 #cooling-cells = <2>; /* min followed by max */ 55 }; 56 57 cpu1: cpu@f01 { 58 device_type = "cpu"; 59 compatible = "arm,cortex-a7"; 60 reg = <0xf01>; 61 resets = <&cru SRST_CORE1>; 62 operating-points-v2 = <&cpu_opp_table>; 63 }; 64 65 cpu2: cpu@f02 { 66 device_type = "cpu"; 67 compatible = "arm,cortex-a7"; 68 reg = <0xf02>; 69 resets = <&cru SRST_CORE2>; 70 operating-points-v2 = <&cpu_opp_table>; 71 }; 72 73 cpu3: cpu@f03 { 74 device_type = "cpu"; 75 compatible = "arm,cortex-a7"; 76 reg = <0xf03>; 77 resets = <&cru SRST_CORE3>; 78 operating-points-v2 = <&cpu_opp_table>; 79 }; 80 }; 81 82 cpu_opp_table: opp-table-0 { 83 compatible = "operating-points-v2"; 84 opp-shared; 85 86 opp-216000000 { 87 opp-hz = /bits/ 64 <216000000>; 88 opp-microvolt = <950000 950000 1325000>; 89 clock-latency-ns = <40000>; 90 }; 91 opp-408000000 { 92 opp-hz = /bits/ 64 <408000000>; 93 opp-microvolt = <950000 950000 1325000>; 94 clock-latency-ns = <40000>; 95 }; 96 opp-600000000 { 97 opp-hz = /bits/ 64 <600000000>; 98 opp-microvolt = <950000 950000 1325000>; 99 clock-latency-ns = <40000>; 100 }; 101 opp-696000000 { 102 opp-hz = /bits/ 64 <696000000>; 103 opp-microvolt = <975000 975000 1325000>; 104 clock-latency-ns = <40000>; 105 }; 106 opp-816000000 { 107 opp-hz = /bits/ 64 <816000000>; 108 opp-microvolt = <1075000 1075000 1325000>; 109 opp-suspend; 110 clock-latency-ns = <40000>; 111 }; 112 opp-1008000000 { 113 opp-hz = /bits/ 64 <1008000000>; 114 opp-microvolt = <1200000 1200000 1325000>; 115 clock-latency-ns = <40000>; 116 }; 117 opp-1200000000 { 118 opp-hz = /bits/ 64 <1200000000>; 119 opp-microvolt = <1325000 1325000 1325000>; 120 clock-latency-ns = <40000>; 121 }; 122 }; 123 124 display_subsystem: display-subsystem { 125 compatible = "rockchip,display-subsystem"; 126 ports = <&vop_out>; 127 status = "disabled"; 128 }; 129 130 gpu_opp_table: opp-table-1 { 131 compatible = "operating-points-v2"; 132 133 opp-200000000 { 134 opp-hz = /bits/ 64 <200000000>; 135 opp-microvolt = <975000 975000 1250000>; 136 }; 137 opp-300000000 { 138 opp-hz = /bits/ 64 <300000000>; 139 opp-microvolt = <1050000 1050000 1250000>; 140 }; 141 opp-400000000 { 142 opp-hz = /bits/ 64 <400000000>; 143 opp-microvolt = <1150000 1150000 1250000>; 144 }; 145 opp-480000000 { 146 opp-hz = /bits/ 64 <480000000>; 147 opp-microvolt = <1250000 1250000 1250000>; 148 }; 149 }; 150 151 timer { 152 compatible = "arm,armv7-timer"; 153 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 154 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 155 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 156 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 157 arm,cpu-registers-not-fw-configured; 158 clock-frequency = <24000000>; 159 }; 160 161 xin24m: oscillator { 162 compatible = "fixed-clock"; 163 clock-frequency = <24000000>; 164 clock-output-names = "xin24m"; 165 #clock-cells = <0>; 166 }; 167 168 imem: sram@10080000 { 169 compatible = "mmio-sram"; 170 reg = <0x10080000 0x2000>; 171 #address-cells = <1>; 172 #size-cells = <1>; 173 ranges = <0 0x10080000 0x2000>; 174 175 smp-sram@0 { 176 compatible = "rockchip,rk3066-smp-sram"; 177 reg = <0x00 0x10>; 178 }; 179 }; 180 181 gpu: gpu@10090000 { 182 compatible = "rockchip,rk3128-mali", "arm,mali-400"; 183 reg = <0x10090000 0x10000>; 184 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 185 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 186 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, 187 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 188 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, 189 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 190 interrupt-names = "gp", 191 "gpmmu", 192 "pp0", 193 "ppmmu0", 194 "pp1", 195 "ppmmu1"; 196 clocks = <&cru ACLK_GPU>, <&cru ACLK_GPU>; 197 clock-names = "bus", "core"; 198 operating-points-v2 = <&gpu_opp_table>; 199 resets = <&cru SRST_GPU>; 200 power-domains = <&power RK3128_PD_GPU>; 201 status = "disabled"; 202 }; 203 204 pmu: syscon@100a0000 { 205 compatible = "rockchip,rk3128-pmu", "syscon", "simple-mfd"; 206 reg = <0x100a0000 0x1000>; 207 208 power: power-controller { 209 compatible = "rockchip,rk3128-power-controller"; 210 #power-domain-cells = <1>; 211 #address-cells = <1>; 212 #size-cells = <0>; 213 214 power-domain@RK3128_PD_VIO { 215 reg = <RK3128_PD_VIO>; 216 clocks = <&cru ACLK_CIF>, 217 <&cru HCLK_CIF>, 218 <&cru DCLK_EBC>, 219 <&cru HCLK_EBC>, 220 <&cru ACLK_IEP>, 221 <&cru HCLK_IEP>, 222 <&cru ACLK_LCDC0>, 223 <&cru HCLK_LCDC0>, 224 <&cru PCLK_MIPI>, 225 <&cru PCLK_MIPIPHY>, 226 <&cru SCLK_MIPI_24M>, 227 <&cru ACLK_RGA>, 228 <&cru HCLK_RGA>, 229 <&cru ACLK_VIO0>, 230 <&cru ACLK_VIO1>, 231 <&cru HCLK_VIO>, 232 <&cru HCLK_VIO_H2P>, 233 <&cru DCLK_VOP>, 234 <&cru SCLK_VOP>; 235 pm_qos = <&qos_ebc>, 236 <&qos_iep>, 237 <&qos_lcdc>, 238 <&qos_rga>, 239 <&qos_vip>; 240 #power-domain-cells = <0>; 241 }; 242 243 power-domain@RK3128_PD_VIDEO { 244 reg = <RK3128_PD_VIDEO>; 245 clocks = <&cru ACLK_VDPU>, 246 <&cru HCLK_VDPU>, 247 <&cru ACLK_VEPU>, 248 <&cru HCLK_VEPU>, 249 <&cru SCLK_HEVC_CORE>; 250 pm_qos = <&qos_vpu>; 251 #power-domain-cells = <0>; 252 }; 253 254 power-domain@RK3128_PD_GPU { 255 reg = <RK3128_PD_GPU>; 256 clocks = <&cru ACLK_GPU>; 257 pm_qos = <&qos_gpu>; 258 #power-domain-cells = <0>; 259 }; 260 }; 261 }; 262 263 vpu: video-codec@10106000 { 264 compatible = "rockchip,rk3128-vpu", "rockchip,rk3066-vpu"; 265 reg = <0x10106000 0x800>; 266 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, 267 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 268 interrupt-names = "vepu", "vdpu"; 269 clocks = <&cru ACLK_VDPU>, <&cru HCLK_VDPU>, 270 <&cru ACLK_VEPU>, <&cru HCLK_VEPU>; 271 clock-names = "aclk_vdpu", "hclk_vdpu", 272 "aclk_vepu", "hclk_vepu"; 273 iommus = <&vpu_mmu>; 274 power-domains = <&power RK3128_PD_VIDEO>; 275 }; 276 277 vpu_mmu: iommu@10106800 { 278 compatible = "rockchip,iommu"; 279 reg = <0x10106800 0x100>; 280 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; 281 clocks = <&cru ACLK_VEPU>, <&cru HCLK_VDPU>; 282 clock-names = "aclk", "iface"; 283 power-domains = <&power RK3128_PD_VIDEO>; 284 #iommu-cells = <0>; 285 }; 286 287 vop: vop@1010e000 { 288 compatible = "rockchip,rk3126-vop"; 289 reg = <0x1010e000 0x300>; 290 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 291 clocks = <&cru ACLK_LCDC0>, <&cru DCLK_VOP>, 292 <&cru HCLK_LCDC0>; 293 clock-names = "aclk_vop", "dclk_vop", 294 "hclk_vop"; 295 resets = <&cru SRST_VOP_A>, <&cru SRST_VOP_H>, 296 <&cru SRST_VOP_D>; 297 reset-names = "axi", "ahb", 298 "dclk"; 299 power-domains = <&power RK3128_PD_VIO>; 300 status = "disabled"; 301 302 vop_out: port { 303 #address-cells = <1>; 304 #size-cells = <0>; 305 306 vop_out_hdmi: endpoint@0 { 307 reg = <0>; 308 remote-endpoint = <&hdmi_in_vop>; 309 }; 310 311 vop_out_dsi: endpoint@1 { 312 reg = <1>; 313 remote-endpoint = <&dsi_in_vop>; 314 }; 315 }; 316 }; 317 318 dsi: dsi@10110000 { 319 compatible = "rockchip,rk3128-mipi-dsi", "snps,dw-mipi-dsi"; 320 reg = <0x10110000 0x4000>; 321 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 322 clocks = <&cru PCLK_MIPI>; 323 clock-names = "pclk"; 324 phys = <&dphy>; 325 phy-names = "dphy"; 326 power-domains = <&power RK3128_PD_VIO>; 327 resets = <&cru SRST_VIO_MIPI_DSI>; 328 reset-names = "apb"; 329 rockchip,grf = <&grf>; 330 status = "disabled"; 331 332 ports { 333 #address-cells = <1>; 334 #size-cells = <0>; 335 336 dsi_in: port@0 { 337 reg = <0>; 338 339 dsi_in_vop: endpoint { 340 remote-endpoint = <&vop_out_dsi>; 341 }; 342 }; 343 344 dsi_out: port@1 { 345 reg = <1>; 346 }; 347 }; 348 }; 349 350 qos_gpu: qos@1012d000 { 351 compatible = "rockchip,rk3128-qos", "syscon"; 352 reg = <0x1012d000 0x20>; 353 }; 354 355 qos_vpu: qos@1012e000 { 356 compatible = "rockchip,rk3128-qos", "syscon"; 357 reg = <0x1012e000 0x20>; 358 }; 359 360 qos_rga: qos@1012f000 { 361 compatible = "rockchip,rk3128-qos", "syscon"; 362 reg = <0x1012f000 0x20>; 363 }; 364 365 qos_ebc: qos@1012f080 { 366 compatible = "rockchip,rk3128-qos", "syscon"; 367 reg = <0x1012f080 0x20>; 368 }; 369 370 qos_iep: qos@1012f100 { 371 compatible = "rockchip,rk3128-qos", "syscon"; 372 reg = <0x1012f100 0x20>; 373 }; 374 375 qos_lcdc: qos@1012f180 { 376 compatible = "rockchip,rk3128-qos", "syscon"; 377 reg = <0x1012f180 0x20>; 378 }; 379 380 qos_vip: qos@1012f200 { 381 compatible = "rockchip,rk3128-qos", "syscon"; 382 reg = <0x1012f200 0x20>; 383 }; 384 385 gic: interrupt-controller@10139000 { 386 compatible = "arm,cortex-a7-gic"; 387 reg = <0x10139000 0x1000>, 388 <0x1013a000 0x1000>, 389 <0x1013c000 0x2000>, 390 <0x1013e000 0x2000>; 391 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 392 interrupt-controller; 393 #interrupt-cells = <3>; 394 #address-cells = <0>; 395 }; 396 397 usb_otg: usb@10180000 { 398 compatible = "rockchip,rk3128-usb", "rockchip,rk3066-usb", "snps,dwc2"; 399 reg = <0x10180000 0x40000>; 400 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 401 clocks = <&cru HCLK_OTG>; 402 clock-names = "otg"; 403 dr_mode = "otg"; 404 g-np-tx-fifo-size = <16>; 405 g-rx-fifo-size = <280>; 406 g-tx-fifo-size = <256 128 128 64 32 16>; 407 phys = <&usb2phy_otg>; 408 phy-names = "usb2-phy"; 409 status = "disabled"; 410 }; 411 412 usb_host_ehci: usb@101c0000 { 413 compatible = "generic-ehci"; 414 reg = <0x101c0000 0x20000>; 415 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 416 clocks = <&cru HCLK_HOST2>; 417 phys = <&usb2phy_host>; 418 phy-names = "usb"; 419 status = "disabled"; 420 }; 421 422 usb_host_ohci: usb@101e0000 { 423 compatible = "generic-ohci"; 424 reg = <0x101e0000 0x20000>; 425 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 426 clocks = <&cru HCLK_HOST2>; 427 phys = <&usb2phy_host>; 428 phy-names = "usb"; 429 status = "disabled"; 430 }; 431 432 i2s_8ch: i2s@10200000 { 433 compatible = "rockchip,rk3128-i2s", "rockchip,rk3066-i2s"; 434 reg = <0x10200000 0x1000>; 435 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>; 436 clocks = <&cru SCLK_I2S0>, <&cru HCLK_I2S_8CH>; 437 clock-names = "i2s_clk", "i2s_hclk"; 438 dmas = <&pdma 14>, <&pdma 15>; 439 dma-names = "tx", "rx"; 440 #sound-dai-cells = <0>; 441 status = "disabled"; 442 }; 443 444 spdif: spdif@10204000 { 445 compatible = "rockchip,rk3128-spdif", "rockchip,rk3066-spdif"; 446 reg = <0x10204000 0x1000>; 447 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; 448 clocks = <&cru SCLK_SPDIF>, <&cru HCLK_SPDIF>; 449 clock-names = "mclk", "hclk"; 450 dmas = <&pdma 13>; 451 dma-names = "tx"; 452 pinctrl-names = "default"; 453 pinctrl-0 = <&spdif_tx>; 454 #sound-dai-cells = <0>; 455 status = "disabled"; 456 }; 457 458 sfc: spi@1020c000 { 459 compatible = "rockchip,sfc"; 460 reg = <0x1020c000 0x8000>; 461 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; 462 clocks = <&cru SCLK_SFC>, <&cru HCLK_SFC>; 463 clock-names = "clk_sfc", "hclk_sfc"; 464 status = "disabled"; 465 }; 466 467 sdmmc: mmc@10214000 { 468 compatible = "rockchip,rk3128-dw-mshc", "rockchip,rk3288-dw-mshc"; 469 reg = <0x10214000 0x4000>; 470 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 471 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>, 472 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>; 473 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 474 dmas = <&pdma 10>; 475 dma-names = "rx-tx"; 476 fifo-depth = <256>; 477 max-frequency = <150000000>; 478 resets = <&cru SRST_SDMMC>; 479 reset-names = "reset"; 480 status = "disabled"; 481 }; 482 483 sdio: mmc@10218000 { 484 compatible = "rockchip,rk3128-dw-mshc", "rockchip,rk3288-dw-mshc"; 485 reg = <0x10218000 0x4000>; 486 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 487 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>, 488 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>; 489 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 490 dmas = <&pdma 11>; 491 dma-names = "rx-tx"; 492 fifo-depth = <256>; 493 max-frequency = <150000000>; 494 resets = <&cru SRST_SDIO>; 495 reset-names = "reset"; 496 status = "disabled"; 497 }; 498 499 emmc: mmc@1021c000 { 500 compatible = "rockchip,rk3128-dw-mshc", "rockchip,rk3288-dw-mshc"; 501 reg = <0x1021c000 0x4000>; 502 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 503 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>, 504 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>; 505 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 506 dmas = <&pdma 12>; 507 dma-names = "rx-tx"; 508 fifo-depth = <256>; 509 max-frequency = <150000000>; 510 resets = <&cru SRST_EMMC>; 511 reset-names = "reset"; 512 status = "disabled"; 513 }; 514 515 i2s_2ch: i2s@10220000 { 516 compatible = "rockchip,rk3128-i2s", "rockchip,rk3066-i2s"; 517 reg = <0x10220000 0x1000>; 518 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 519 clocks = <&cru SCLK_I2S1>, <&cru HCLK_I2S_2CH>; 520 clock-names = "i2s_clk", "i2s_hclk"; 521 dmas = <&pdma 0>, <&pdma 1>; 522 dma-names = "tx", "rx"; 523 rockchip,playback-channels = <2>; 524 pinctrl-names = "default"; 525 pinctrl-0 = <&i2s_bus>; 526 #sound-dai-cells = <0>; 527 status = "disabled"; 528 }; 529 530 nfc: nand-controller@10500000 { 531 compatible = "rockchip,rk3128-nfc", "rockchip,rk2928-nfc"; 532 reg = <0x10500000 0x4000>; 533 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>; 534 clocks = <&cru HCLK_NANDC>, <&cru SCLK_NANDC>; 535 clock-names = "ahb", "nfc"; 536 pinctrl-names = "default"; 537 pinctrl-0 = <&flash_ale &flash_bus8 &flash_cle &flash_cs0 538 &flash_dqs &flash_rdn &flash_rdy &flash_wrn>; 539 status = "disabled"; 540 }; 541 542 cru: clock-controller@20000000 { 543 compatible = "rockchip,rk3128-cru"; 544 reg = <0x20000000 0x1000>; 545 clocks = <&xin24m>; 546 clock-names = "xin24m"; 547 rockchip,grf = <&grf>; 548 #clock-cells = <1>; 549 #reset-cells = <1>; 550 assigned-clocks = <&cru PLL_GPLL>; 551 assigned-clock-rates = <594000000>; 552 }; 553 554 grf: syscon@20008000 { 555 compatible = "rockchip,rk3128-grf", "syscon", "simple-mfd"; 556 reg = <0x20008000 0x1000>; 557 #address-cells = <1>; 558 #size-cells = <1>; 559 560 usb2phy: usb2phy@17c { 561 compatible = "rockchip,rk3128-usb2phy"; 562 reg = <0x017c 0x0c>; 563 clocks = <&cru SCLK_OTGPHY0>; 564 clock-names = "phyclk"; 565 clock-output-names = "usb480m_phy"; 566 assigned-clocks = <&cru SCLK_USB480M>; 567 assigned-clock-parents = <&usb2phy>; 568 #clock-cells = <0>; 569 status = "disabled"; 570 571 usb2phy_host: host-port { 572 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 573 interrupt-names = "linestate"; 574 #phy-cells = <0>; 575 status = "disabled"; 576 }; 577 578 usb2phy_otg: otg-port { 579 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>, 580 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, 581 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; 582 interrupt-names = "otg-bvalid", "otg-id", 583 "linestate"; 584 #phy-cells = <0>; 585 status = "disabled"; 586 }; 587 }; 588 }; 589 590 hdmi: hdmi@20034000 { 591 compatible = "rockchip,rk3128-inno-hdmi"; 592 reg = <0x20034000 0x4000>; 593 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 594 clocks = <&cru PCLK_HDMI>, <&cru DCLK_VOP>; 595 clock-names = "pclk", "ref"; 596 pinctrl-names = "default"; 597 pinctrl-0 = <&hdmii2c_xfer &hdmi_hpd &hdmi_cec>; 598 power-domains = <&power RK3128_PD_VIO>; 599 #sound-dai-cells = <0>; 600 status = "disabled"; 601 602 ports { 603 #address-cells = <1>; 604 #size-cells = <0>; 605 606 hdmi_in: port@0 { 607 reg = <0>; 608 hdmi_in_vop: endpoint { 609 remote-endpoint = <&vop_out_hdmi>; 610 }; 611 }; 612 613 hdmi_out: port@1 { 614 reg = <1>; 615 }; 616 }; 617 }; 618 619 dphy: phy@20038000 { 620 compatible = "rockchip,rk3128-dsi-dphy"; 621 reg = <0x20038000 0x4000>; 622 clocks = <&cru SCLK_MIPI_24M>, <&cru PCLK_MIPIPHY>; 623 clock-names = "ref", "pclk"; 624 #phy-cells = <0>; 625 power-domains = <&power RK3128_PD_VIO>; 626 resets = <&cru SRST_MIPIPHY_P>; 627 reset-names = "apb"; 628 status = "disabled"; 629 }; 630 631 timer0: timer@20044000 { 632 compatible = "rockchip,rk3128-timer", "rockchip,rk3288-timer"; 633 reg = <0x20044000 0x20>; 634 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 635 clocks = <&cru PCLK_TIMER>, <&cru SCLK_TIMER0>; 636 clock-names = "pclk", "timer"; 637 }; 638 639 timer1: timer@20044020 { 640 compatible = "rockchip,rk3128-timer", "rockchip,rk3288-timer"; 641 reg = <0x20044020 0x20>; 642 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 643 clocks = <&cru PCLK_TIMER>, <&cru SCLK_TIMER1>; 644 clock-names = "pclk", "timer"; 645 }; 646 647 timer2: timer@20044040 { 648 compatible = "rockchip,rk3128-timer", "rockchip,rk3288-timer"; 649 reg = <0x20044040 0x20>; 650 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; 651 clocks = <&cru PCLK_TIMER>, <&cru SCLK_TIMER2>; 652 clock-names = "pclk", "timer"; 653 }; 654 655 timer3: timer@20044060 { 656 compatible = "rockchip,rk3128-timer", "rockchip,rk3288-timer"; 657 reg = <0x20044060 0x20>; 658 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; 659 clocks = <&cru PCLK_TIMER>, <&cru SCLK_TIMER3>; 660 clock-names = "pclk", "timer"; 661 }; 662 663 timer4: timer@20044080 { 664 compatible = "rockchip,rk3128-timer", "rockchip,rk3288-timer"; 665 reg = <0x20044080 0x20>; 666 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; 667 clocks = <&cru PCLK_TIMER>, <&cru SCLK_TIMER4>; 668 clock-names = "pclk", "timer"; 669 }; 670 671 timer5: timer@200440a0 { 672 compatible = "rockchip,rk3128-timer", "rockchip,rk3288-timer"; 673 reg = <0x200440a0 0x20>; 674 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 675 clocks = <&cru PCLK_TIMER>, <&cru SCLK_TIMER5>; 676 clock-names = "pclk", "timer"; 677 }; 678 679 watchdog: watchdog@2004c000 { 680 compatible = "rockchip,rk3128-wdt", "snps,dw-wdt"; 681 reg = <0x2004c000 0x100>; 682 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 683 clocks = <&cru PCLK_WDT>; 684 status = "disabled"; 685 }; 686 687 pwm0: pwm@20050000 { 688 compatible = "rockchip,rk3128-pwm", "rockchip,rk3288-pwm"; 689 reg = <0x20050000 0x10>; 690 clocks = <&cru PCLK_PWM>; 691 pinctrl-names = "default"; 692 pinctrl-0 = <&pwm0_pin>; 693 #pwm-cells = <3>; 694 status = "disabled"; 695 }; 696 697 pwm1: pwm@20050010 { 698 compatible = "rockchip,rk3128-pwm", "rockchip,rk3288-pwm"; 699 reg = <0x20050010 0x10>; 700 clocks = <&cru PCLK_PWM>; 701 pinctrl-names = "default"; 702 pinctrl-0 = <&pwm1_pin>; 703 #pwm-cells = <3>; 704 status = "disabled"; 705 }; 706 707 pwm2: pwm@20050020 { 708 compatible = "rockchip,rk3128-pwm", "rockchip,rk3288-pwm"; 709 reg = <0x20050020 0x10>; 710 clocks = <&cru PCLK_PWM>; 711 pinctrl-names = "default"; 712 pinctrl-0 = <&pwm2_pin>; 713 #pwm-cells = <3>; 714 status = "disabled"; 715 }; 716 717 pwm3: pwm@20050030 { 718 compatible = "rockchip,rk3128-pwm", "rockchip,rk3288-pwm"; 719 reg = <0x20050030 0x10>; 720 clocks = <&cru PCLK_PWM>; 721 pinctrl-names = "default"; 722 pinctrl-0 = <&pwm3_pin>; 723 #pwm-cells = <3>; 724 status = "disabled"; 725 }; 726 727 i2c1: i2c@20056000 { 728 compatible = "rockchip,rk3128-i2c", "rockchip,rk3288-i2c"; 729 reg = <0x20056000 0x1000>; 730 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 731 clock-names = "i2c"; 732 clocks = <&cru PCLK_I2C1>; 733 pinctrl-names = "default"; 734 pinctrl-0 = <&i2c1_xfer>; 735 #address-cells = <1>; 736 #size-cells = <0>; 737 status = "disabled"; 738 }; 739 740 i2c2: i2c@2005a000 { 741 compatible = "rockchip,rk3128-i2c", "rockchip,rk3288-i2c"; 742 reg = <0x2005a000 0x1000>; 743 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 744 clock-names = "i2c"; 745 clocks = <&cru PCLK_I2C2>; 746 pinctrl-names = "default"; 747 pinctrl-0 = <&i2c2_xfer>; 748 #address-cells = <1>; 749 #size-cells = <0>; 750 status = "disabled"; 751 }; 752 753 i2c3: i2c@2005e000 { 754 compatible = "rockchip,rk3128-i2c", "rockchip,rk3288-i2c"; 755 reg = <0x2005e000 0x1000>; 756 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 757 clock-names = "i2c"; 758 clocks = <&cru PCLK_I2C3>; 759 pinctrl-names = "default"; 760 pinctrl-0 = <&i2c3_xfer>; 761 #address-cells = <1>; 762 #size-cells = <0>; 763 status = "disabled"; 764 }; 765 766 uart0: serial@20060000 { 767 compatible = "rockchip,rk3128-uart", "snps,dw-apb-uart"; 768 reg = <0x20060000 0x100>; 769 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 770 clock-frequency = <24000000>; 771 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; 772 clock-names = "baudclk", "apb_pclk"; 773 dmas = <&pdma 2>, <&pdma 3>; 774 dma-names = "tx", "rx"; 775 pinctrl-names = "default"; 776 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>; 777 reg-io-width = <4>; 778 reg-shift = <2>; 779 status = "disabled"; 780 }; 781 782 uart1: serial@20064000 { 783 compatible = "rockchip,rk3128-uart", "snps,dw-apb-uart"; 784 reg = <0x20064000 0x100>; 785 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 786 clock-frequency = <24000000>; 787 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; 788 clock-names = "baudclk", "apb_pclk"; 789 dmas = <&pdma 4>, <&pdma 5>; 790 dma-names = "tx", "rx"; 791 pinctrl-names = "default"; 792 pinctrl-0 = <&uart1_xfer>; 793 reg-io-width = <4>; 794 reg-shift = <2>; 795 status = "disabled"; 796 }; 797 798 uart2: serial@20068000 { 799 compatible = "rockchip,rk3128-uart", "snps,dw-apb-uart"; 800 reg = <0x20068000 0x100>; 801 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; 802 clock-frequency = <24000000>; 803 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; 804 clock-names = "baudclk", "apb_pclk"; 805 dmas = <&pdma 6>, <&pdma 7>; 806 dma-names = "tx", "rx"; 807 pinctrl-names = "default"; 808 pinctrl-0 = <&uart2_xfer>; 809 reg-io-width = <4>; 810 reg-shift = <2>; 811 status = "disabled"; 812 }; 813 814 saradc: saradc@2006c000 { 815 compatible = "rockchip,saradc"; 816 reg = <0x2006c000 0x100>; 817 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 818 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>; 819 clock-names = "saradc", "apb_pclk"; 820 resets = <&cru SRST_SARADC>; 821 reset-names = "saradc-apb"; 822 #io-channel-cells = <1>; 823 status = "disabled"; 824 }; 825 826 i2c0: i2c@20072000 { 827 compatible = "rockchip,rk3128-i2c", "rockchip,rk3288-i2c"; 828 reg = <0x20072000 0x1000>; 829 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; 830 clock-names = "i2c"; 831 clocks = <&cru PCLK_I2C0>; 832 pinctrl-names = "default"; 833 pinctrl-0 = <&i2c0_xfer>; 834 #address-cells = <1>; 835 #size-cells = <0>; 836 status = "disabled"; 837 }; 838 839 spi0: spi@20074000 { 840 compatible = "rockchip,rk3128-spi", "rockchip,rk3066-spi"; 841 reg = <0x20074000 0x1000>; 842 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 843 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>; 844 clock-names = "spiclk", "apb_pclk"; 845 dmas = <&pdma 8>, <&pdma 9>; 846 dma-names = "tx", "rx"; 847 pinctrl-names = "default"; 848 pinctrl-0 = <&spi0_tx &spi0_rx &spi0_clk &spi0_cs0 &spi0_cs1>; 849 #address-cells = <1>; 850 #size-cells = <0>; 851 status = "disabled"; 852 }; 853 854 pdma: dma-controller@20078000 { 855 compatible = "arm,pl330", "arm,primecell"; 856 reg = <0x20078000 0x4000>; 857 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 858 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; 859 arm,pl330-broken-no-flushp; 860 arm,pl330-periph-burst; 861 clocks = <&cru ACLK_DMAC>; 862 clock-names = "apb_pclk"; 863 #dma-cells = <1>; 864 }; 865 866 gmac: ethernet@2008c000 { 867 compatible = "rockchip,rk3128-gmac"; 868 reg = <0x2008c000 0x4000>; 869 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 870 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; 871 interrupt-names = "macirq", "eth_wake_irq"; 872 clocks = <&cru SCLK_MAC>, 873 <&cru SCLK_MAC_RX>, <&cru SCLK_MAC_TX>, 874 <&cru SCLK_MAC_REF>, <&cru SCLK_MAC_REFOUT>, 875 <&cru ACLK_GMAC>, <&cru PCLK_GMAC>; 876 clock-names = "stmmaceth", 877 "mac_clk_rx", "mac_clk_tx", 878 "clk_mac_ref", "clk_mac_refout", 879 "aclk_mac", "pclk_mac"; 880 resets = <&cru SRST_GMAC>; 881 reset-names = "stmmaceth"; 882 rockchip,grf = <&grf>; 883 rx-fifo-depth = <4096>; 884 tx-fifo-depth = <2048>; 885 status = "disabled"; 886 887 mdio: mdio { 888 compatible = "snps,dwmac-mdio"; 889 #address-cells = <0x1>; 890 #size-cells = <0x0>; 891 }; 892 }; 893 894 pinctrl: pinctrl { 895 compatible = "rockchip,rk3128-pinctrl"; 896 rockchip,grf = <&grf>; 897 #address-cells = <1>; 898 #size-cells = <1>; 899 ranges; 900 901 gpio0: gpio@2007c000 { 902 compatible = "rockchip,gpio-bank"; 903 reg = <0x2007c000 0x100>; 904 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 905 clocks = <&cru PCLK_GPIO0>; 906 gpio-controller; 907 #gpio-cells = <2>; 908 interrupt-controller; 909 #interrupt-cells = <2>; 910 }; 911 912 gpio1: gpio@20080000 { 913 compatible = "rockchip,gpio-bank"; 914 reg = <0x20080000 0x100>; 915 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 916 clocks = <&cru PCLK_GPIO1>; 917 gpio-controller; 918 #gpio-cells = <2>; 919 interrupt-controller; 920 #interrupt-cells = <2>; 921 }; 922 923 gpio2: gpio@20084000 { 924 compatible = "rockchip,gpio-bank"; 925 reg = <0x20084000 0x100>; 926 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 927 clocks = <&cru PCLK_GPIO2>; 928 gpio-controller; 929 #gpio-cells = <2>; 930 interrupt-controller; 931 #interrupt-cells = <2>; 932 }; 933 934 gpio3: gpio@20088000 { 935 compatible = "rockchip,gpio-bank"; 936 reg = <0x20088000 0x100>; 937 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; 938 clocks = <&cru PCLK_GPIO3>; 939 gpio-controller; 940 #gpio-cells = <2>; 941 interrupt-controller; 942 #interrupt-cells = <2>; 943 }; 944 945 pcfg_pull_default: pcfg-pull-default { 946 bias-pull-pin-default; 947 }; 948 949 pcfg_pull_none: pcfg-pull-none { 950 bias-disable; 951 }; 952 953 emmc { 954 emmc_clk: emmc-clk { 955 rockchip,pins = <2 RK_PA7 2 &pcfg_pull_none>; 956 }; 957 958 emmc_cmd: emmc-cmd { 959 rockchip,pins = <1 RK_PC6 2 &pcfg_pull_default>; 960 }; 961 962 emmc_cmd1: emmc-cmd1 { 963 rockchip,pins = <2 RK_PA4 2 &pcfg_pull_default>; 964 }; 965 966 emmc_pwr: emmc-pwr { 967 rockchip,pins = <2 RK_PA5 2 &pcfg_pull_default>; 968 }; 969 970 emmc_bus1: emmc-bus1 { 971 rockchip,pins = <1 RK_PD0 2 &pcfg_pull_default>; 972 }; 973 974 emmc_bus4: emmc-bus4 { 975 rockchip,pins = <1 RK_PD0 2 &pcfg_pull_default>, 976 <1 RK_PD1 2 &pcfg_pull_default>, 977 <1 RK_PD2 2 &pcfg_pull_default>, 978 <1 RK_PD3 2 &pcfg_pull_default>; 979 }; 980 981 emmc_bus8: emmc-bus8 { 982 rockchip,pins = <1 RK_PD0 2 &pcfg_pull_default>, 983 <1 RK_PD1 2 &pcfg_pull_default>, 984 <1 RK_PD2 2 &pcfg_pull_default>, 985 <1 RK_PD3 2 &pcfg_pull_default>, 986 <1 RK_PD4 2 &pcfg_pull_default>, 987 <1 RK_PD5 2 &pcfg_pull_default>, 988 <1 RK_PD6 2 &pcfg_pull_default>, 989 <1 RK_PD7 2 &pcfg_pull_default>; 990 }; 991 }; 992 993 gmac { 994 rgmii_pins: rgmii-pins { 995 rockchip,pins = <2 RK_PB0 3 &pcfg_pull_default>, 996 <2 RK_PB1 3 &pcfg_pull_default>, 997 <2 RK_PB3 3 &pcfg_pull_default>, 998 <2 RK_PB4 3 &pcfg_pull_default>, 999 <2 RK_PB5 3 &pcfg_pull_default>, 1000 <2 RK_PB6 3 &pcfg_pull_default>, 1001 <2 RK_PC0 3 &pcfg_pull_default>, 1002 <2 RK_PC1 3 &pcfg_pull_default>, 1003 <2 RK_PC2 3 &pcfg_pull_default>, 1004 <2 RK_PC3 3 &pcfg_pull_default>, 1005 <2 RK_PD1 3 &pcfg_pull_default>, 1006 <2 RK_PC4 4 &pcfg_pull_default>, 1007 <2 RK_PC5 4 &pcfg_pull_default>, 1008 <2 RK_PC6 4 &pcfg_pull_default>, 1009 <2 RK_PC7 4 &pcfg_pull_default>; 1010 }; 1011 1012 rmii_pins: rmii-pins { 1013 rockchip,pins = <2 RK_PB0 3 &pcfg_pull_default>, 1014 <2 RK_PB4 3 &pcfg_pull_default>, 1015 <2 RK_PB5 3 &pcfg_pull_default>, 1016 <2 RK_PB6 3 &pcfg_pull_default>, 1017 <2 RK_PB7 3 &pcfg_pull_default>, 1018 <2 RK_PC0 3 &pcfg_pull_default>, 1019 <2 RK_PC1 3 &pcfg_pull_default>, 1020 <2 RK_PC2 3 &pcfg_pull_default>, 1021 <2 RK_PC3 3 &pcfg_pull_default>, 1022 <2 RK_PD1 3 &pcfg_pull_default>; 1023 }; 1024 }; 1025 1026 hdmi { 1027 hdmii2c_xfer: hdmii2c-xfer { 1028 rockchip,pins = <0 RK_PA6 2 &pcfg_pull_none>, 1029 <0 RK_PA7 2 &pcfg_pull_none>; 1030 }; 1031 1032 hdmi_hpd: hdmi-hpd { 1033 rockchip,pins = <0 RK_PB7 1 &pcfg_pull_none>; 1034 }; 1035 1036 hdmi_cec: hdmi-cec { 1037 rockchip,pins = <0 RK_PC4 1 &pcfg_pull_none>; 1038 }; 1039 }; 1040 1041 i2c0 { 1042 i2c0_xfer: i2c0-xfer { 1043 rockchip,pins = <0 RK_PA0 1 &pcfg_pull_none>, 1044 <0 RK_PA1 1 &pcfg_pull_none>; 1045 }; 1046 }; 1047 1048 i2c1 { 1049 i2c1_xfer: i2c1-xfer { 1050 rockchip,pins = <0 RK_PA2 1 &pcfg_pull_none>, 1051 <0 RK_PA3 1 &pcfg_pull_none>; 1052 }; 1053 }; 1054 1055 i2c2 { 1056 i2c2_xfer: i2c2-xfer { 1057 rockchip,pins = <2 RK_PC4 3 &pcfg_pull_none>, 1058 <2 RK_PC5 3 &pcfg_pull_none>; 1059 }; 1060 }; 1061 1062 i2c3 { 1063 i2c3_xfer: i2c3-xfer { 1064 rockchip,pins = <0 RK_PA6 1 &pcfg_pull_none>, 1065 <0 RK_PA7 1 &pcfg_pull_none>; 1066 }; 1067 }; 1068 1069 i2s { 1070 i2s_bus: i2s-bus { 1071 rockchip,pins = <0 RK_PB0 1 &pcfg_pull_none>, 1072 <0 RK_PB1 1 &pcfg_pull_none>, 1073 <0 RK_PB3 1 &pcfg_pull_none>, 1074 <0 RK_PB4 1 &pcfg_pull_none>, 1075 <0 RK_PB5 1 &pcfg_pull_none>, 1076 <0 RK_PB6 1 &pcfg_pull_none>; 1077 }; 1078 1079 i2s1_bus: i2s1-bus { 1080 rockchip,pins = <1 RK_PA0 1 &pcfg_pull_none>, 1081 <1 RK_PA1 1 &pcfg_pull_none>, 1082 <1 RK_PA2 1 &pcfg_pull_none>, 1083 <1 RK_PA3 1 &pcfg_pull_none>, 1084 <1 RK_PA4 1 &pcfg_pull_none>, 1085 <1 RK_PA5 1 &pcfg_pull_none>; 1086 }; 1087 }; 1088 1089 lcdc { 1090 lcdc_dclk: lcdc-dclk { 1091 rockchip,pins = <2 RK_PB0 1 &pcfg_pull_none>; 1092 }; 1093 1094 lcdc_den: lcdc-den { 1095 rockchip,pins = <2 RK_PB3 1 &pcfg_pull_none>; 1096 }; 1097 1098 lcdc_hsync: lcdc-hsync { 1099 rockchip,pins = <2 RK_PB1 1 &pcfg_pull_none>; 1100 }; 1101 1102 lcdc_vsync: lcdc-vsync { 1103 rockchip,pins = <2 RK_PB2 1 &pcfg_pull_none>; 1104 }; 1105 1106 lcdc_rgb24: lcdc-rgb24 { 1107 rockchip,pins = <2 RK_PB4 1 &pcfg_pull_none>, 1108 <2 RK_PB5 1 &pcfg_pull_none>, 1109 <2 RK_PB6 1 &pcfg_pull_none>, 1110 <2 RK_PB7 1 &pcfg_pull_none>, 1111 <2 RK_PC0 1 &pcfg_pull_none>, 1112 <2 RK_PC1 1 &pcfg_pull_none>, 1113 <2 RK_PC2 1 &pcfg_pull_none>, 1114 <2 RK_PC3 1 &pcfg_pull_none>, 1115 <2 RK_PC4 1 &pcfg_pull_none>, 1116 <2 RK_PC5 1 &pcfg_pull_none>, 1117 <2 RK_PC6 1 &pcfg_pull_none>, 1118 <2 RK_PC7 1 &pcfg_pull_none>, 1119 <2 RK_PD0 1 &pcfg_pull_none>, 1120 <2 RK_PD1 1 &pcfg_pull_none>; 1121 }; 1122 }; 1123 1124 nfc { 1125 flash_ale: flash-ale { 1126 rockchip,pins = <2 RK_PA0 1 &pcfg_pull_none>; 1127 }; 1128 1129 flash_cle: flash-cle { 1130 rockchip,pins = <2 RK_PA1 1 &pcfg_pull_none>; 1131 }; 1132 1133 flash_wrn: flash-wrn { 1134 rockchip,pins = <2 RK_PA2 1 &pcfg_pull_none>; 1135 }; 1136 1137 flash_rdn: flash-rdn { 1138 rockchip,pins = <2 RK_PA3 1 &pcfg_pull_none>; 1139 }; 1140 1141 flash_rdy: flash-rdy { 1142 rockchip,pins = <2 RK_PA4 1 &pcfg_pull_none>; 1143 }; 1144 1145 flash_cs0: flash-cs0 { 1146 rockchip,pins = <2 RK_PA6 1 &pcfg_pull_none>; 1147 }; 1148 1149 flash_dqs: flash-dqs { 1150 rockchip,pins = <2 RK_PA7 1 &pcfg_pull_none>; 1151 }; 1152 1153 flash_bus8: flash-bus8 { 1154 rockchip,pins = <1 RK_PD0 1 &pcfg_pull_none>, 1155 <1 RK_PD1 1 &pcfg_pull_none>, 1156 <1 RK_PD2 1 &pcfg_pull_none>, 1157 <1 RK_PD3 1 &pcfg_pull_none>, 1158 <1 RK_PD4 1 &pcfg_pull_none>, 1159 <1 RK_PD5 1 &pcfg_pull_none>, 1160 <1 RK_PD6 1 &pcfg_pull_none>, 1161 <1 RK_PD7 1 &pcfg_pull_none>; 1162 }; 1163 }; 1164 1165 pwm0 { 1166 pwm0_pin: pwm0-pin { 1167 rockchip,pins = <0 RK_PD2 1 &pcfg_pull_none>; 1168 }; 1169 }; 1170 1171 pwm1 { 1172 pwm1_pin: pwm1-pin { 1173 rockchip,pins = <0 RK_PD3 1 &pcfg_pull_none>; 1174 }; 1175 }; 1176 1177 pwm2 { 1178 pwm2_pin: pwm2-pin { 1179 rockchip,pins = <0 RK_PD4 1 &pcfg_pull_none>; 1180 }; 1181 }; 1182 1183 pwm3 { 1184 pwm3_pin: pwm3-pin { 1185 rockchip,pins = <3 RK_PD2 1 &pcfg_pull_none>; 1186 }; 1187 }; 1188 1189 sdio { 1190 sdio_clk: sdio-clk { 1191 rockchip,pins = <1 RK_PA0 2 &pcfg_pull_none>; 1192 }; 1193 1194 sdio_cmd: sdio-cmd { 1195 rockchip,pins = <0 RK_PA3 2 &pcfg_pull_default>; 1196 }; 1197 1198 sdio_pwren: sdio-pwren { 1199 rockchip,pins = <0 RK_PD6 1 &pcfg_pull_default>; 1200 }; 1201 1202 sdio_bus4: sdio-bus4 { 1203 rockchip,pins = <1 RK_PA1 2 &pcfg_pull_default>, 1204 <1 RK_PA2 2 &pcfg_pull_default>, 1205 <1 RK_PA4 2 &pcfg_pull_default>, 1206 <1 RK_PA5 2 &pcfg_pull_default>; 1207 }; 1208 }; 1209 1210 sdmmc { 1211 sdmmc_clk: sdmmc-clk { 1212 rockchip,pins = <1 RK_PC0 1 &pcfg_pull_none>; 1213 }; 1214 1215 sdmmc_cmd: sdmmc-cmd { 1216 rockchip,pins = <1 RK_PB7 1 &pcfg_pull_default>; 1217 }; 1218 1219 sdmmc_det: sdmmc-det { 1220 rockchip,pins = <1 RK_PC1 1 &pcfg_pull_default>; 1221 }; 1222 1223 sdmmc_wp: sdmmc-wp { 1224 rockchip,pins = <1 RK_PA7 1 &pcfg_pull_default>; 1225 }; 1226 1227 sdmmc_pwren: sdmmc-pwren { 1228 rockchip,pins = <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_default>; 1229 }; 1230 1231 sdmmc_bus4: sdmmc-bus4 { 1232 rockchip,pins = <1 RK_PC2 1 &pcfg_pull_default>, 1233 <1 RK_PC3 1 &pcfg_pull_default>, 1234 <1 RK_PC4 1 &pcfg_pull_default>, 1235 <1 RK_PC5 1 &pcfg_pull_default>; 1236 }; 1237 }; 1238 1239 sfc { 1240 sfc_bus2: sfc-bus2 { 1241 rockchip,pins = <1 RK_PD0 3 &pcfg_pull_default>, 1242 <1 RK_PD1 3 &pcfg_pull_default>; 1243 }; 1244 1245 sfc_bus4: sfc-bus4 { 1246 rockchip,pins = <1 RK_PD0 3 &pcfg_pull_default>, 1247 <1 RK_PD1 3 &pcfg_pull_default>, 1248 <1 RK_PD2 3 &pcfg_pull_default>, 1249 <1 RK_PD3 3 &pcfg_pull_default>; 1250 }; 1251 1252 sfc_clk: sfc-clk { 1253 rockchip,pins = <2 RK_PA4 3 &pcfg_pull_none>; 1254 }; 1255 1256 sfc_cs0: sfc-cs0 { 1257 rockchip,pins = <2 RK_PA2 2 &pcfg_pull_default>; 1258 }; 1259 1260 sfc_cs1: sfc-cs1 { 1261 rockchip,pins = <2 RK_PA3 2 &pcfg_pull_default>; 1262 }; 1263 }; 1264 1265 spdif { 1266 spdif_tx: spdif-tx { 1267 rockchip,pins = <3 RK_PD3 1 &pcfg_pull_none>; 1268 }; 1269 }; 1270 1271 spi0 { 1272 spi0_clk: spi0-clk { 1273 rockchip,pins = <1 RK_PB0 1 &pcfg_pull_default>; 1274 }; 1275 1276 spi0_cs0: spi0-cs0 { 1277 rockchip,pins = <1 RK_PB3 1 &pcfg_pull_default>; 1278 }; 1279 1280 spi0_tx: spi0-tx { 1281 rockchip,pins = <1 RK_PB1 1 &pcfg_pull_default>; 1282 }; 1283 1284 spi0_rx: spi0-rx { 1285 rockchip,pins = <1 RK_PB2 1 &pcfg_pull_default>; 1286 }; 1287 1288 spi0_cs1: spi0-cs1 { 1289 rockchip,pins = <1 RK_PB4 1 &pcfg_pull_default>; 1290 }; 1291 1292 spi1_clk: spi1-clk { 1293 rockchip,pins = <2 RK_PA0 2 &pcfg_pull_default>; 1294 }; 1295 1296 spi1_cs0: spi1-cs0 { 1297 rockchip,pins = <1 RK_PD6 3 &pcfg_pull_default>; 1298 }; 1299 1300 spi1_tx: spi1-tx { 1301 rockchip,pins = <1 RK_PD5 3 &pcfg_pull_default>; 1302 }; 1303 1304 spi1_rx: spi1-rx { 1305 rockchip,pins = <1 RK_PD4 3 &pcfg_pull_default>; 1306 }; 1307 1308 spi1_cs1: spi1-cs1 { 1309 rockchip,pins = <1 RK_PD7 3 &pcfg_pull_default>; 1310 }; 1311 1312 spi2_clk: spi2-clk { 1313 rockchip,pins = <0 RK_PB1 2 &pcfg_pull_default>; 1314 }; 1315 1316 spi2_cs0: spi2-cs0 { 1317 rockchip,pins = <0 RK_PB6 2 &pcfg_pull_default>; 1318 }; 1319 1320 spi2_tx: spi2-tx { 1321 rockchip,pins = <0 RK_PB3 2 &pcfg_pull_default>; 1322 }; 1323 1324 spi2_rx: spi2-rx { 1325 rockchip,pins = <0 RK_PB5 2 &pcfg_pull_default>; 1326 }; 1327 }; 1328 1329 uart0 { 1330 uart0_xfer: uart0-xfer { 1331 rockchip,pins = <2 RK_PD2 2 &pcfg_pull_default>, 1332 <2 RK_PD3 2 &pcfg_pull_none>; 1333 }; 1334 1335 uart0_cts: uart0-cts { 1336 rockchip,pins = <2 RK_PD5 2 &pcfg_pull_none>; 1337 }; 1338 1339 uart0_rts: uart0-rts { 1340 rockchip,pins = <0 RK_PC1 2 &pcfg_pull_none>; 1341 }; 1342 }; 1343 1344 uart1 { 1345 uart1_xfer: uart1-xfer { 1346 rockchip,pins = <1 RK_PB1 2 &pcfg_pull_default>, 1347 <1 RK_PB2 2 &pcfg_pull_default>; 1348 }; 1349 1350 uart1_cts: uart1-cts { 1351 rockchip,pins = <1 RK_PB0 2 &pcfg_pull_none>; 1352 }; 1353 1354 uart1_rts: uart1-rts { 1355 rockchip,pins = <1 RK_PB3 2 &pcfg_pull_none>; 1356 }; 1357 }; 1358 1359 uart2 { 1360 uart2_xfer: uart2-xfer { 1361 rockchip,pins = <1 RK_PC2 2 &pcfg_pull_default>, 1362 <1 RK_PC3 2 &pcfg_pull_none>; 1363 }; 1364 1365 uart2_cts: uart2-cts { 1366 rockchip,pins = <0 RK_PD1 1 &pcfg_pull_none>; 1367 }; 1368 1369 uart2_rts: uart2-rts { 1370 rockchip,pins = <0 RK_PD0 1 &pcfg_pull_none>; 1371 }; 1372 }; 1373 }; 1374};
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