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r8a7792.dtsi
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linux-6.19.14/arch/arm/boot/dts/renesas/r8a7792.dtsi
1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Device Tree Source for the R-Car V2H (R8A77920) SoC 4 * 5 * Copyright (C) 2016 Cogent Embedded Inc. 6 */ 7 8#include <dt-bindings/clock/r8a7792-cpg-mssr.h> 9#include <dt-bindings/interrupt-controller/irq.h> 10#include <dt-bindings/interrupt-controller/arm-gic.h> 11#include <dt-bindings/power/r8a7792-sysc.h> 12 13/ { 14 compatible = "renesas,r8a7792"; 15 #address-cells = <2>; 16 #size-cells = <2>; 17 interrupt-parent = <&gic>; 18 19 aliases { 20 i2c0 = &i2c0; 21 i2c1 = &i2c1; 22 i2c2 = &i2c2; 23 i2c3 = &i2c3; 24 i2c4 = &i2c4; 25 i2c5 = &i2c5; 26 i2c6 = &iic3; 27 spi0 = &qspi; 28 spi1 = &msiof0; 29 spi2 = &msiof1; 30 vin0 = &vin0; 31 vin1 = &vin1; 32 vin2 = &vin2; 33 vin3 = &vin3; 34 vin4 = &vin4; 35 vin5 = &vin5; 36 }; 37 38 /* External CAN clock */ 39 can_clk: can { 40 compatible = "fixed-clock"; 41 #clock-cells = <0>; 42 /* This value must be overridden by the board. */ 43 clock-frequency = <0>; 44 }; 45 46 cpus { 47 #address-cells = <1>; 48 #size-cells = <0>; 49 50 cpu0: cpu@0 { 51 device_type = "cpu"; 52 compatible = "arm,cortex-a15"; 53 reg = <0>; 54 clock-frequency = <1000000000>; 55 clocks = <&cpg CPG_CORE R8A7792_CLK_Z>; 56 power-domains = <&sysc R8A7792_PD_CA15_CPU0>; 57 enable-method = "renesas,apmu"; 58 next-level-cache = <&L2_CA15>; 59 }; 60 61 cpu1: cpu@1 { 62 device_type = "cpu"; 63 compatible = "arm,cortex-a15"; 64 reg = <1>; 65 clock-frequency = <1000000000>; 66 clocks = <&cpg CPG_CORE R8A7792_CLK_Z>; 67 power-domains = <&sysc R8A7792_PD_CA15_CPU1>; 68 enable-method = "renesas,apmu"; 69 next-level-cache = <&L2_CA15>; 70 }; 71 72 L2_CA15: cache-controller-0 { 73 compatible = "cache"; 74 cache-unified; 75 cache-level = <2>; 76 power-domains = <&sysc R8A7792_PD_CA15_SCU>; 77 }; 78 }; 79 80 /* External root clock */ 81 extal_clk: extal { 82 compatible = "fixed-clock"; 83 #clock-cells = <0>; 84 /* This value must be overridden by the board. */ 85 clock-frequency = <0>; 86 bootph-all; 87 }; 88 89 lbsc: bus { 90 compatible = "simple-bus"; 91 #address-cells = <1>; 92 #size-cells = <1>; 93 ranges = <0 0 0 0x1c000000>; 94 }; 95 96 pmu { 97 compatible = "arm,cortex-a15-pmu"; 98 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, 99 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 100 interrupt-affinity = <&cpu0>, <&cpu1>; 101 }; 102 103 /* External SCIF clock */ 104 scif_clk: scif { 105 compatible = "fixed-clock"; 106 #clock-cells = <0>; 107 /* This value must be overridden by the board. */ 108 clock-frequency = <0>; 109 }; 110 111 soc { 112 compatible = "simple-bus"; 113 bootph-all; 114 115 #address-cells = <2>; 116 #size-cells = <2>; 117 ranges; 118 119 rwdt: watchdog@e6020000 { 120 compatible = "renesas,r8a7792-wdt", 121 "renesas,rcar-gen2-wdt"; 122 reg = <0 0xe6020000 0 0x0c>; 123 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; 124 clocks = <&cpg CPG_MOD 402>; 125 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 126 resets = <&cpg 402>; 127 status = "disabled"; 128 }; 129 130 gpio0: gpio@e6050000 { 131 compatible = "renesas,gpio-r8a7792", 132 "renesas,rcar-gen2-gpio"; 133 reg = <0 0xe6050000 0 0x50>; 134 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 135 #gpio-cells = <2>; 136 gpio-controller; 137 gpio-ranges = <&pfc 0 0 29>; 138 #interrupt-cells = <2>; 139 interrupt-controller; 140 clocks = <&cpg CPG_MOD 912>; 141 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 142 resets = <&cpg 912>; 143 }; 144 145 gpio1: gpio@e6051000 { 146 compatible = "renesas,gpio-r8a7792", 147 "renesas,rcar-gen2-gpio"; 148 reg = <0 0xe6051000 0 0x50>; 149 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 150 #gpio-cells = <2>; 151 gpio-controller; 152 gpio-ranges = <&pfc 0 32 23>; 153 #interrupt-cells = <2>; 154 interrupt-controller; 155 clocks = <&cpg CPG_MOD 911>; 156 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 157 resets = <&cpg 911>; 158 }; 159 160 gpio2: gpio@e6052000 { 161 compatible = "renesas,gpio-r8a7792", 162 "renesas,rcar-gen2-gpio"; 163 reg = <0 0xe6052000 0 0x50>; 164 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 165 #gpio-cells = <2>; 166 gpio-controller; 167 gpio-ranges = <&pfc 0 64 32>; 168 #interrupt-cells = <2>; 169 interrupt-controller; 170 clocks = <&cpg CPG_MOD 910>; 171 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 172 resets = <&cpg 910>; 173 }; 174 175 gpio3: gpio@e6053000 { 176 compatible = "renesas,gpio-r8a7792", 177 "renesas,rcar-gen2-gpio"; 178 reg = <0 0xe6053000 0 0x50>; 179 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 180 #gpio-cells = <2>; 181 gpio-controller; 182 gpio-ranges = <&pfc 0 96 28>; 183 #interrupt-cells = <2>; 184 interrupt-controller; 185 clocks = <&cpg CPG_MOD 909>; 186 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 187 resets = <&cpg 909>; 188 }; 189 190 gpio4: gpio@e6054000 { 191 compatible = "renesas,gpio-r8a7792", 192 "renesas,rcar-gen2-gpio"; 193 reg = <0 0xe6054000 0 0x50>; 194 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 195 #gpio-cells = <2>; 196 gpio-controller; 197 gpio-ranges = <&pfc 0 128 17>; 198 #interrupt-cells = <2>; 199 interrupt-controller; 200 clocks = <&cpg CPG_MOD 908>; 201 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 202 resets = <&cpg 908>; 203 }; 204 205 gpio5: gpio@e6055000 { 206 compatible = "renesas,gpio-r8a7792", 207 "renesas,rcar-gen2-gpio"; 208 reg = <0 0xe6055000 0 0x50>; 209 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 210 #gpio-cells = <2>; 211 gpio-controller; 212 gpio-ranges = <&pfc 0 160 17>; 213 #interrupt-cells = <2>; 214 interrupt-controller; 215 clocks = <&cpg CPG_MOD 907>; 216 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 217 resets = <&cpg 907>; 218 }; 219 220 gpio6: gpio@e6055100 { 221 compatible = "renesas,gpio-r8a7792", 222 "renesas,rcar-gen2-gpio"; 223 reg = <0 0xe6055100 0 0x50>; 224 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 225 #gpio-cells = <2>; 226 gpio-controller; 227 gpio-ranges = <&pfc 0 192 17>; 228 #interrupt-cells = <2>; 229 interrupt-controller; 230 clocks = <&cpg CPG_MOD 905>; 231 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 232 resets = <&cpg 905>; 233 }; 234 235 gpio7: gpio@e6055200 { 236 compatible = "renesas,gpio-r8a7792", 237 "renesas,rcar-gen2-gpio"; 238 reg = <0 0xe6055200 0 0x50>; 239 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 240 #gpio-cells = <2>; 241 gpio-controller; 242 gpio-ranges = <&pfc 0 224 17>; 243 #interrupt-cells = <2>; 244 interrupt-controller; 245 clocks = <&cpg CPG_MOD 904>; 246 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 247 resets = <&cpg 904>; 248 }; 249 250 gpio8: gpio@e6055300 { 251 compatible = "renesas,gpio-r8a7792", 252 "renesas,rcar-gen2-gpio"; 253 reg = <0 0xe6055300 0 0x50>; 254 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 255 #gpio-cells = <2>; 256 gpio-controller; 257 gpio-ranges = <&pfc 0 256 17>; 258 #interrupt-cells = <2>; 259 interrupt-controller; 260 clocks = <&cpg CPG_MOD 921>; 261 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 262 resets = <&cpg 921>; 263 }; 264 265 gpio9: gpio@e6055400 { 266 compatible = "renesas,gpio-r8a7792", 267 "renesas,rcar-gen2-gpio"; 268 reg = <0 0xe6055400 0 0x50>; 269 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 270 #gpio-cells = <2>; 271 gpio-controller; 272 gpio-ranges = <&pfc 0 288 17>; 273 #interrupt-cells = <2>; 274 interrupt-controller; 275 clocks = <&cpg CPG_MOD 919>; 276 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 277 resets = <&cpg 919>; 278 }; 279 280 gpio10: gpio@e6055500 { 281 compatible = "renesas,gpio-r8a7792", 282 "renesas,rcar-gen2-gpio"; 283 reg = <0 0xe6055500 0 0x50>; 284 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 285 #gpio-cells = <2>; 286 gpio-controller; 287 gpio-ranges = <&pfc 0 320 32>; 288 #interrupt-cells = <2>; 289 interrupt-controller; 290 clocks = <&cpg CPG_MOD 914>; 291 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 292 resets = <&cpg 914>; 293 }; 294 295 gpio11: gpio@e6055600 { 296 compatible = "renesas,gpio-r8a7792", 297 "renesas,rcar-gen2-gpio"; 298 reg = <0 0xe6055600 0 0x50>; 299 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 300 #gpio-cells = <2>; 301 gpio-controller; 302 gpio-ranges = <&pfc 0 352 30>; 303 #interrupt-cells = <2>; 304 interrupt-controller; 305 clocks = <&cpg CPG_MOD 913>; 306 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 307 resets = <&cpg 913>; 308 }; 309 310 pfc: pinctrl@e6060000 { 311 compatible = "renesas,pfc-r8a7792"; 312 reg = <0 0xe6060000 0 0x144>; 313 bootph-all; 314 }; 315 316 cpg: clock-controller@e6150000 { 317 compatible = "renesas,r8a7792-cpg-mssr"; 318 reg = <0 0xe6150000 0 0x1000>; 319 clocks = <&extal_clk>; 320 clock-names = "extal"; 321 #clock-cells = <2>; 322 #power-domain-cells = <0>; 323 #reset-cells = <1>; 324 bootph-all; 325 }; 326 327 apmu@e6152000 { 328 compatible = "renesas,r8a7792-apmu", "renesas,apmu"; 329 reg = <0 0xe6152000 0 0x188>; 330 cpus = <&cpu0>, <&cpu1>; 331 }; 332 333 rst: reset-controller@e6160000 { 334 compatible = "renesas,r8a7792-rst"; 335 reg = <0 0xe6160000 0 0x0100>; 336 bootph-all; 337 }; 338 339 sysc: system-controller@e6180000 { 340 compatible = "renesas,r8a7792-sysc"; 341 reg = <0 0xe6180000 0 0x0200>; 342 #power-domain-cells = <1>; 343 }; 344 345 irqc: interrupt-controller@e61c0000 { 346 compatible = "renesas,irqc-r8a7792", "renesas,irqc"; 347 #interrupt-cells = <2>; 348 interrupt-controller; 349 reg = <0 0xe61c0000 0 0x200>; 350 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 351 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 352 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 353 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 354 clocks = <&cpg CPG_MOD 407>; 355 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 356 resets = <&cpg 407>; 357 }; 358 359 tmu0: timer@e61e0000 { 360 compatible = "renesas,tmu-r8a7792", "renesas,tmu"; 361 reg = <0 0xe61e0000 0 0x30>; 362 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 363 <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, 364 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 365 interrupt-names = "tuni0", "tuni1", "tuni2"; 366 clocks = <&cpg CPG_MOD 125>; 367 clock-names = "fck"; 368 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 369 resets = <&cpg 125>; 370 status = "disabled"; 371 }; 372 373 tmu1: timer@fff60000 { 374 compatible = "renesas,tmu-r8a7792", "renesas,tmu"; 375 reg = <0 0xfff60000 0 0x30>; 376 interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, 377 <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>, 378 <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, 379 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>; 380 interrupt-names = "tuni0", "tuni1", "tuni2", "ticpi2"; 381 clocks = <&cpg CPG_MOD 111>; 382 clock-names = "fck"; 383 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 384 resets = <&cpg 111>; 385 status = "disabled"; 386 }; 387 388 tmu2: timer@fff70000 { 389 compatible = "renesas,tmu-r8a7792", "renesas,tmu"; 390 reg = <0 0xfff70000 0 0x30>; 391 interrupts = <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>, 392 <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 393 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>, 394 <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>; 395 interrupt-names = "tuni0", "tuni1", "tuni2", "ticpi2"; 396 clocks = <&cpg CPG_MOD 122>; 397 clock-names = "fck"; 398 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 399 resets = <&cpg 122>; 400 status = "disabled"; 401 }; 402 403 tmu3: timer@fff80000 { 404 compatible = "renesas,tmu-r8a7792", "renesas,tmu"; 405 reg = <0 0xfff80000 0 0x30>; 406 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 407 <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, 408 <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, 409 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 410 interrupt-names = "tuni0", "tuni1", "tuni2", "ticpi2"; 411 clocks = <&cpg CPG_MOD 121>; 412 clock-names = "fck"; 413 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 414 resets = <&cpg 121>; 415 status = "disabled"; 416 }; 417 418 icram0: sram@e63a0000 { 419 compatible = "mmio-sram"; 420 reg = <0 0xe63a0000 0 0x12000>; 421 #address-cells = <1>; 422 #size-cells = <1>; 423 ranges = <0 0 0xe63a0000 0x12000>; 424 }; 425 426 icram1: sram@e63c0000 { 427 compatible = "mmio-sram"; 428 reg = <0 0xe63c0000 0 0x1000>; 429 #address-cells = <1>; 430 #size-cells = <1>; 431 ranges = <0 0 0xe63c0000 0x1000>; 432 433 smp-sram@0 { 434 compatible = "renesas,smp-sram"; 435 reg = <0 0x100>; 436 }; 437 }; 438 439 /* I2C doesn't need pinmux */ 440 i2c0: i2c@e6508000 { 441 compatible = "renesas,i2c-r8a7792", 442 "renesas,rcar-gen2-i2c"; 443 reg = <0 0xe6508000 0 0x40>; 444 interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>; 445 clocks = <&cpg CPG_MOD 931>; 446 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 447 resets = <&cpg 931>; 448 i2c-scl-internal-delay-ns = <6>; 449 #address-cells = <1>; 450 #size-cells = <0>; 451 status = "disabled"; 452 }; 453 454 i2c1: i2c@e6518000 { 455 compatible = "renesas,i2c-r8a7792", 456 "renesas,rcar-gen2-i2c"; 457 reg = <0 0xe6518000 0 0x40>; 458 interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>; 459 clocks = <&cpg CPG_MOD 930>; 460 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 461 resets = <&cpg 930>; 462 i2c-scl-internal-delay-ns = <6>; 463 #address-cells = <1>; 464 #size-cells = <0>; 465 status = "disabled"; 466 }; 467 468 i2c2: i2c@e6530000 { 469 compatible = "renesas,i2c-r8a7792", 470 "renesas,rcar-gen2-i2c"; 471 reg = <0 0xe6530000 0 0x40>; 472 interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>; 473 clocks = <&cpg CPG_MOD 929>; 474 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 475 resets = <&cpg 929>; 476 i2c-scl-internal-delay-ns = <6>; 477 #address-cells = <1>; 478 #size-cells = <0>; 479 status = "disabled"; 480 }; 481 482 i2c3: i2c@e6540000 { 483 compatible = "renesas,i2c-r8a7792", 484 "renesas,rcar-gen2-i2c"; 485 reg = <0 0xe6540000 0 0x40>; 486 interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>; 487 clocks = <&cpg CPG_MOD 928>; 488 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 489 resets = <&cpg 928>; 490 i2c-scl-internal-delay-ns = <6>; 491 #address-cells = <1>; 492 #size-cells = <0>; 493 status = "disabled"; 494 }; 495 496 i2c4: i2c@e6520000 { 497 compatible = "renesas,i2c-r8a7792", 498 "renesas,rcar-gen2-i2c"; 499 reg = <0 0xe6520000 0 0x40>; 500 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 501 clocks = <&cpg CPG_MOD 927>; 502 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 503 resets = <&cpg 927>; 504 i2c-scl-internal-delay-ns = <6>; 505 #address-cells = <1>; 506 #size-cells = <0>; 507 status = "disabled"; 508 }; 509 510 i2c5: i2c@e6528000 { 511 compatible = "renesas,i2c-r8a7792", 512 "renesas,rcar-gen2-i2c"; 513 reg = <0 0xe6528000 0 0x40>; 514 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 515 clocks = <&cpg CPG_MOD 925>; 516 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 517 resets = <&cpg 925>; 518 i2c-scl-internal-delay-ns = <110>; 519 #address-cells = <1>; 520 #size-cells = <0>; 521 status = "disabled"; 522 }; 523 524 iic3: i2c@e60b0000 { 525 #address-cells = <1>; 526 #size-cells = <0>; 527 compatible = "renesas,iic-r8a7792", 528 "renesas,rcar-gen2-iic", 529 "renesas,rmobile-iic"; 530 reg = <0 0xe60b0000 0 0x425>; 531 interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>; 532 clocks = <&cpg CPG_MOD 926>; 533 dmas = <&dmac0 0x77>, <&dmac0 0x78>, 534 <&dmac1 0x77>, <&dmac1 0x78>; 535 dma-names = "tx", "rx", "tx", "rx"; 536 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 537 resets = <&cpg 926>; 538 status = "disabled"; 539 }; 540 541 dmac0: dma-controller@e6700000 { 542 compatible = "renesas,dmac-r8a7792", 543 "renesas,rcar-dmac"; 544 reg = <0 0xe6700000 0 0x20000>; 545 interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>, 546 <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>, 547 <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>, 548 <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>, 549 <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>, 550 <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>, 551 <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>, 552 <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>, 553 <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>, 554 <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>, 555 <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>, 556 <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>, 557 <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>, 558 <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>, 559 <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>, 560 <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>; 561 interrupt-names = "error", 562 "ch0", "ch1", "ch2", "ch3", 563 "ch4", "ch5", "ch6", "ch7", 564 "ch8", "ch9", "ch10", "ch11", 565 "ch12", "ch13", "ch14"; 566 clocks = <&cpg CPG_MOD 219>; 567 clock-names = "fck"; 568 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 569 resets = <&cpg 219>; 570 #dma-cells = <1>; 571 dma-channels = <15>; 572 }; 573 574 dmac1: dma-controller@e6720000 { 575 compatible = "renesas,dmac-r8a7792", 576 "renesas,rcar-dmac"; 577 reg = <0 0xe6720000 0 0x20000>; 578 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>, 579 <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>, 580 <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>, 581 <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>, 582 <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>, 583 <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>, 584 <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>, 585 <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>, 586 <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>, 587 <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>, 588 <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>, 589 <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>, 590 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 591 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 592 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 593 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>; 594 interrupt-names = "error", 595 "ch0", "ch1", "ch2", "ch3", 596 "ch4", "ch5", "ch6", "ch7", 597 "ch8", "ch9", "ch10", "ch11", 598 "ch12", "ch13", "ch14"; 599 clocks = <&cpg CPG_MOD 218>; 600 clock-names = "fck"; 601 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 602 resets = <&cpg 218>; 603 #dma-cells = <1>; 604 dma-channels = <15>; 605 }; 606 607 avb: ethernet@e6800000 { 608 compatible = "renesas,etheravb-r8a7792", 609 "renesas,etheravb-rcar-gen2"; 610 reg = <0 0xe6800000 0 0x800>, <0 0xee0e8000 0 0x4000>; 611 interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>; 612 clocks = <&cpg CPG_MOD 812>; 613 clock-names = "fck"; 614 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 615 resets = <&cpg 812>; 616 #address-cells = <1>; 617 #size-cells = <0>; 618 status = "disabled"; 619 }; 620 621 qspi: spi@e6b10000 { 622 compatible = "renesas,qspi-r8a7792", "renesas,qspi"; 623 reg = <0 0xe6b10000 0 0x2c>; 624 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; 625 clocks = <&cpg CPG_MOD 917>; 626 dmas = <&dmac0 0x17>, <&dmac0 0x18>, 627 <&dmac1 0x17>, <&dmac1 0x18>; 628 dma-names = "tx", "rx", "tx", "rx"; 629 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 630 resets = <&cpg 917>; 631 num-cs = <1>; 632 #address-cells = <1>; 633 #size-cells = <0>; 634 status = "disabled"; 635 }; 636 637 scif0: serial@e6e60000 { 638 compatible = "renesas,scif-r8a7792", 639 "renesas,rcar-gen2-scif", "renesas,scif"; 640 reg = <0 0xe6e60000 0 64>; 641 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; 642 clocks = <&cpg CPG_MOD 721>, 643 <&cpg CPG_CORE R8A7792_CLK_ZS>, <&scif_clk>; 644 clock-names = "fck", "brg_int", "scif_clk"; 645 dmas = <&dmac0 0x29>, <&dmac0 0x2a>, 646 <&dmac1 0x29>, <&dmac1 0x2a>; 647 dma-names = "tx", "rx", "tx", "rx"; 648 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 649 resets = <&cpg 721>; 650 status = "disabled"; 651 }; 652 653 scif1: serial@e6e68000 { 654 compatible = "renesas,scif-r8a7792", 655 "renesas,rcar-gen2-scif", "renesas,scif"; 656 reg = <0 0xe6e68000 0 64>; 657 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; 658 clocks = <&cpg CPG_MOD 720>, 659 <&cpg CPG_CORE R8A7792_CLK_ZS>, <&scif_clk>; 660 clock-names = "fck", "brg_int", "scif_clk"; 661 dmas = <&dmac0 0x2d>, <&dmac0 0x2e>, 662 <&dmac1 0x2d>, <&dmac1 0x2e>; 663 dma-names = "tx", "rx", "tx", "rx"; 664 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 665 resets = <&cpg 720>; 666 status = "disabled"; 667 }; 668 669 scif2: serial@e6e58000 { 670 compatible = "renesas,scif-r8a7792", 671 "renesas,rcar-gen2-scif", "renesas,scif"; 672 reg = <0 0xe6e58000 0 64>; 673 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; 674 clocks = <&cpg CPG_MOD 719>, 675 <&cpg CPG_CORE R8A7792_CLK_ZS>, <&scif_clk>; 676 clock-names = "fck", "brg_int", "scif_clk"; 677 dmas = <&dmac0 0x2b>, <&dmac0 0x2c>, 678 <&dmac1 0x2b>, <&dmac1 0x2c>; 679 dma-names = "tx", "rx", "tx", "rx"; 680 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 681 resets = <&cpg 719>; 682 status = "disabled"; 683 }; 684 685 scif3: serial@e6ea8000 { 686 compatible = "renesas,scif-r8a7792", 687 "renesas,rcar-gen2-scif", "renesas,scif"; 688 reg = <0 0xe6ea8000 0 64>; 689 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 690 clocks = <&cpg CPG_MOD 718>, 691 <&cpg CPG_CORE R8A7792_CLK_ZS>, <&scif_clk>; 692 clock-names = "fck", "brg_int", "scif_clk"; 693 dmas = <&dmac0 0x2f>, <&dmac0 0x30>, 694 <&dmac1 0x2f>, <&dmac1 0x30>; 695 dma-names = "tx", "rx", "tx", "rx"; 696 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 697 resets = <&cpg 718>; 698 status = "disabled"; 699 }; 700 701 hscif0: serial@e62c0000 { 702 compatible = "renesas,hscif-r8a7792", 703 "renesas,rcar-gen2-hscif", "renesas,hscif"; 704 reg = <0 0xe62c0000 0 96>; 705 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; 706 clocks = <&cpg CPG_MOD 717>, 707 <&cpg CPG_CORE R8A7792_CLK_ZS>, <&scif_clk>; 708 clock-names = "fck", "brg_int", "scif_clk"; 709 dmas = <&dmac0 0x39>, <&dmac0 0x3a>, 710 <&dmac1 0x39>, <&dmac1 0x3a>; 711 dma-names = "tx", "rx", "tx", "rx"; 712 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 713 resets = <&cpg 717>; 714 status = "disabled"; 715 }; 716 717 hscif1: serial@e62c8000 { 718 compatible = "renesas,hscif-r8a7792", 719 "renesas,rcar-gen2-hscif", "renesas,hscif"; 720 reg = <0 0xe62c8000 0 96>; 721 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 722 clocks = <&cpg CPG_MOD 716>, 723 <&cpg CPG_CORE R8A7792_CLK_ZS>, <&scif_clk>; 724 clock-names = "fck", "brg_int", "scif_clk"; 725 dmas = <&dmac0 0x4d>, <&dmac0 0x4e>, 726 <&dmac1 0x4d>, <&dmac1 0x4e>; 727 dma-names = "tx", "rx", "tx", "rx"; 728 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 729 resets = <&cpg 716>; 730 status = "disabled"; 731 }; 732 733 msiof0: spi@e6e20000 { 734 compatible = "renesas,msiof-r8a7792", 735 "renesas,rcar-gen2-msiof"; 736 reg = <0 0xe6e20000 0 0x0064>; 737 interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>; 738 clocks = <&cpg CPG_MOD 000>; 739 dmas = <&dmac0 0x51>, <&dmac0 0x52>, 740 <&dmac1 0x51>, <&dmac1 0x52>; 741 dma-names = "tx", "rx", "tx", "rx"; 742 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 743 resets = <&cpg 000>; 744 #address-cells = <1>; 745 #size-cells = <0>; 746 status = "disabled"; 747 }; 748 749 msiof1: spi@e6e10000 { 750 compatible = "renesas,msiof-r8a7792", 751 "renesas,rcar-gen2-msiof"; 752 reg = <0 0xe6e10000 0 0x0064>; 753 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>; 754 clocks = <&cpg CPG_MOD 208>; 755 dmas = <&dmac0 0x55>, <&dmac0 0x56>, 756 <&dmac1 0x55>, <&dmac1 0x56>; 757 dma-names = "tx", "rx", "tx", "rx"; 758 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 759 resets = <&cpg 208>; 760 #address-cells = <1>; 761 #size-cells = <0>; 762 status = "disabled"; 763 }; 764 765 can0: can@e6e80000 { 766 compatible = "renesas,can-r8a7792", 767 "renesas,rcar-gen2-can"; 768 reg = <0 0xe6e80000 0 0x1000>; 769 interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>; 770 clocks = <&cpg CPG_MOD 916>, 771 <&cpg CPG_CORE R8A7792_CLK_RCAN>, <&can_clk>; 772 clock-names = "clkp1", "clkp2", "can_clk"; 773 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 774 resets = <&cpg 916>; 775 status = "disabled"; 776 }; 777 778 can1: can@e6e88000 { 779 compatible = "renesas,can-r8a7792", 780 "renesas,rcar-gen2-can"; 781 reg = <0 0xe6e88000 0 0x1000>; 782 interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>; 783 clocks = <&cpg CPG_MOD 915>, 784 <&cpg CPG_CORE R8A7792_CLK_RCAN>, <&can_clk>; 785 clock-names = "clkp1", "clkp2", "can_clk"; 786 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 787 resets = <&cpg 915>; 788 status = "disabled"; 789 }; 790 791 vin0: video@e6ef0000 { 792 compatible = "renesas,vin-r8a7792", 793 "renesas,rcar-gen2-vin"; 794 reg = <0 0xe6ef0000 0 0x1000>; 795 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>; 796 clocks = <&cpg CPG_MOD 811>; 797 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 798 resets = <&cpg 811>; 799 status = "disabled"; 800 }; 801 802 vin1: video@e6ef1000 { 803 compatible = "renesas,vin-r8a7792", 804 "renesas,rcar-gen2-vin"; 805 reg = <0 0xe6ef1000 0 0x1000>; 806 interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>; 807 clocks = <&cpg CPG_MOD 810>; 808 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 809 resets = <&cpg 810>; 810 status = "disabled"; 811 }; 812 813 vin2: video@e6ef2000 { 814 compatible = "renesas,vin-r8a7792", 815 "renesas,rcar-gen2-vin"; 816 reg = <0 0xe6ef2000 0 0x1000>; 817 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>; 818 clocks = <&cpg CPG_MOD 809>; 819 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 820 resets = <&cpg 809>; 821 status = "disabled"; 822 }; 823 824 vin3: video@e6ef3000 { 825 compatible = "renesas,vin-r8a7792", 826 "renesas,rcar-gen2-vin"; 827 reg = <0 0xe6ef3000 0 0x1000>; 828 interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>; 829 clocks = <&cpg CPG_MOD 808>; 830 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 831 resets = <&cpg 808>; 832 status = "disabled"; 833 }; 834 835 vin4: video@e6ef4000 { 836 compatible = "renesas,vin-r8a7792", 837 "renesas,rcar-gen2-vin"; 838 reg = <0 0xe6ef4000 0 0x1000>; 839 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>; 840 clocks = <&cpg CPG_MOD 805>; 841 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 842 resets = <&cpg 805>; 843 status = "disabled"; 844 }; 845 846 vin5: video@e6ef5000 { 847 compatible = "renesas,vin-r8a7792", 848 "renesas,rcar-gen2-vin"; 849 reg = <0 0xe6ef5000 0 0x1000>; 850 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>; 851 clocks = <&cpg CPG_MOD 804>; 852 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 853 resets = <&cpg 804>; 854 status = "disabled"; 855 }; 856 857 sdhi0: mmc@ee100000 { 858 compatible = "renesas,sdhi-r8a7792", 859 "renesas,rcar-gen2-sdhi"; 860 reg = <0 0xee100000 0 0x328>; 861 interrupts = <0 165 IRQ_TYPE_LEVEL_HIGH>; 862 dmas = <&dmac0 0xcd>, <&dmac0 0xce>, 863 <&dmac1 0xcd>, <&dmac1 0xce>; 864 dma-names = "tx", "rx", "tx", "rx"; 865 clocks = <&cpg CPG_MOD 314>; 866 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 867 resets = <&cpg 314>; 868 status = "disabled"; 869 }; 870 871 gic: interrupt-controller@f1001000 { 872 compatible = "arm,gic-400"; 873 #interrupt-cells = <3>; 874 interrupt-controller; 875 reg = <0 0xf1001000 0 0x1000>, 876 <0 0xf1002000 0 0x2000>, 877 <0 0xf1004000 0 0x2000>, 878 <0 0xf1006000 0 0x2000>; 879 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | 880 IRQ_TYPE_LEVEL_HIGH)>; 881 clocks = <&cpg CPG_MOD 408>; 882 clock-names = "clk"; 883 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 884 resets = <&cpg 408>; 885 }; 886 887 vsp@fe928000 { 888 compatible = "renesas,vsp1"; 889 reg = <0 0xfe928000 0 0x8000>; 890 interrupts = <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>; 891 clocks = <&cpg CPG_MOD 131>; 892 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 893 resets = <&cpg 131>; 894 }; 895 896 vsp@fe930000 { 897 compatible = "renesas,vsp1"; 898 reg = <0 0xfe930000 0 0x8000>; 899 interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>; 900 clocks = <&cpg CPG_MOD 128>; 901 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 902 resets = <&cpg 128>; 903 }; 904 905 vsp@fe938000 { 906 compatible = "renesas,vsp1"; 907 reg = <0 0xfe938000 0 0x8000>; 908 interrupts = <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>; 909 clocks = <&cpg CPG_MOD 127>; 910 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 911 resets = <&cpg 127>; 912 }; 913 914 jpu: jpeg-codec@fe980000 { 915 compatible = "renesas,jpu-r8a7792", 916 "renesas,rcar-gen2-jpu"; 917 reg = <0 0xfe980000 0 0x10300>; 918 interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>; 919 clocks = <&cpg CPG_MOD 106>; 920 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 921 resets = <&cpg 106>; 922 }; 923 924 du: display@feb00000 { 925 compatible = "renesas,du-r8a7792"; 926 reg = <0 0xfeb00000 0 0x40000>; 927 interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>, 928 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>; 929 clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>; 930 clock-names = "du.0", "du.1"; 931 resets = <&cpg 724>; 932 reset-names = "du.0"; 933 status = "disabled"; 934 935 ports { 936 #address-cells = <1>; 937 #size-cells = <0>; 938 939 port@0 { 940 reg = <0>; 941 du_out_rgb0: endpoint { 942 }; 943 }; 944 port@1 { 945 reg = <1>; 946 du_out_rgb1: endpoint { 947 }; 948 }; 949 }; 950 }; 951 952 prr: chipid@ff000044 { 953 compatible = "renesas,prr"; 954 reg = <0 0xff000044 0 4>; 955 bootph-all; 956 }; 957 958 cmt0: timer@ffca0000 { 959 compatible = "renesas,r8a7792-cmt0", 960 "renesas,rcar-gen2-cmt0"; 961 reg = <0 0xffca0000 0 0x1004>; 962 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 963 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; 964 clocks = <&cpg CPG_MOD 124>; 965 clock-names = "fck"; 966 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 967 resets = <&cpg 124>; 968 969 status = "disabled"; 970 }; 971 972 cmt1: timer@e6130000 { 973 compatible = "renesas,r8a7792-cmt1", 974 "renesas,rcar-gen2-cmt1"; 975 reg = <0 0xe6130000 0 0x1004>; 976 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 977 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 978 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, 979 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 980 <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, 981 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 982 <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, 983 <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; 984 clocks = <&cpg CPG_MOD 329>; 985 clock-names = "fck"; 986 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 987 resets = <&cpg 329>; 988 989 status = "disabled"; 990 }; 991 }; 992 993 timer { 994 compatible = "arm,armv7-timer"; 995 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, 996 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, 997 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, 998 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>; 999 interrupt-names = "sec-phys", "phys", "virt", "hyp-phys"; 1000 }; 1001};
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