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qcom-msm8974.dtsi
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linux-6.19.14/arch/arm/boot/dts/qcom/qcom-msm8974.dtsi
1// SPDX-License-Identifier: GPL-2.0 2/dts-v1/; 3 4#include <dt-bindings/interconnect/qcom,msm8974.h> 5#include <dt-bindings/interrupt-controller/arm-gic.h> 6#include <dt-bindings/clock/qcom,dsi-phy-28nm.h> 7#include <dt-bindings/clock/qcom,gcc-msm8974.h> 8#include <dt-bindings/clock/qcom,mmcc-msm8974.h> 9#include <dt-bindings/clock/qcom,rpmcc.h> 10#include <dt-bindings/reset/qcom,gcc-msm8974.h> 11#include <dt-bindings/gpio/gpio.h> 12 13/ { 14 #address-cells = <1>; 15 #size-cells = <1>; 16 interrupt-parent = <&intc>; 17 18 chosen { }; 19 20 clocks { 21 xo_board: xo_board { 22 compatible = "fixed-clock"; 23 #clock-cells = <0>; 24 clock-frequency = <19200000>; 25 }; 26 27 sleep_clk: sleep_clk { 28 compatible = "fixed-clock"; 29 #clock-cells = <0>; 30 clock-frequency = <32768>; 31 }; 32 }; 33 34 cpus { 35 #address-cells = <1>; 36 #size-cells = <0>; 37 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 38 39 cpu0: cpu@0 { 40 compatible = "qcom,krait"; 41 enable-method = "qcom,kpss-acc-v2"; 42 device_type = "cpu"; 43 reg = <0>; 44 next-level-cache = <&l2>; 45 qcom,acc = <&acc0>; 46 qcom,saw = <&saw0>; 47 cpu-idle-states = <&cpu_spc>; 48 }; 49 50 cpu1: cpu@1 { 51 compatible = "qcom,krait"; 52 enable-method = "qcom,kpss-acc-v2"; 53 device_type = "cpu"; 54 reg = <1>; 55 next-level-cache = <&l2>; 56 qcom,acc = <&acc1>; 57 qcom,saw = <&saw1>; 58 cpu-idle-states = <&cpu_spc>; 59 }; 60 61 cpu2: cpu@2 { 62 compatible = "qcom,krait"; 63 enable-method = "qcom,kpss-acc-v2"; 64 device_type = "cpu"; 65 reg = <2>; 66 next-level-cache = <&l2>; 67 qcom,acc = <&acc2>; 68 qcom,saw = <&saw2>; 69 cpu-idle-states = <&cpu_spc>; 70 }; 71 72 cpu3: cpu@3 { 73 compatible = "qcom,krait"; 74 enable-method = "qcom,kpss-acc-v2"; 75 device_type = "cpu"; 76 reg = <3>; 77 next-level-cache = <&l2>; 78 qcom,acc = <&acc3>; 79 qcom,saw = <&saw3>; 80 cpu-idle-states = <&cpu_spc>; 81 }; 82 83 l2: l2-cache { 84 compatible = "cache"; 85 cache-level = <2>; 86 cache-unified; 87 qcom,saw = <&saw_l2>; 88 }; 89 90 idle-states { 91 cpu_spc: cpu-spc { 92 compatible = "qcom,idle-state-spc", 93 "arm,idle-state"; 94 entry-latency-us = <150>; 95 exit-latency-us = <200>; 96 min-residency-us = <2000>; 97 }; 98 }; 99 }; 100 101 firmware { 102 scm { 103 compatible = "qcom,scm-msm8974", "qcom,scm"; 104 clocks = <&gcc GCC_CE1_CLK>, <&gcc GCC_CE1_AXI_CLK>, <&gcc GCC_CE1_AHB_CLK>; 105 clock-names = "core", "bus", "iface"; 106 }; 107 }; 108 109 memory@0 { 110 device_type = "memory"; 111 reg = <0x0 0x0>; 112 }; 113 114 pmu { 115 compatible = "qcom,krait-pmu"; 116 interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 117 }; 118 119 rpm: remoteproc { 120 compatible = "qcom,msm8974-rpm-proc", "qcom,rpm-proc"; 121 122 master-stats { 123 compatible = "qcom,rpm-master-stats"; 124 qcom,rpm-msg-ram = <&apss_master_stats>, 125 <&mpss_master_stats>, 126 <&lpss_master_stats>, 127 <&pronto_master_stats>; 128 qcom,master-names = "APSS", 129 "MPSS", 130 "LPSS", 131 "PRONTO"; 132 }; 133 134 smd-edge { 135 interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>; 136 mboxes = <&apcs 0>; 137 qcom,smd-edge = <15>; 138 139 rpm_requests: rpm-requests { 140 compatible = "qcom,rpm-msm8974", "qcom,smd-rpm"; 141 qcom,smd-channels = "rpm_requests"; 142 143 rpmcc: clock-controller { 144 compatible = "qcom,rpmcc-msm8974", "qcom,rpmcc"; 145 #clock-cells = <1>; 146 clocks = <&xo_board>; 147 clock-names = "xo"; 148 }; 149 }; 150 }; 151 }; 152 153 reserved_memory: reserved-memory { 154 #address-cells = <1>; 155 #size-cells = <1>; 156 ranges; 157 158 mpss_region: mpss@8000000 { 159 reg = <0x08000000 0x5100000>; 160 no-map; 161 }; 162 163 mba_region: mba@d100000 { 164 reg = <0x0d100000 0x100000>; 165 no-map; 166 }; 167 168 wcnss_region: wcnss@d200000 { 169 reg = <0x0d200000 0xa00000>; 170 no-map; 171 }; 172 173 adsp_region: adsp@dc00000 { 174 reg = <0x0dc00000 0x1900000>; 175 no-map; 176 }; 177 178 venus_region: memory@f500000 { 179 reg = <0x0f500000 0x500000>; 180 no-map; 181 }; 182 183 smem_region: smem@fa00000 { 184 reg = <0xfa00000 0x200000>; 185 no-map; 186 }; 187 188 tz_region: memory@fc00000 { 189 reg = <0x0fc00000 0x160000>; 190 no-map; 191 }; 192 193 rfsa_mem: memory@fd60000 { 194 reg = <0x0fd60000 0x20000>; 195 no-map; 196 }; 197 198 rmtfs@fd80000 { 199 compatible = "qcom,rmtfs-mem"; 200 reg = <0x0fd80000 0x180000>; 201 no-map; 202 203 qcom,client-id = <1>; 204 }; 205 }; 206 207 smem { 208 compatible = "qcom,smem"; 209 210 memory-region = <&smem_region>; 211 qcom,rpm-msg-ram = <&rpm_msg_ram>; 212 213 hwlocks = <&tcsr_mutex 3>; 214 }; 215 216 smp2p-adsp { 217 compatible = "qcom,smp2p"; 218 qcom,smem = <443>, <429>; 219 220 interrupt-parent = <&intc>; 221 interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>; 222 223 mboxes = <&apcs 10>; 224 225 qcom,local-pid = <0>; 226 qcom,remote-pid = <2>; 227 228 adsp_smp2p_out: master-kernel { 229 qcom,entry-name = "master-kernel"; 230 #qcom,smem-state-cells = <1>; 231 }; 232 233 adsp_smp2p_in: slave-kernel { 234 qcom,entry-name = "slave-kernel"; 235 236 interrupt-controller; 237 #interrupt-cells = <2>; 238 }; 239 }; 240 241 smp2p-modem { 242 compatible = "qcom,smp2p"; 243 qcom,smem = <435>, <428>; 244 245 interrupt-parent = <&intc>; 246 interrupts = <GIC_SPI 27 IRQ_TYPE_EDGE_RISING>; 247 248 mboxes = <&apcs 14>; 249 250 qcom,local-pid = <0>; 251 qcom,remote-pid = <1>; 252 253 modem_smp2p_out: master-kernel { 254 qcom,entry-name = "master-kernel"; 255 #qcom,smem-state-cells = <1>; 256 }; 257 258 modem_smp2p_in: slave-kernel { 259 qcom,entry-name = "slave-kernel"; 260 261 interrupt-controller; 262 #interrupt-cells = <2>; 263 }; 264 }; 265 266 smp2p-wcnss { 267 compatible = "qcom,smp2p"; 268 qcom,smem = <451>, <431>; 269 270 interrupt-parent = <&intc>; 271 interrupts = <GIC_SPI 143 IRQ_TYPE_EDGE_RISING>; 272 273 mboxes = <&apcs 18>; 274 275 qcom,local-pid = <0>; 276 qcom,remote-pid = <4>; 277 278 wcnss_smp2p_out: master-kernel { 279 qcom,entry-name = "master-kernel"; 280 281 #qcom,smem-state-cells = <1>; 282 }; 283 284 wcnss_smp2p_in: slave-kernel { 285 qcom,entry-name = "slave-kernel"; 286 287 interrupt-controller; 288 #interrupt-cells = <2>; 289 }; 290 }; 291 292 smsm { 293 compatible = "qcom,smsm"; 294 295 #address-cells = <1>; 296 #size-cells = <0>; 297 298 mboxes = <0>, <&apcs 13>, <&apcs 9>, <&apcs 19>; 299 300 apps_smsm: apps@0 { 301 reg = <0>; 302 303 #qcom,smem-state-cells = <1>; 304 }; 305 306 modem_smsm: modem@1 { 307 reg = <1>; 308 interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>; 309 310 interrupt-controller; 311 #interrupt-cells = <2>; 312 }; 313 314 adsp_smsm: adsp@2 { 315 reg = <2>; 316 interrupts = <GIC_SPI 157 IRQ_TYPE_EDGE_RISING>; 317 318 interrupt-controller; 319 #interrupt-cells = <2>; 320 }; 321 322 wcnss_smsm: wcnss@7 { 323 reg = <7>; 324 interrupts = <GIC_SPI 144 IRQ_TYPE_EDGE_RISING>; 325 326 interrupt-controller; 327 #interrupt-cells = <2>; 328 }; 329 }; 330 331 soc: soc { 332 #address-cells = <1>; 333 #size-cells = <1>; 334 ranges; 335 compatible = "simple-bus"; 336 337 intc: interrupt-controller@f9000000 { 338 compatible = "qcom,msm-qgic2"; 339 interrupt-controller; 340 #interrupt-cells = <3>; 341 reg = <0xf9000000 0x1000>, 342 <0xf9002000 0x1000>; 343 }; 344 345 apcs: mailbox@f9011000 { 346 compatible = "qcom,msm8974-apcs-kpss-global", 347 "qcom,msm8994-apcs-kpss-global", "syscon"; 348 reg = <0xf9011000 0x1000>; 349 #mbox-cells = <1>; 350 }; 351 352 saw_l2: power-manager@f9012000 { 353 compatible = "qcom,msm8974-saw2-v2.1-l2", "qcom,saw2"; 354 reg = <0xf9012000 0x1000>; 355 }; 356 357 watchdog@f9017000 { 358 compatible = "qcom,apss-wdt-msm8974", "qcom,kpss-wdt"; 359 reg = <0xf9017000 0x1000>; 360 interrupts = <GIC_SPI 3 IRQ_TYPE_EDGE_RISING>, 361 <GIC_SPI 4 IRQ_TYPE_EDGE_RISING>; 362 clocks = <&sleep_clk>; 363 }; 364 365 timer@f9020000 { 366 #address-cells = <1>; 367 #size-cells = <1>; 368 ranges; 369 compatible = "arm,armv7-timer-mem"; 370 reg = <0xf9020000 0x1000>; 371 clock-frequency = <19200000>; 372 373 frame@f9021000 { 374 frame-number = <0>; 375 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 376 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 377 reg = <0xf9021000 0x1000>, 378 <0xf9022000 0x1000>; 379 }; 380 381 frame@f9023000 { 382 frame-number = <1>; 383 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 384 reg = <0xf9023000 0x1000>; 385 status = "disabled"; 386 }; 387 388 frame@f9024000 { 389 frame-number = <2>; 390 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 391 reg = <0xf9024000 0x1000>; 392 status = "disabled"; 393 }; 394 395 frame@f9025000 { 396 frame-number = <3>; 397 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 398 reg = <0xf9025000 0x1000>; 399 status = "disabled"; 400 }; 401 402 frame@f9026000 { 403 frame-number = <4>; 404 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 405 reg = <0xf9026000 0x1000>; 406 status = "disabled"; 407 }; 408 409 frame@f9027000 { 410 frame-number = <5>; 411 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 412 reg = <0xf9027000 0x1000>; 413 status = "disabled"; 414 }; 415 416 frame@f9028000 { 417 frame-number = <6>; 418 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 419 reg = <0xf9028000 0x1000>; 420 status = "disabled"; 421 }; 422 }; 423 424 acc0: power-manager@f9088000 { 425 compatible = "qcom,kpss-acc-v2"; 426 reg = <0xf9088000 0x1000>, <0xf9008000 0x1000>; 427 }; 428 429 saw0: power-manager@f9089000 { 430 compatible = "qcom,msm8974-saw2-v2.1-cpu", "qcom,saw2"; 431 reg = <0xf9089000 0x1000>, <0xf9009000 0x1000>; 432 }; 433 434 acc1: power-manager@f9098000 { 435 compatible = "qcom,kpss-acc-v2"; 436 reg = <0xf9098000 0x1000>, <0xf9008000 0x1000>; 437 }; 438 439 saw1: power-manager@f9099000 { 440 compatible = "qcom,msm8974-saw2-v2.1-cpu", "qcom,saw2"; 441 reg = <0xf9099000 0x1000>, <0xf9009000 0x1000>; 442 }; 443 444 acc2: power-manager@f90a8000 { 445 compatible = "qcom,kpss-acc-v2"; 446 reg = <0xf90a8000 0x1000>, <0xf9008000 0x1000>; 447 }; 448 449 saw2: power-manager@f90a9000 { 450 compatible = "qcom,msm8974-saw2-v2.1-cpu", "qcom,saw2"; 451 reg = <0xf90a9000 0x1000>, <0xf9009000 0x1000>; 452 }; 453 454 acc3: power-manager@f90b8000 { 455 compatible = "qcom,kpss-acc-v2"; 456 reg = <0xf90b8000 0x1000>, <0xf9008000 0x1000>; 457 }; 458 459 saw3: power-manager@f90b9000 { 460 compatible = "qcom,msm8974-saw2-v2.1-cpu", "qcom,saw2"; 461 reg = <0xf90b9000 0x1000>, <0xf9009000 0x1000>; 462 }; 463 464 sdhc_1: mmc@f9824900 { 465 compatible = "qcom,msm8974-sdhci", "qcom,sdhci-msm-v4"; 466 reg = <0xf9824900 0x11c>, <0xf9824000 0x800>; 467 reg-names = "hc", "core"; 468 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 469 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 470 interrupt-names = "hc_irq", "pwr_irq"; 471 clocks = <&gcc GCC_SDCC1_AHB_CLK>, 472 <&gcc GCC_SDCC1_APPS_CLK>, 473 <&xo_board>; 474 clock-names = "iface", "core", "xo"; 475 bus-width = <8>; 476 non-removable; 477 478 status = "disabled"; 479 }; 480 481 sdhc_3: mmc@f9864900 { 482 compatible = "qcom,msm8974-sdhci", "qcom,sdhci-msm-v4"; 483 reg = <0xf9864900 0x11c>, <0xf9864000 0x800>; 484 reg-names = "hc", "core"; 485 interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>, 486 <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>; 487 interrupt-names = "hc_irq", "pwr_irq"; 488 clocks = <&gcc GCC_SDCC3_AHB_CLK>, 489 <&gcc GCC_SDCC3_APPS_CLK>, 490 <&xo_board>; 491 clock-names = "iface", "core", "xo"; 492 bus-width = <4>; 493 494 #address-cells = <1>; 495 #size-cells = <0>; 496 497 status = "disabled"; 498 }; 499 500 sdhc_2: mmc@f98a4900 { 501 compatible = "qcom,msm8974-sdhci", "qcom,sdhci-msm-v4"; 502 reg = <0xf98a4900 0x11c>, <0xf98a4000 0x800>; 503 reg-names = "hc", "core"; 504 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 505 <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>; 506 interrupt-names = "hc_irq", "pwr_irq"; 507 clocks = <&gcc GCC_SDCC2_AHB_CLK>, 508 <&gcc GCC_SDCC2_APPS_CLK>, 509 <&xo_board>; 510 clock-names = "iface", "core", "xo"; 511 bus-width = <4>; 512 513 #address-cells = <1>; 514 #size-cells = <0>; 515 516 status = "disabled"; 517 }; 518 519 blsp1_uart1: serial@f991d000 { 520 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 521 reg = <0xf991d000 0x1000>; 522 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; 523 clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; 524 clock-names = "core", "iface"; 525 status = "disabled"; 526 }; 527 528 blsp1_uart2: serial@f991e000 { 529 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 530 reg = <0xf991e000 0x1000>; 531 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 532 clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; 533 clock-names = "core", "iface"; 534 pinctrl-names = "default"; 535 pinctrl-0 = <&blsp1_uart2_default>; 536 status = "disabled"; 537 }; 538 539 blsp1_i2c1: i2c@f9923000 { 540 status = "disabled"; 541 compatible = "qcom,i2c-qup-v2.1.1"; 542 reg = <0xf9923000 0x1000>; 543 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 544 clocks = <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; 545 clock-names = "core", "iface"; 546 pinctrl-names = "default", "sleep"; 547 pinctrl-0 = <&blsp1_i2c1_default>; 548 pinctrl-1 = <&blsp1_i2c1_sleep>; 549 #address-cells = <1>; 550 #size-cells = <0>; 551 }; 552 553 blsp1_i2c2: i2c@f9924000 { 554 status = "disabled"; 555 compatible = "qcom,i2c-qup-v2.1.1"; 556 reg = <0xf9924000 0x1000>; 557 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 558 clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; 559 clock-names = "core", "iface"; 560 pinctrl-names = "default", "sleep"; 561 pinctrl-0 = <&blsp1_i2c2_default>; 562 pinctrl-1 = <&blsp1_i2c2_sleep>; 563 #address-cells = <1>; 564 #size-cells = <0>; 565 }; 566 567 blsp1_i2c3: i2c@f9925000 { 568 status = "disabled"; 569 compatible = "qcom,i2c-qup-v2.1.1"; 570 reg = <0xf9925000 0x1000>; 571 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 572 clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; 573 clock-names = "core", "iface"; 574 pinctrl-names = "default", "sleep"; 575 pinctrl-0 = <&blsp1_i2c3_default>; 576 pinctrl-1 = <&blsp1_i2c3_sleep>; 577 #address-cells = <1>; 578 #size-cells = <0>; 579 }; 580 581 blsp1_i2c6: i2c@f9928000 { 582 status = "disabled"; 583 compatible = "qcom,i2c-qup-v2.1.1"; 584 reg = <0xf9928000 0x1000>; 585 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; 586 clocks = <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; 587 clock-names = "core", "iface"; 588 pinctrl-names = "default", "sleep"; 589 pinctrl-0 = <&blsp1_i2c6_default>; 590 pinctrl-1 = <&blsp1_i2c6_sleep>; 591 #address-cells = <1>; 592 #size-cells = <0>; 593 }; 594 595 blsp2_dma: dma-controller@f9944000 { 596 compatible = "qcom,bam-v1.4.0"; 597 reg = <0xf9944000 0x19000>; 598 interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>; 599 clocks = <&gcc GCC_BLSP2_AHB_CLK>; 600 clock-names = "bam_clk"; 601 #dma-cells = <1>; 602 qcom,ee = <0>; 603 }; 604 605 blsp2_uart1: serial@f995d000 { 606 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 607 reg = <0xf995d000 0x1000>; 608 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; 609 clocks = <&gcc GCC_BLSP2_UART1_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>; 610 clock-names = "core", "iface"; 611 pinctrl-names = "default", "sleep"; 612 pinctrl-0 = <&blsp2_uart1_default>; 613 pinctrl-1 = <&blsp2_uart1_sleep>; 614 status = "disabled"; 615 }; 616 617 blsp2_uart2: serial@f995e000 { 618 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 619 reg = <0xf995e000 0x1000>; 620 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 621 clocks = <&gcc GCC_BLSP2_UART2_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>; 622 clock-names = "core", "iface"; 623 status = "disabled"; 624 }; 625 626 blsp2_uart4: serial@f9960000 { 627 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 628 reg = <0xf9960000 0x1000>; 629 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 630 clocks = <&gcc GCC_BLSP2_UART4_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>; 631 clock-names = "core", "iface"; 632 pinctrl-names = "default"; 633 pinctrl-0 = <&blsp2_uart4_default>; 634 status = "disabled"; 635 }; 636 637 blsp2_i2c2: i2c@f9964000 { 638 status = "disabled"; 639 compatible = "qcom,i2c-qup-v2.1.1"; 640 reg = <0xf9964000 0x1000>; 641 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; 642 clocks = <&gcc GCC_BLSP2_QUP2_I2C_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>; 643 clock-names = "core", "iface"; 644 pinctrl-names = "default", "sleep"; 645 pinctrl-0 = <&blsp2_i2c2_default>; 646 pinctrl-1 = <&blsp2_i2c2_sleep>; 647 #address-cells = <1>; 648 #size-cells = <0>; 649 }; 650 651 blsp2_i2c5: i2c@f9967000 { 652 status = "disabled"; 653 compatible = "qcom,i2c-qup-v2.1.1"; 654 reg = <0xf9967000 0x1000>; 655 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; 656 clocks = <&gcc GCC_BLSP2_QUP5_I2C_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>; 657 clock-names = "core", "iface"; 658 dmas = <&blsp2_dma 20>, <&blsp2_dma 21>; 659 dma-names = "tx", "rx"; 660 pinctrl-names = "default", "sleep"; 661 pinctrl-0 = <&blsp2_i2c5_default>; 662 pinctrl-1 = <&blsp2_i2c5_sleep>; 663 #address-cells = <1>; 664 #size-cells = <0>; 665 }; 666 667 blsp2_i2c6: i2c@f9968000 { 668 status = "disabled"; 669 compatible = "qcom,i2c-qup-v2.1.1"; 670 reg = <0xf9968000 0x1000>; 671 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; 672 clocks = <&gcc GCC_BLSP2_QUP6_I2C_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>; 673 clock-names = "core", "iface"; 674 pinctrl-names = "default", "sleep"; 675 pinctrl-0 = <&blsp2_i2c6_default>; 676 pinctrl-1 = <&blsp2_i2c6_sleep>; 677 #address-cells = <1>; 678 #size-cells = <0>; 679 }; 680 681 usb: usb@f9a55000 { 682 compatible = "qcom,ci-hdrc"; 683 reg = <0xf9a55000 0x200>, 684 <0xf9a55200 0x200>; 685 interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>; 686 clocks = <&gcc GCC_USB_HS_AHB_CLK>, 687 <&gcc GCC_USB_HS_SYSTEM_CLK>; 688 clock-names = "iface", "core"; 689 assigned-clocks = <&gcc GCC_USB_HS_SYSTEM_CLK>; 690 assigned-clock-rates = <75000000>; 691 resets = <&gcc GCC_USB_HS_BCR>; 692 reset-names = "core"; 693 phy_type = "ulpi"; 694 dr_mode = "otg"; 695 ahb-burst-config = <0>; 696 phy-names = "usb-phy"; 697 status = "disabled"; 698 #reset-cells = <1>; 699 700 ulpi { 701 usb_hs1_phy: phy-0 { 702 compatible = "qcom,usb-hs-phy-msm8974", 703 "qcom,usb-hs-phy"; 704 #phy-cells = <0>; 705 clocks = <&xo_board>, <&gcc GCC_USB2A_PHY_SLEEP_CLK>; 706 clock-names = "ref", "sleep"; 707 resets = <&gcc GCC_USB2A_PHY_BCR>, <&usb 0>; 708 reset-names = "phy", "por"; 709 status = "disabled"; 710 }; 711 712 usb_hs2_phy: phy-1 { 713 compatible = "qcom,usb-hs-phy-msm8974", 714 "qcom,usb-hs-phy"; 715 #phy-cells = <0>; 716 clocks = <&xo_board>, <&gcc GCC_USB2B_PHY_SLEEP_CLK>; 717 clock-names = "ref", "sleep"; 718 resets = <&gcc GCC_USB2B_PHY_BCR>, <&usb 1>; 719 reset-names = "phy", "por"; 720 status = "disabled"; 721 }; 722 }; 723 }; 724 725 rng@f9bff000 { 726 compatible = "qcom,prng"; 727 reg = <0xf9bff000 0x200>; 728 clocks = <&gcc GCC_PRNG_AHB_CLK>; 729 clock-names = "core"; 730 }; 731 732 pronto: remoteproc@fb204000 { 733 compatible = "qcom,pronto-v2-pil", "qcom,pronto"; 734 reg = <0xfb204000 0x2000>, <0xfb202000 0x1000>, <0xfb21b000 0x3000>; 735 reg-names = "ccu", "dxe", "pmu"; 736 737 memory-region = <&wcnss_region>; 738 739 interrupts-extended = <&intc GIC_SPI 149 IRQ_TYPE_EDGE_RISING>, 740 <&wcnss_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 741 <&wcnss_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 742 <&wcnss_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 743 <&wcnss_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 744 interrupt-names = "wdog", "fatal", "ready", "handover", "stop-ack"; 745 746 qcom,smem-states = <&wcnss_smp2p_out 0>; 747 qcom,smem-state-names = "stop"; 748 749 status = "disabled"; 750 751 iris { 752 compatible = "qcom,wcn3680"; 753 754 clocks = <&rpmcc RPM_SMD_CXO_A2>; 755 clock-names = "xo"; 756 }; 757 758 smd-edge { 759 interrupts = <GIC_SPI 142 IRQ_TYPE_EDGE_RISING>; 760 761 mboxes = <&apcs 17>; 762 qcom,smd-edge = <6>; 763 764 wcnss { 765 compatible = "qcom,wcnss"; 766 qcom,smd-channels = "WCNSS_CTRL"; 767 status = "disabled"; 768 769 qcom,mmio = <&pronto>; 770 771 bluetooth { 772 compatible = "qcom,wcnss-bt"; 773 }; 774 775 wifi { 776 compatible = "qcom,wcnss-wlan"; 777 778 interrupts = <GIC_SPI 145 IRQ_TYPE_EDGE_RISING>, 779 <GIC_SPI 146 IRQ_TYPE_EDGE_RISING>; 780 interrupt-names = "tx", "rx"; 781 782 qcom,smem-states = <&apps_smsm 10>, <&apps_smsm 9>; 783 qcom,smem-state-names = "tx-enable", 784 "tx-rings-empty"; 785 }; 786 }; 787 }; 788 }; 789 790 sram@fc190000 { 791 compatible = "qcom,msm8974-rpm-stats"; 792 reg = <0xfc190000 0x10000>; 793 }; 794 795 etf@fc307000 { 796 compatible = "arm,coresight-tmc", "arm,primecell"; 797 reg = <0xfc307000 0x1000>; 798 799 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 800 clock-names = "apb_pclk", "atclk"; 801 802 out-ports { 803 port { 804 etf_out: endpoint { 805 remote-endpoint = <&replicator_in>; 806 }; 807 }; 808 }; 809 810 in-ports { 811 port { 812 etf_in: endpoint { 813 remote-endpoint = <&merger_out>; 814 }; 815 }; 816 }; 817 }; 818 819 tpiu@fc318000 { 820 compatible = "arm,coresight-tpiu", "arm,primecell"; 821 reg = <0xfc318000 0x1000>; 822 823 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 824 clock-names = "apb_pclk", "atclk"; 825 826 in-ports { 827 port { 828 tpiu_in: endpoint { 829 remote-endpoint = <&replicator_out1>; 830 }; 831 }; 832 }; 833 }; 834 835 funnel@fc31a000 { 836 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 837 reg = <0xfc31a000 0x1000>; 838 839 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 840 clock-names = "apb_pclk", "atclk"; 841 842 in-ports { 843 #address-cells = <1>; 844 #size-cells = <0>; 845 846 /* 847 * Not described input ports: 848 * 0 - not-connected 849 * 1 - connected trought funnel to Multimedia CPU 850 * 2 - connected to Wireless CPU 851 * 3 - not-connected 852 * 4 - not-connected 853 * 6 - not-connected 854 * 7 - connected to STM 855 */ 856 port@5 { 857 reg = <5>; 858 funnel1_in5: endpoint { 859 remote-endpoint = <&kpss_out>; 860 }; 861 }; 862 }; 863 864 out-ports { 865 port { 866 funnel1_out: endpoint { 867 remote-endpoint = <&merger_in1>; 868 }; 869 }; 870 }; 871 }; 872 873 funnel@fc31b000 { 874 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 875 reg = <0xfc31b000 0x1000>; 876 877 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 878 clock-names = "apb_pclk", "atclk"; 879 880 in-ports { 881 #address-cells = <1>; 882 #size-cells = <0>; 883 884 /* 885 * Not described input ports: 886 * 0 - connected trought funnel to Audio, Modem and 887 * Resource and Power Manager CPU's 888 * 2...7 - not-connected 889 */ 890 port@1 { 891 reg = <1>; 892 merger_in1: endpoint { 893 remote-endpoint = <&funnel1_out>; 894 }; 895 }; 896 }; 897 898 out-ports { 899 port { 900 merger_out: endpoint { 901 remote-endpoint = <&etf_in>; 902 }; 903 }; 904 }; 905 }; 906 907 replicator@fc31c000 { 908 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 909 reg = <0xfc31c000 0x1000>; 910 911 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 912 clock-names = "apb_pclk", "atclk"; 913 914 out-ports { 915 #address-cells = <1>; 916 #size-cells = <0>; 917 918 port@0 { 919 reg = <0>; 920 replicator_out0: endpoint { 921 remote-endpoint = <&etr_in>; 922 }; 923 }; 924 port@1 { 925 reg = <1>; 926 replicator_out1: endpoint { 927 remote-endpoint = <&tpiu_in>; 928 }; 929 }; 930 }; 931 932 in-ports { 933 port { 934 replicator_in: endpoint { 935 remote-endpoint = <&etf_out>; 936 }; 937 }; 938 }; 939 }; 940 941 etr@fc322000 { 942 compatible = "arm,coresight-tmc", "arm,primecell"; 943 reg = <0xfc322000 0x1000>; 944 945 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 946 clock-names = "apb_pclk", "atclk"; 947 948 in-ports { 949 port { 950 etr_in: endpoint { 951 remote-endpoint = <&replicator_out0>; 952 }; 953 }; 954 }; 955 }; 956 957 etm@fc33c000 { 958 compatible = "arm,coresight-etm4x", "arm,primecell"; 959 reg = <0xfc33c000 0x1000>; 960 961 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 962 clock-names = "apb_pclk", "atclk"; 963 964 cpu = <&cpu0>; 965 966 out-ports { 967 port { 968 etm0_out: endpoint { 969 remote-endpoint = <&kpss_in0>; 970 }; 971 }; 972 }; 973 }; 974 975 etm@fc33d000 { 976 compatible = "arm,coresight-etm4x", "arm,primecell"; 977 reg = <0xfc33d000 0x1000>; 978 979 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 980 clock-names = "apb_pclk", "atclk"; 981 982 cpu = <&cpu1>; 983 984 out-ports { 985 port { 986 etm1_out: endpoint { 987 remote-endpoint = <&kpss_in1>; 988 }; 989 }; 990 }; 991 }; 992 993 etm@fc33e000 { 994 compatible = "arm,coresight-etm4x", "arm,primecell"; 995 reg = <0xfc33e000 0x1000>; 996 997 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 998 clock-names = "apb_pclk", "atclk"; 999 1000 cpu = <&cpu2>; 1001 1002 out-ports { 1003 port { 1004 etm2_out: endpoint { 1005 remote-endpoint = <&kpss_in2>; 1006 }; 1007 }; 1008 }; 1009 }; 1010 1011 etm@fc33f000 { 1012 compatible = "arm,coresight-etm4x", "arm,primecell"; 1013 reg = <0xfc33f000 0x1000>; 1014 1015 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 1016 clock-names = "apb_pclk", "atclk"; 1017 1018 cpu = <&cpu3>; 1019 1020 out-ports { 1021 port { 1022 etm3_out: endpoint { 1023 remote-endpoint = <&kpss_in3>; 1024 }; 1025 }; 1026 }; 1027 }; 1028 1029 /* KPSS funnel, only 4 inputs are used */ 1030 funnel@fc345000 { 1031 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 1032 reg = <0xfc345000 0x1000>; 1033 1034 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 1035 clock-names = "apb_pclk", "atclk"; 1036 1037 in-ports { 1038 #address-cells = <1>; 1039 #size-cells = <0>; 1040 1041 port@0 { 1042 reg = <0>; 1043 kpss_in0: endpoint { 1044 remote-endpoint = <&etm0_out>; 1045 }; 1046 }; 1047 port@1 { 1048 reg = <1>; 1049 kpss_in1: endpoint { 1050 remote-endpoint = <&etm1_out>; 1051 }; 1052 }; 1053 port@2 { 1054 reg = <2>; 1055 kpss_in2: endpoint { 1056 remote-endpoint = <&etm2_out>; 1057 }; 1058 }; 1059 port@3 { 1060 reg = <3>; 1061 kpss_in3: endpoint { 1062 remote-endpoint = <&etm3_out>; 1063 }; 1064 }; 1065 }; 1066 1067 out-ports { 1068 port { 1069 kpss_out: endpoint { 1070 remote-endpoint = <&funnel1_in5>; 1071 }; 1072 }; 1073 }; 1074 }; 1075 1076 bimc: interconnect@fc380000 { 1077 reg = <0xfc380000 0x6a000>; 1078 compatible = "qcom,msm8974-bimc"; 1079 #interconnect-cells = <1>; 1080 clock-names = "bus", "bus_a"; 1081 clocks = <&rpmcc RPM_SMD_BIMC_CLK>, 1082 <&rpmcc RPM_SMD_BIMC_A_CLK>; 1083 }; 1084 1085 gcc: clock-controller@fc400000 { 1086 compatible = "qcom,gcc-msm8974"; 1087 #clock-cells = <1>; 1088 #reset-cells = <1>; 1089 #power-domain-cells = <1>; 1090 reg = <0xfc400000 0x4000>; 1091 1092 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, 1093 <&sleep_clk>; 1094 clock-names = "xo", 1095 "sleep_clk"; 1096 }; 1097 1098 rpm_msg_ram: sram@fc428000 { 1099 compatible = "qcom,rpm-msg-ram"; 1100 reg = <0xfc428000 0x4000>; 1101 1102 #address-cells = <1>; 1103 #size-cells = <1>; 1104 ranges = <0 0xfc428000 0x4000>; 1105 1106 apss_master_stats: sram@150 { 1107 reg = <0x150 0x14>; 1108 }; 1109 1110 mpss_master_stats: sram@b50 { 1111 reg = <0xb50 0x14>; 1112 }; 1113 1114 lpss_master_stats: sram@1550 { 1115 reg = <0x1550 0x14>; 1116 }; 1117 1118 pronto_master_stats: sram@1f50 { 1119 reg = <0x1f50 0x14>; 1120 }; 1121 }; 1122 1123 snoc: interconnect@fc460000 { 1124 reg = <0xfc460000 0x4000>; 1125 compatible = "qcom,msm8974-snoc"; 1126 #interconnect-cells = <1>; 1127 clock-names = "bus", "bus_a"; 1128 clocks = <&rpmcc RPM_SMD_SNOC_CLK>, 1129 <&rpmcc RPM_SMD_SNOC_A_CLK>; 1130 }; 1131 1132 pnoc: interconnect@fc468000 { 1133 reg = <0xfc468000 0x4000>; 1134 compatible = "qcom,msm8974-pnoc"; 1135 #interconnect-cells = <1>; 1136 clock-names = "bus", "bus_a"; 1137 clocks = <&rpmcc RPM_SMD_PNOC_CLK>, 1138 <&rpmcc RPM_SMD_PNOC_A_CLK>; 1139 }; 1140 1141 ocmemnoc: interconnect@fc470000 { 1142 reg = <0xfc470000 0x4000>; 1143 compatible = "qcom,msm8974-ocmemnoc"; 1144 #interconnect-cells = <1>; 1145 clock-names = "bus", "bus_a"; 1146 clocks = <&rpmcc RPM_SMD_OCMEMGX_CLK>, 1147 <&rpmcc RPM_SMD_OCMEMGX_A_CLK>; 1148 }; 1149 1150 mmssnoc: interconnect@fc478000 { 1151 reg = <0xfc478000 0x4000>; 1152 compatible = "qcom,msm8974-mmssnoc"; 1153 #interconnect-cells = <1>; 1154 clock-names = "bus", "bus_a"; 1155 clocks = <&mmcc MMSS_S0_AXI_CLK>, 1156 <&mmcc MMSS_S0_AXI_CLK>; 1157 }; 1158 1159 cnoc: interconnect@fc480000 { 1160 reg = <0xfc480000 0x4000>; 1161 compatible = "qcom,msm8974-cnoc"; 1162 #interconnect-cells = <1>; 1163 clock-names = "bus", "bus_a"; 1164 clocks = <&rpmcc RPM_SMD_CNOC_CLK>, 1165 <&rpmcc RPM_SMD_CNOC_A_CLK>; 1166 }; 1167 1168 tsens: thermal-sensor@fc4a9000 { 1169 compatible = "qcom,msm8974-tsens", "qcom,tsens-v0_1"; 1170 reg = <0xfc4a9000 0x1000>, /* TM */ 1171 <0xfc4a8000 0x1000>; /* SROT */ 1172 nvmem-cells = <&tsens_mode>, 1173 <&tsens_base1>, <&tsens_base2>, 1174 <&tsens_use_backup>, 1175 <&tsens_mode_backup>, 1176 <&tsens_base1_backup>, <&tsens_base2_backup>, 1177 <&tsens_s0_p1>, <&tsens_s0_p2>, 1178 <&tsens_s1_p1>, <&tsens_s1_p2>, 1179 <&tsens_s2_p1>, <&tsens_s2_p2>, 1180 <&tsens_s3_p1>, <&tsens_s3_p2>, 1181 <&tsens_s4_p1>, <&tsens_s4_p2>, 1182 <&tsens_s5_p1>, <&tsens_s5_p2>, 1183 <&tsens_s6_p1>, <&tsens_s6_p2>, 1184 <&tsens_s7_p1>, <&tsens_s7_p2>, 1185 <&tsens_s8_p1>, <&tsens_s8_p2>, 1186 <&tsens_s9_p1>, <&tsens_s9_p2>, 1187 <&tsens_s10_p1>, <&tsens_s10_p2>, 1188 <&tsens_s0_p1_backup>, <&tsens_s0_p2_backup>, 1189 <&tsens_s1_p1_backup>, <&tsens_s1_p2_backup>, 1190 <&tsens_s2_p1_backup>, <&tsens_s2_p2_backup>, 1191 <&tsens_s3_p1_backup>, <&tsens_s3_p2_backup>, 1192 <&tsens_s4_p1_backup>, <&tsens_s4_p2_backup>, 1193 <&tsens_s5_p1_backup>, <&tsens_s5_p2_backup>, 1194 <&tsens_s6_p1_backup>, <&tsens_s6_p2_backup>, 1195 <&tsens_s7_p1_backup>, <&tsens_s7_p2_backup>, 1196 <&tsens_s8_p1_backup>, <&tsens_s8_p2_backup>, 1197 <&tsens_s9_p1_backup>, <&tsens_s9_p2_backup>, 1198 <&tsens_s10_p1_backup>, <&tsens_s10_p2_backup>; 1199 nvmem-cell-names = "mode", 1200 "base1", "base2", 1201 "use_backup", 1202 "mode_backup", 1203 "base1_backup", "base2_backup", 1204 "s0_p1", "s0_p2", 1205 "s1_p1", "s1_p2", 1206 "s2_p1", "s2_p2", 1207 "s3_p1", "s3_p2", 1208 "s4_p1", "s4_p2", 1209 "s5_p1", "s5_p2", 1210 "s6_p1", "s6_p2", 1211 "s7_p1", "s7_p2", 1212 "s8_p1", "s8_p2", 1213 "s9_p1", "s9_p2", 1214 "s10_p1", "s10_p2", 1215 "s0_p1_backup", "s0_p2_backup", 1216 "s1_p1_backup", "s1_p2_backup", 1217 "s2_p1_backup", "s2_p2_backup", 1218 "s3_p1_backup", "s3_p2_backup", 1219 "s4_p1_backup", "s4_p2_backup", 1220 "s5_p1_backup", "s5_p2_backup", 1221 "s6_p1_backup", "s6_p2_backup", 1222 "s7_p1_backup", "s7_p2_backup", 1223 "s8_p1_backup", "s8_p2_backup", 1224 "s9_p1_backup", "s9_p2_backup", 1225 "s10_p1_backup", "s10_p2_backup"; 1226 #qcom,sensors = <11>; 1227 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; 1228 interrupt-names = "uplow"; 1229 #thermal-sensor-cells = <1>; 1230 }; 1231 1232 restart@fc4ab000 { 1233 compatible = "qcom,pshold"; 1234 reg = <0xfc4ab000 0x4>; 1235 }; 1236 1237 qfprom: efuse@fc4bc000 { 1238 compatible = "qcom,msm8974-qfprom", "qcom,qfprom"; 1239 reg = <0xfc4bc000 0x2100>; 1240 #address-cells = <1>; 1241 #size-cells = <1>; 1242 1243 tsens_base1: base1@d0 { 1244 reg = <0xd0 0x1>; 1245 bits = <0 8>; 1246 }; 1247 1248 tsens_s0_p1: s0-p1@d1 { 1249 reg = <0xd1 0x1>; 1250 bits = <0 6>; 1251 }; 1252 1253 tsens_s1_p1: s1-p1@d2 { 1254 reg = <0xd1 0x2>; 1255 bits = <6 6>; 1256 }; 1257 1258 tsens_s2_p1: s2-p1@d2 { 1259 reg = <0xd2 0x2>; 1260 bits = <4 6>; 1261 }; 1262 1263 tsens_s3_p1: s3-p1@d3 { 1264 reg = <0xd3 0x1>; 1265 bits = <2 6>; 1266 }; 1267 1268 tsens_s4_p1: s4-p1@d4 { 1269 reg = <0xd4 0x1>; 1270 bits = <0 6>; 1271 }; 1272 1273 tsens_s5_p1: s5-p1@d4 { 1274 reg = <0xd4 0x2>; 1275 bits = <6 6>; 1276 }; 1277 1278 tsens_s6_p1: s6-p1@d5 { 1279 reg = <0xd5 0x2>; 1280 bits = <4 6>; 1281 }; 1282 1283 tsens_s7_p1: s7-p1@d6 { 1284 reg = <0xd6 0x1>; 1285 bits = <2 6>; 1286 }; 1287 1288 tsens_s8_p1: s8-p1@d7 { 1289 reg = <0xd7 0x1>; 1290 bits = <0 6>; 1291 }; 1292 1293 tsens_mode: mode@d7 { 1294 reg = <0xd7 0x1>; 1295 bits = <6 2>; 1296 }; 1297 1298 tsens_s9_p1: s9-p1@d8 { 1299 reg = <0xd8 0x1>; 1300 bits = <0 6>; 1301 }; 1302 1303 tsens_s10_p1: s10-p1@d8 { 1304 reg = <0xd8 0x2>; 1305 bits = <6 6>; 1306 }; 1307 1308 tsens_base2: base2@d9 { 1309 reg = <0xd9 0x2>; 1310 bits = <4 8>; 1311 }; 1312 1313 tsens_s0_p2: s0-p2@da { 1314 reg = <0xda 0x2>; 1315 bits = <4 6>; 1316 }; 1317 1318 tsens_s1_p2: s1-p2@db { 1319 reg = <0xdb 0x1>; 1320 bits = <2 6>; 1321 }; 1322 1323 tsens_s2_p2: s2-p2@dc { 1324 reg = <0xdc 0x1>; 1325 bits = <0 6>; 1326 }; 1327 1328 tsens_s3_p2: s3-p2@dc { 1329 reg = <0xdc 0x2>; 1330 bits = <6 6>; 1331 }; 1332 1333 tsens_s4_p2: s4-p2@dd { 1334 reg = <0xdd 0x2>; 1335 bits = <4 6>; 1336 }; 1337 1338 tsens_s5_p2: s5-p2@de { 1339 reg = <0xde 0x2>; 1340 bits = <2 6>; 1341 }; 1342 1343 tsens_s6_p2: s6-p2@df { 1344 reg = <0xdf 0x1>; 1345 bits = <0 6>; 1346 }; 1347 1348 tsens_s7_p2: s7-p2@e0 { 1349 reg = <0xe0 0x1>; 1350 bits = <0 6>; 1351 }; 1352 1353 tsens_s8_p2: s8-p2@e0 { 1354 reg = <0xe0 0x2>; 1355 bits = <6 6>; 1356 }; 1357 1358 tsens_s9_p2: s9-p2@e1 { 1359 reg = <0xe1 0x2>; 1360 bits = <4 6>; 1361 }; 1362 1363 tsens_s10_p2: s10-p2@e2 { 1364 reg = <0xe2 0x2>; 1365 bits = <2 6>; 1366 }; 1367 1368 tsens_s5_p2_backup: s5-p2-backup@e3 { 1369 reg = <0xe3 0x2>; 1370 bits = <0 6>; 1371 }; 1372 1373 tsens_mode_backup: mode-backup@e3 { 1374 reg = <0xe3 0x1>; 1375 bits = <6 2>; 1376 }; 1377 1378 tsens_s6_p2_backup: s6-p2-backup@e4 { 1379 reg = <0xe4 0x1>; 1380 bits = <0 6>; 1381 }; 1382 1383 tsens_s7_p2_backup: s7-p2-backup@e4 { 1384 reg = <0xe4 0x2>; 1385 bits = <6 6>; 1386 }; 1387 1388 tsens_s8_p2_backup: s8-p2-backup@e5 { 1389 reg = <0xe5 0x2>; 1390 bits = <4 6>; 1391 }; 1392 1393 tsens_s9_p2_backup: s9-p2-backup@e6 { 1394 reg = <0xe6 0x2>; 1395 bits = <2 6>; 1396 }; 1397 1398 tsens_s10_p2_backup: s10-p2-backup@e7 { 1399 reg = <0xe7 0x1>; 1400 bits = <0 6>; 1401 }; 1402 1403 tsens_base1_backup: base1-backup@440 { 1404 reg = <0x440 0x1>; 1405 bits = <0 8>; 1406 }; 1407 1408 tsens_s0_p1_backup: s0-p1-backup@441 { 1409 reg = <0x441 0x1>; 1410 bits = <0 6>; 1411 }; 1412 1413 tsens_s1_p1_backup: s1-p1-backup@442 { 1414 reg = <0x441 0x2>; 1415 bits = <6 6>; 1416 }; 1417 1418 tsens_s2_p1_backup: s2-p1-backup@442 { 1419 reg = <0x442 0x2>; 1420 bits = <4 6>; 1421 }; 1422 1423 tsens_s3_p1_backup: s3-p1-backup@443 { 1424 reg = <0x443 0x1>; 1425 bits = <2 6>; 1426 }; 1427 1428 tsens_s4_p1_backup: s4-p1-backup@444 { 1429 reg = <0x444 0x1>; 1430 bits = <0 6>; 1431 }; 1432 1433 tsens_s5_p1_backup: s5-p1-backup@444 { 1434 reg = <0x444 0x2>; 1435 bits = <6 6>; 1436 }; 1437 1438 tsens_s6_p1_backup: s6-p1-backup@445 { 1439 reg = <0x445 0x2>; 1440 bits = <4 6>; 1441 }; 1442 1443 tsens_s7_p1_backup: s7-p1-backup@446 { 1444 reg = <0x446 0x1>; 1445 bits = <2 6>; 1446 }; 1447 1448 tsens_use_backup: use-backup@447 { 1449 reg = <0x447 0x1>; 1450 bits = <5 3>; 1451 }; 1452 1453 tsens_s8_p1_backup: s8-p1-backup@448 { 1454 reg = <0x448 0x1>; 1455 bits = <0 6>; 1456 }; 1457 1458 tsens_s9_p1_backup: s9-p1-backup@448 { 1459 reg = <0x448 0x2>; 1460 bits = <6 6>; 1461 }; 1462 1463 tsens_s10_p1_backup: s10-p1-backup@449 { 1464 reg = <0x449 0x2>; 1465 bits = <4 6>; 1466 }; 1467 1468 tsens_base2_backup: base2-backup@44a { 1469 reg = <0x44a 0x2>; 1470 bits = <2 8>; 1471 }; 1472 1473 tsens_s0_p2_backup: s0-p2-backup@44b { 1474 reg = <0x44b 0x3>; 1475 bits = <2 6>; 1476 }; 1477 1478 tsens_s1_p2_backup: s1-p2-backup@44c { 1479 reg = <0x44c 0x1>; 1480 bits = <0 6>; 1481 }; 1482 1483 tsens_s2_p2_backup: s2-p2-backup@44c { 1484 reg = <0x44c 0x2>; 1485 bits = <6 6>; 1486 }; 1487 1488 tsens_s3_p2_backup: s3-p2-backup@44d { 1489 reg = <0x44d 0x2>; 1490 bits = <4 6>; 1491 }; 1492 1493 tsens_s4_p2_backup: s4-p2-backup@44e { 1494 reg = <0x44e 0x1>; 1495 bits = <2 6>; 1496 }; 1497 }; 1498 1499 spmi_bus: spmi@fc4cf000 { 1500 compatible = "qcom,spmi-pmic-arb"; 1501 reg-names = "core", "intr", "cnfg"; 1502 reg = <0xfc4cf000 0x1000>, 1503 <0xfc4cb000 0x1000>, 1504 <0xfc4ca000 0x1000>; 1505 interrupt-names = "periph_irq"; 1506 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>; 1507 qcom,ee = <0>; 1508 qcom,channel = <0>; 1509 #address-cells = <2>; 1510 #size-cells = <0>; 1511 interrupt-controller; 1512 #interrupt-cells = <4>; 1513 }; 1514 1515 bam_dmux_dma: dma-controller@fc834000 { 1516 compatible = "qcom,bam-v1.4.0"; 1517 reg = <0xfc834000 0x7000>; 1518 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 1519 #dma-cells = <1>; 1520 qcom,ee = <0>; 1521 1522 num-channels = <6>; 1523 qcom,num-ees = <1>; 1524 qcom,powered-remotely; 1525 }; 1526 1527 remoteproc_mss: remoteproc@fc880000 { 1528 compatible = "qcom,msm8974-mss-pil"; 1529 reg = <0xfc880000 0x100>, <0xfc820000 0x020>; 1530 reg-names = "qdsp6", "rmb"; 1531 1532 interrupts-extended = <&intc GIC_SPI 24 IRQ_TYPE_EDGE_RISING>, 1533 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 1534 <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 1535 <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 1536 <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 1537 interrupt-names = "wdog", "fatal", "ready", "handover", "stop-ack"; 1538 1539 clocks = <&gcc GCC_MSS_Q6_BIMC_AXI_CLK>, 1540 <&gcc GCC_MSS_CFG_AHB_CLK>, 1541 <&gcc GCC_BOOT_ROM_AHB_CLK>, 1542 <&xo_board>; 1543 clock-names = "iface", "bus", "mem", "xo"; 1544 1545 resets = <&gcc GCC_MSS_RESTART>; 1546 reset-names = "mss_restart"; 1547 1548 qcom,halt-regs = <&tcsr_mutex 0x1180 0x1200 0x1280>; 1549 1550 qcom,smem-states = <&modem_smp2p_out 0>; 1551 qcom,smem-state-names = "stop"; 1552 1553 status = "disabled"; 1554 1555 mba { 1556 memory-region = <&mba_region>; 1557 }; 1558 1559 mpss { 1560 memory-region = <&mpss_region>; 1561 }; 1562 1563 bam_dmux: bam-dmux { 1564 compatible = "qcom,bam-dmux"; 1565 1566 interrupt-parent = <&modem_smsm>; 1567 interrupts = <1 IRQ_TYPE_EDGE_BOTH>, <11 IRQ_TYPE_EDGE_BOTH>; 1568 interrupt-names = "pc", "pc-ack"; 1569 1570 qcom,smem-states = <&apps_smsm 1>, <&apps_smsm 11>; 1571 qcom,smem-state-names = "pc", "pc-ack"; 1572 1573 dmas = <&bam_dmux_dma 4>, <&bam_dmux_dma 5>; 1574 dma-names = "tx", "rx"; 1575 }; 1576 1577 smd-edge { 1578 interrupts = <GIC_SPI 25 IRQ_TYPE_EDGE_RISING>; 1579 1580 mboxes = <&apcs 12>; 1581 qcom,smd-edge = <0>; 1582 1583 label = "modem"; 1584 }; 1585 }; 1586 1587 tcsr_mutex: hwlock@fd484000 { 1588 compatible = "qcom,msm8974-tcsr-mutex", "qcom,tcsr-mutex", "syscon"; 1589 reg = <0xfd484000 0x2000>; 1590 #hwlock-cells = <1>; 1591 }; 1592 1593 tcsr: syscon@fd4a0000 { 1594 compatible = "qcom,tcsr-msm8974", "syscon"; 1595 reg = <0xfd4a0000 0x10000>; 1596 }; 1597 1598 tlmm: pinctrl@fd510000 { 1599 compatible = "qcom,msm8974-pinctrl"; 1600 reg = <0xfd510000 0x4000>; 1601 gpio-controller; 1602 gpio-ranges = <&tlmm 0 0 146>; 1603 #gpio-cells = <2>; 1604 interrupt-controller; 1605 #interrupt-cells = <2>; 1606 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 1607 1608 sdc1_off: sdc1-off-state { 1609 clk-pins { 1610 pins = "sdc1_clk"; 1611 bias-disable; 1612 drive-strength = <2>; 1613 }; 1614 1615 cmd-pins { 1616 pins = "sdc1_cmd"; 1617 bias-pull-up; 1618 drive-strength = <2>; 1619 }; 1620 1621 data-pins { 1622 pins = "sdc1_data"; 1623 bias-pull-up; 1624 drive-strength = <2>; 1625 }; 1626 }; 1627 1628 sdc2_off: sdc2-off-state { 1629 clk-pins { 1630 pins = "sdc2_clk"; 1631 bias-disable; 1632 drive-strength = <2>; 1633 }; 1634 1635 cmd-pins { 1636 pins = "sdc2_cmd"; 1637 bias-pull-up; 1638 drive-strength = <2>; 1639 }; 1640 1641 data-pins { 1642 pins = "sdc2_data"; 1643 bias-pull-up; 1644 drive-strength = <2>; 1645 }; 1646 }; 1647 1648 blsp1_uart2_default: blsp1-uart2-default-state { 1649 rx-pins { 1650 pins = "gpio5"; 1651 function = "blsp_uart2"; 1652 drive-strength = <2>; 1653 bias-pull-up; 1654 }; 1655 1656 tx-pins { 1657 pins = "gpio4"; 1658 function = "blsp_uart2"; 1659 drive-strength = <4>; 1660 bias-disable; 1661 }; 1662 }; 1663 1664 blsp2_uart1_default: blsp2-uart1-default-state { 1665 tx-rts-pins { 1666 pins = "gpio41", "gpio44"; 1667 function = "blsp_uart7"; 1668 drive-strength = <2>; 1669 bias-disable; 1670 }; 1671 1672 rx-cts-pins { 1673 pins = "gpio42", "gpio43"; 1674 function = "blsp_uart7"; 1675 drive-strength = <2>; 1676 bias-pull-up; 1677 }; 1678 }; 1679 1680 blsp2_uart1_sleep: blsp2-uart1-sleep-state { 1681 pins = "gpio41", "gpio42", "gpio43", "gpio44"; 1682 function = "gpio"; 1683 drive-strength = <2>; 1684 bias-pull-down; 1685 }; 1686 1687 blsp2_uart4_default: blsp2-uart4-default-state { 1688 tx-rts-pins { 1689 pins = "gpio53", "gpio56"; 1690 function = "blsp_uart10"; 1691 drive-strength = <2>; 1692 bias-disable; 1693 }; 1694 1695 rx-cts-pins { 1696 pins = "gpio54", "gpio55"; 1697 function = "blsp_uart10"; 1698 drive-strength = <2>; 1699 bias-pull-up; 1700 }; 1701 }; 1702 1703 blsp1_i2c1_default: blsp1-i2c1-default-state { 1704 pins = "gpio2", "gpio3"; 1705 function = "blsp_i2c1"; 1706 drive-strength = <2>; 1707 bias-disable; 1708 }; 1709 1710 blsp1_i2c1_sleep: blsp1-i2c1-sleep-state { 1711 pins = "gpio2", "gpio3"; 1712 function = "blsp_i2c1"; 1713 drive-strength = <2>; 1714 bias-pull-up; 1715 }; 1716 1717 blsp1_i2c2_default: blsp1-i2c2-default-state { 1718 pins = "gpio6", "gpio7"; 1719 function = "blsp_i2c2"; 1720 drive-strength = <2>; 1721 bias-disable; 1722 }; 1723 1724 blsp1_i2c2_sleep: blsp1-i2c2-sleep-state { 1725 pins = "gpio6", "gpio7"; 1726 function = "blsp_i2c2"; 1727 drive-strength = <2>; 1728 bias-pull-up; 1729 }; 1730 1731 blsp1_i2c3_default: blsp1-i2c3-default-state { 1732 pins = "gpio10", "gpio11"; 1733 function = "blsp_i2c3"; 1734 drive-strength = <2>; 1735 bias-disable; 1736 }; 1737 1738 blsp1_i2c3_sleep: blsp1-i2c3-sleep-state { 1739 pins = "gpio10", "gpio11"; 1740 function = "blsp_i2c3"; 1741 drive-strength = <2>; 1742 bias-pull-up; 1743 }; 1744 1745 /* BLSP1_I2C4 info is missing */ 1746 1747 /* BLSP1_I2C5 info is missing */ 1748 1749 blsp1_i2c6_default: blsp1-i2c6-default-state { 1750 pins = "gpio29", "gpio30"; 1751 function = "blsp_i2c6"; 1752 drive-strength = <2>; 1753 bias-disable; 1754 }; 1755 1756 blsp1_i2c6_sleep: blsp1-i2c6-sleep-state { 1757 pins = "gpio29", "gpio30"; 1758 function = "blsp_i2c6"; 1759 drive-strength = <2>; 1760 bias-pull-up; 1761 }; 1762 /* 6 interfaces per QUP, BLSP2 indexes are numbered (n)+6 */ 1763 1764 /* BLSP2_I2C1 info is missing */ 1765 1766 blsp2_i2c2_default: blsp2-i2c2-default-state { 1767 pins = "gpio47", "gpio48"; 1768 function = "blsp_i2c8"; 1769 drive-strength = <2>; 1770 bias-disable; 1771 }; 1772 1773 blsp2_i2c2_sleep: blsp2-i2c2-sleep-state { 1774 pins = "gpio47", "gpio48"; 1775 function = "blsp_i2c8"; 1776 drive-strength = <2>; 1777 bias-pull-up; 1778 }; 1779 1780 /* BLSP2_I2C3 info is missing */ 1781 1782 /* BLSP2_I2C4 info is missing */ 1783 1784 blsp2_i2c5_default: blsp2-i2c5-default-state { 1785 pins = "gpio83", "gpio84"; 1786 function = "blsp_i2c11"; 1787 drive-strength = <2>; 1788 bias-disable; 1789 }; 1790 1791 blsp2_i2c5_sleep: blsp2-i2c5-sleep-state { 1792 pins = "gpio83", "gpio84"; 1793 function = "blsp_i2c11"; 1794 drive-strength = <2>; 1795 bias-pull-up; 1796 }; 1797 1798 blsp2_i2c6_default: blsp2-i2c6-default-state { 1799 pins = "gpio87", "gpio88"; 1800 function = "blsp_i2c12"; 1801 drive-strength = <2>; 1802 bias-disable; 1803 }; 1804 1805 blsp2_i2c6_sleep: blsp2-i2c6-sleep-state { 1806 pins = "gpio87", "gpio88"; 1807 function = "blsp_i2c12"; 1808 drive-strength = <2>; 1809 bias-pull-up; 1810 }; 1811 1812 cci_default: cci-default-state { 1813 cci_i2c0_default: cci-i2c0-default-pins { 1814 pins = "gpio19", "gpio20"; 1815 function = "cci_i2c0"; 1816 drive-strength = <2>; 1817 bias-disable; 1818 }; 1819 1820 cci_i2c1_default: cci-i2c1-default-pins { 1821 pins = "gpio21", "gpio22"; 1822 function = "cci_i2c1"; 1823 drive-strength = <2>; 1824 bias-disable; 1825 }; 1826 }; 1827 1828 cci_sleep: cci-sleep-state { 1829 cci_i2c0_sleep: cci-i2c0-sleep-pins { 1830 pins = "gpio19", "gpio20"; 1831 function = "gpio"; 1832 drive-strength = <2>; 1833 bias-disable; 1834 }; 1835 1836 cci_i2c1_sleep: cci-i2c1-sleep-pins { 1837 pins = "gpio21", "gpio22"; 1838 function = "gpio"; 1839 drive-strength = <2>; 1840 bias-disable; 1841 }; 1842 }; 1843 1844 spi8_default: spi8_default-state { 1845 mosi-pins { 1846 pins = "gpio45"; 1847 function = "blsp_spi8"; 1848 }; 1849 miso-pins { 1850 pins = "gpio46"; 1851 function = "blsp_spi8"; 1852 }; 1853 cs-pins { 1854 pins = "gpio47"; 1855 function = "blsp_spi8"; 1856 }; 1857 clk-pins { 1858 pins = "gpio48"; 1859 function = "blsp_spi8"; 1860 }; 1861 }; 1862 }; 1863 1864 mmcc: clock-controller@fd8c0000 { 1865 compatible = "qcom,mmcc-msm8974"; 1866 #clock-cells = <1>; 1867 #reset-cells = <1>; 1868 #power-domain-cells = <1>; 1869 reg = <0xfd8c0000 0x6000>; 1870 clocks = <&xo_board>, 1871 <&gcc GCC_MMSS_GPLL0_CLK_SRC>, 1872 <&gcc GPLL0_VOTE>, 1873 <&gcc GPLL1_VOTE>, 1874 <&rpmcc RPM_SMD_GFX3D_CLK_SRC>, 1875 <&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>, 1876 <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>, 1877 <&mdss_dsi1_phy DSI_PIXEL_PLL_CLK>, 1878 <&mdss_dsi1_phy DSI_BYTE_PLL_CLK>, 1879 <0>, 1880 <0>, 1881 <0>; 1882 clock-names = "xo", 1883 "mmss_gpll0_vote", 1884 "gpll0_vote", 1885 "gpll1_vote", 1886 "gfx3d_clk_src", 1887 "dsi0pll", 1888 "dsi0pllbyte", 1889 "dsi1pll", 1890 "dsi1pllbyte", 1891 "hdmipll", 1892 "edp_link_clk", 1893 "edp_vco_div"; 1894 }; 1895 1896 mdss: display-subsystem@fd900000 { 1897 compatible = "qcom,mdss"; 1898 reg = <0xfd900000 0x100>, <0xfd924000 0x1000>; 1899 reg-names = "mdss_phys", "vbif_phys"; 1900 1901 power-domains = <&mmcc MDSS_GDSC>; 1902 1903 clocks = <&mmcc MDSS_AHB_CLK>, 1904 <&mmcc MDSS_AXI_CLK>, 1905 <&mmcc MDSS_VSYNC_CLK>; 1906 clock-names = "iface", "bus", "vsync"; 1907 1908 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 1909 1910 interrupt-controller; 1911 #interrupt-cells = <1>; 1912 1913 status = "disabled"; 1914 1915 #address-cells = <1>; 1916 #size-cells = <1>; 1917 ranges; 1918 1919 mdp: display-controller@fd900000 { 1920 compatible = "qcom,msm8974-mdp5", "qcom,mdp5"; 1921 reg = <0xfd900100 0x22000>; 1922 reg-names = "mdp_phys"; 1923 1924 interrupt-parent = <&mdss>; 1925 interrupts = <0>; 1926 1927 clocks = <&mmcc MDSS_AHB_CLK>, 1928 <&mmcc MDSS_AXI_CLK>, 1929 <&mmcc MDSS_MDP_CLK>, 1930 <&mmcc MDSS_VSYNC_CLK>; 1931 clock-names = "iface", "bus", "core", "vsync"; 1932 1933 interconnects = <&mmssnoc MNOC_MAS_MDP_PORT0 &bimc BIMC_SLV_EBI_CH0>; 1934 interconnect-names = "mdp0-mem"; 1935 1936 ports { 1937 #address-cells = <1>; 1938 #size-cells = <0>; 1939 1940 port@0 { 1941 reg = <0>; 1942 mdp5_intf1_out: endpoint { 1943 remote-endpoint = <&mdss_dsi0_in>; 1944 }; 1945 }; 1946 1947 port@1 { 1948 reg = <1>; 1949 mdp5_intf2_out: endpoint { 1950 remote-endpoint = <&mdss_dsi1_in>; 1951 }; 1952 }; 1953 }; 1954 }; 1955 1956 mdss_dsi0: dsi@fd922800 { 1957 compatible = "qcom,msm8974-dsi-ctrl", 1958 "qcom,mdss-dsi-ctrl"; 1959 reg = <0xfd922800 0x1f8>; 1960 reg-names = "dsi_ctrl"; 1961 1962 interrupt-parent = <&mdss>; 1963 interrupts = <4>; 1964 1965 assigned-clocks = <&mmcc BYTE0_CLK_SRC>, 1966 <&mmcc PCLK0_CLK_SRC>; 1967 assigned-clock-parents = <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>, 1968 <&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>; 1969 1970 clocks = <&mmcc MDSS_MDP_CLK>, 1971 <&mmcc MDSS_AHB_CLK>, 1972 <&mmcc MDSS_AXI_CLK>, 1973 <&mmcc MDSS_BYTE0_CLK>, 1974 <&mmcc MDSS_PCLK0_CLK>, 1975 <&mmcc MDSS_ESC0_CLK>, 1976 <&mmcc MMSS_MISC_AHB_CLK>; 1977 clock-names = "mdp_core", 1978 "iface", 1979 "bus", 1980 "byte", 1981 "pixel", 1982 "core", 1983 "core_mmss"; 1984 1985 phys = <&mdss_dsi0_phy>; 1986 1987 status = "disabled"; 1988 1989 #address-cells = <1>; 1990 #size-cells = <0>; 1991 1992 ports { 1993 #address-cells = <1>; 1994 #size-cells = <0>; 1995 1996 port@0 { 1997 reg = <0>; 1998 mdss_dsi0_in: endpoint { 1999 remote-endpoint = <&mdp5_intf1_out>; 2000 }; 2001 }; 2002 2003 port@1 { 2004 reg = <1>; 2005 mdss_dsi0_out: endpoint { 2006 }; 2007 }; 2008 }; 2009 }; 2010 2011 mdss_dsi0_phy: phy@fd922a00 { 2012 compatible = "qcom,dsi-phy-28nm-hpm"; 2013 reg = <0xfd922a00 0xd4>, 2014 <0xfd922b00 0x280>, 2015 <0xfd922d80 0x30>; 2016 reg-names = "dsi_pll", 2017 "dsi_phy", 2018 "dsi_phy_regulator"; 2019 2020 #clock-cells = <1>; 2021 #phy-cells = <0>; 2022 2023 clocks = <&mmcc MDSS_AHB_CLK>, <&xo_board>; 2024 clock-names = "iface", "ref"; 2025 2026 status = "disabled"; 2027 }; 2028 2029 mdss_dsi1: dsi@fd922e00 { 2030 compatible = "qcom,msm8974-dsi-ctrl", 2031 "qcom,mdss-dsi-ctrl"; 2032 reg = <0xfd922e00 0x1f8>; 2033 reg-names = "dsi_ctrl"; 2034 2035 interrupt-parent = <&mdss>; 2036 interrupts = <4>; 2037 2038 assigned-clocks = <&mmcc BYTE1_CLK_SRC>, 2039 <&mmcc PCLK1_CLK_SRC>; 2040 assigned-clock-parents = <&mdss_dsi1_phy DSI_BYTE_PLL_CLK>, 2041 <&mdss_dsi1_phy DSI_PIXEL_PLL_CLK>; 2042 2043 clocks = <&mmcc MDSS_MDP_CLK>, 2044 <&mmcc MDSS_AHB_CLK>, 2045 <&mmcc MDSS_AXI_CLK>, 2046 <&mmcc MDSS_BYTE1_CLK>, 2047 <&mmcc MDSS_PCLK1_CLK>, 2048 <&mmcc MDSS_ESC1_CLK>, 2049 <&mmcc MMSS_MISC_AHB_CLK>; 2050 clock-names = "mdp_core", 2051 "iface", 2052 "bus", 2053 "byte", 2054 "pixel", 2055 "core", 2056 "core_mmss"; 2057 2058 phys = <&mdss_dsi1_phy>; 2059 2060 status = "disabled"; 2061 2062 #address-cells = <1>; 2063 #size-cells = <0>; 2064 2065 ports { 2066 #address-cells = <1>; 2067 #size-cells = <0>; 2068 2069 port@0 { 2070 reg = <0>; 2071 mdss_dsi1_in: endpoint { 2072 remote-endpoint = <&mdp5_intf2_out>; 2073 }; 2074 }; 2075 2076 port@1 { 2077 reg = <1>; 2078 mdss_dsi1_out: endpoint { 2079 }; 2080 }; 2081 }; 2082 }; 2083 2084 mdss_dsi1_phy: phy@fd923000 { 2085 compatible = "qcom,dsi-phy-28nm-hpm"; 2086 reg = <0xfd923000 0xd4>, 2087 <0xfd923100 0x280>, 2088 <0xfd923380 0x30>; 2089 reg-names = "dsi_pll", 2090 "dsi_phy", 2091 "dsi_phy_regulator"; 2092 2093 #clock-cells = <1>; 2094 #phy-cells = <0>; 2095 2096 clocks = <&mmcc MDSS_AHB_CLK>, <&xo_board>; 2097 clock-names = "iface", "ref"; 2098 2099 status = "disabled"; 2100 }; 2101 }; 2102 2103 cci: cci@fda0c000 { 2104 compatible = "qcom,msm8974-cci"; 2105 #address-cells = <1>; 2106 #size-cells = <0>; 2107 reg = <0xfda0c000 0x1000>; 2108 interrupts = <GIC_SPI 50 IRQ_TYPE_EDGE_RISING>; 2109 clocks = <&mmcc CAMSS_TOP_AHB_CLK>, 2110 <&mmcc CAMSS_CCI_CCI_AHB_CLK>, 2111 <&mmcc CAMSS_CCI_CCI_CLK>; 2112 clock-names = "camss_top_ahb", 2113 "cci_ahb", 2114 "cci"; 2115 2116 pinctrl-names = "default", "sleep"; 2117 pinctrl-0 = <&cci_default>; 2118 pinctrl-1 = <&cci_sleep>; 2119 2120 status = "disabled"; 2121 2122 cci_i2c0: i2c-bus@0 { 2123 reg = <0>; 2124 clock-frequency = <100000>; 2125 #address-cells = <1>; 2126 #size-cells = <0>; 2127 }; 2128 2129 cci_i2c1: i2c-bus@1 { 2130 reg = <1>; 2131 clock-frequency = <100000>; 2132 #address-cells = <1>; 2133 #size-cells = <0>; 2134 }; 2135 }; 2136 2137 gpu: gpu@fdb00000 { 2138 compatible = "qcom,adreno-330.1", "qcom,adreno"; 2139 reg = <0xfdb00000 0x10000>; 2140 reg-names = "kgsl_3d0_reg_memory"; 2141 2142 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 2143 interrupt-names = "kgsl_3d0_irq"; 2144 2145 clocks = <&mmcc OXILI_GFX3D_CLK>, 2146 <&mmcc OXILICX_AHB_CLK>, 2147 <&mmcc OXILICX_AXI_CLK>; 2148 clock-names = "core", "iface", "mem_iface"; 2149 2150 sram = <&gmu_sram>; 2151 power-domains = <&mmcc OXILICX_GDSC>; 2152 operating-points-v2 = <&gpu_opp_table>; 2153 2154 interconnects = <&mmssnoc MNOC_MAS_GRAPHICS_3D &bimc BIMC_SLV_EBI_CH0>, 2155 <&ocmemnoc OCMEM_VNOC_MAS_GFX3D &ocmemnoc OCMEM_SLV_OCMEM>; 2156 interconnect-names = "gfx-mem", "ocmem"; 2157 2158 // iommus = <&gpu_iommu 0>; 2159 2160 status = "disabled"; 2161 2162 gpu_opp_table: opp-table { 2163 compatible = "operating-points-v2"; 2164 2165 opp-320000000 { 2166 opp-hz = /bits/ 64 <320000000>; 2167 }; 2168 2169 opp-200000000 { 2170 opp-hz = /bits/ 64 <200000000>; 2171 }; 2172 2173 opp-27000000 { 2174 opp-hz = /bits/ 64 <27000000>; 2175 }; 2176 }; 2177 }; 2178 2179 sram@fdd00000 { 2180 compatible = "qcom,msm8974-ocmem"; 2181 reg = <0xfdd00000 0x2000>, 2182 <0xfec00000 0x180000>; 2183 reg-names = "ctrl", "mem"; 2184 ranges = <0 0xfec00000 0x180000>; 2185 clocks = <&rpmcc RPM_SMD_OCMEMGX_CLK>, 2186 <&mmcc OCMEMCX_OCMEMNOC_CLK>; 2187 clock-names = "core", "iface"; 2188 2189 #address-cells = <1>; 2190 #size-cells = <1>; 2191 2192 gmu_sram: gmu-sram@0 { 2193 reg = <0x0 0x100000>; 2194 }; 2195 }; 2196 2197 remoteproc_adsp: remoteproc@fe200000 { 2198 compatible = "qcom,msm8974-adsp-pil"; 2199 reg = <0xfe200000 0x100>; 2200 2201 interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>, 2202 <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 2203 <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 2204 <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 2205 <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 2206 interrupt-names = "wdog", "fatal", "ready", "handover", "stop-ack"; 2207 2208 clocks = <&xo_board>; 2209 clock-names = "xo"; 2210 2211 memory-region = <&adsp_region>; 2212 2213 qcom,smem-states = <&adsp_smp2p_out 0>; 2214 qcom,smem-state-names = "stop"; 2215 2216 status = "disabled"; 2217 2218 smd-edge { 2219 interrupts = <GIC_SPI 156 IRQ_TYPE_EDGE_RISING>; 2220 2221 mboxes = <&apcs 8>; 2222 qcom,smd-edge = <1>; 2223 label = "lpass"; 2224 }; 2225 }; 2226 2227 imem: sram@fe805000 { 2228 compatible = "qcom,msm8974-imem", "syscon", "simple-mfd"; 2229 reg = <0xfe805000 0x1000>; 2230 2231 reboot-mode { 2232 compatible = "syscon-reboot-mode"; 2233 offset = <0x65c>; 2234 }; 2235 }; 2236 }; 2237 2238 thermal-zones { 2239 cpu0-thermal { 2240 polling-delay-passive = <250>; 2241 polling-delay = <1000>; 2242 2243 thermal-sensors = <&tsens 5>; 2244 2245 trips { 2246 cpu_alert0: trip0 { 2247 temperature = <75000>; 2248 hysteresis = <2000>; 2249 type = "passive"; 2250 }; 2251 cpu_crit0: trip1 { 2252 temperature = <110000>; 2253 hysteresis = <2000>; 2254 type = "critical"; 2255 }; 2256 }; 2257 }; 2258 2259 cpu1-thermal { 2260 polling-delay-passive = <250>; 2261 polling-delay = <1000>; 2262 2263 thermal-sensors = <&tsens 6>; 2264 2265 trips { 2266 cpu_alert1: trip0 { 2267 temperature = <75000>; 2268 hysteresis = <2000>; 2269 type = "passive"; 2270 }; 2271 cpu_crit1: trip1 { 2272 temperature = <110000>; 2273 hysteresis = <2000>; 2274 type = "critical"; 2275 }; 2276 }; 2277 }; 2278 2279 cpu2-thermal { 2280 polling-delay-passive = <250>; 2281 polling-delay = <1000>; 2282 2283 thermal-sensors = <&tsens 7>; 2284 2285 trips { 2286 cpu_alert2: trip0 { 2287 temperature = <75000>; 2288 hysteresis = <2000>; 2289 type = "passive"; 2290 }; 2291 cpu_crit2: trip1 { 2292 temperature = <110000>; 2293 hysteresis = <2000>; 2294 type = "critical"; 2295 }; 2296 }; 2297 }; 2298 2299 cpu3-thermal { 2300 polling-delay-passive = <250>; 2301 polling-delay = <1000>; 2302 2303 thermal-sensors = <&tsens 8>; 2304 2305 trips { 2306 cpu_alert3: trip0 { 2307 temperature = <75000>; 2308 hysteresis = <2000>; 2309 type = "passive"; 2310 }; 2311 cpu_crit3: trip1 { 2312 temperature = <110000>; 2313 hysteresis = <2000>; 2314 type = "critical"; 2315 }; 2316 }; 2317 }; 2318 2319 q6-dsp-thermal { 2320 polling-delay-passive = <250>; 2321 polling-delay = <1000>; 2322 2323 thermal-sensors = <&tsens 1>; 2324 2325 trips { 2326 q6_dsp_alert0: trip-point0 { 2327 temperature = <90000>; 2328 hysteresis = <2000>; 2329 type = "hot"; 2330 }; 2331 }; 2332 }; 2333 2334 modemtx-thermal { 2335 polling-delay-passive = <250>; 2336 polling-delay = <1000>; 2337 2338 thermal-sensors = <&tsens 2>; 2339 2340 trips { 2341 modemtx_alert0: trip-point0 { 2342 temperature = <90000>; 2343 hysteresis = <2000>; 2344 type = "hot"; 2345 }; 2346 }; 2347 }; 2348 2349 video-thermal { 2350 polling-delay-passive = <250>; 2351 polling-delay = <1000>; 2352 2353 thermal-sensors = <&tsens 3>; 2354 2355 trips { 2356 video_alert0: trip-point0 { 2357 temperature = <95000>; 2358 hysteresis = <2000>; 2359 type = "hot"; 2360 }; 2361 }; 2362 }; 2363 2364 wlan-thermal { 2365 polling-delay-passive = <250>; 2366 polling-delay = <1000>; 2367 2368 thermal-sensors = <&tsens 4>; 2369 2370 trips { 2371 wlan_alert0: trip-point0 { 2372 temperature = <105000>; 2373 hysteresis = <2000>; 2374 type = "hot"; 2375 }; 2376 }; 2377 }; 2378 2379 gpu-top-thermal { 2380 polling-delay-passive = <250>; 2381 polling-delay = <1000>; 2382 2383 thermal-sensors = <&tsens 9>; 2384 2385 trips { 2386 gpu1_alert0: trip-point0 { 2387 temperature = <90000>; 2388 hysteresis = <2000>; 2389 type = "hot"; 2390 }; 2391 }; 2392 }; 2393 2394 gpu-bottom-thermal { 2395 polling-delay-passive = <250>; 2396 polling-delay = <1000>; 2397 2398 thermal-sensors = <&tsens 10>; 2399 2400 trips { 2401 gpu2_alert0: trip-point0 { 2402 temperature = <90000>; 2403 hysteresis = <2000>; 2404 type = "hot"; 2405 }; 2406 }; 2407 }; 2408 }; 2409 2410 timer { 2411 compatible = "arm,armv7-timer"; 2412 interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 2413 <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 2414 <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 2415 <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 2416 clock-frequency = <19200000>; 2417 }; 2418};
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