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qcom-msm8226.dtsi
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linux-6.19.14/arch/arm/boot/dts/qcom/qcom-msm8226.dtsi
1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * Copyright (c) 2020, The Linux Foundation. All rights reserved. 4 */ 5 6/dts-v1/; 7 8#include <dt-bindings/interrupt-controller/arm-gic.h> 9#include <dt-bindings/clock/qcom,dsi-phy-28nm.h> 10#include <dt-bindings/clock/qcom,gcc-msm8974.h> 11#include <dt-bindings/clock/qcom,mmcc-msm8974.h> 12#include <dt-bindings/clock/qcom,rpmcc.h> 13#include <dt-bindings/gpio/gpio.h> 14#include <dt-bindings/power/qcom-rpmpd.h> 15#include <dt-bindings/reset/qcom,gcc-msm8974.h> 16#include <dt-bindings/thermal/thermal.h> 17 18/ { 19 #address-cells = <1>; 20 #size-cells = <1>; 21 interrupt-parent = <&intc>; 22 23 chosen { }; 24 25 clocks { 26 xo_board: xo_board { 27 compatible = "fixed-clock"; 28 #clock-cells = <0>; 29 clock-frequency = <19200000>; 30 }; 31 32 sleep_clk: sleep_clk { 33 compatible = "fixed-clock"; 34 #clock-cells = <0>; 35 clock-frequency = <32768>; 36 }; 37 }; 38 39 cpus { 40 #address-cells = <1>; 41 #size-cells = <0>; 42 43 cpu0: cpu@0 { 44 compatible = "arm,cortex-a7"; 45 enable-method = "qcom,msm8226-smp"; 46 device_type = "cpu"; 47 reg = <0>; 48 next-level-cache = <&l2>; 49 clocks = <&apcs>; 50 operating-points-v2 = <&cpu_opp_table>; 51 qcom,acc = <&acc0>; 52 qcom,saw = <&saw0>; 53 #cooling-cells = <2>; 54 }; 55 56 cpu1: cpu@1 { 57 compatible = "arm,cortex-a7"; 58 enable-method = "qcom,msm8226-smp"; 59 device_type = "cpu"; 60 reg = <1>; 61 next-level-cache = <&l2>; 62 clocks = <&apcs>; 63 operating-points-v2 = <&cpu_opp_table>; 64 qcom,acc = <&acc1>; 65 qcom,saw = <&saw1>; 66 #cooling-cells = <2>; 67 }; 68 69 cpu2: cpu@2 { 70 compatible = "arm,cortex-a7"; 71 enable-method = "qcom,msm8226-smp"; 72 device_type = "cpu"; 73 reg = <2>; 74 next-level-cache = <&l2>; 75 clocks = <&apcs>; 76 operating-points-v2 = <&cpu_opp_table>; 77 qcom,acc = <&acc2>; 78 qcom,saw = <&saw2>; 79 #cooling-cells = <2>; 80 }; 81 82 cpu3: cpu@3 { 83 compatible = "arm,cortex-a7"; 84 enable-method = "qcom,msm8226-smp"; 85 device_type = "cpu"; 86 reg = <3>; 87 next-level-cache = <&l2>; 88 clocks = <&apcs>; 89 operating-points-v2 = <&cpu_opp_table>; 90 qcom,acc = <&acc3>; 91 qcom,saw = <&saw3>; 92 #cooling-cells = <2>; 93 }; 94 95 l2: l2-cache { 96 compatible = "cache"; 97 cache-level = <2>; 98 cache-unified; 99 }; 100 }; 101 102 firmware { 103 scm { 104 compatible = "qcom,scm-msm8226", "qcom,scm"; 105 clocks = <&gcc GCC_CE1_CLK>, <&gcc GCC_CE1_AXI_CLK>, <&gcc GCC_CE1_AHB_CLK>; 106 clock-names = "core", "bus", "iface"; 107 }; 108 }; 109 110 memory@0 { 111 device_type = "memory"; 112 reg = <0x0 0x0>; 113 }; 114 115 cpu_opp_table: opp-table-cpu { 116 compatible = "operating-points-v2"; 117 opp-shared; 118 119 opp-300000000 { 120 opp-hz = /bits/ 64 <300000000>; 121 }; 122 123 opp-384000000 { 124 opp-hz = /bits/ 64 <384000000>; 125 }; 126 127 opp-600000000 { 128 opp-hz = /bits/ 64 <600000000>; 129 }; 130 131 opp-787200000 { 132 opp-hz = /bits/ 64 <787200000>; 133 }; 134 135 /* Higher CPU frequencies need speedbin support */ 136 }; 137 138 pmu { 139 compatible = "arm,cortex-a7-pmu"; 140 interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) | 141 IRQ_TYPE_LEVEL_HIGH)>; 142 }; 143 144 rpm: remoteproc { 145 compatible = "qcom,msm8226-rpm-proc", "qcom,rpm-proc"; 146 147 master-stats { 148 compatible = "qcom,rpm-master-stats"; 149 qcom,rpm-msg-ram = <&apss_master_stats>, 150 <&mpss_master_stats>, 151 <&lpss_master_stats>, 152 <&pronto_master_stats>; 153 qcom,master-names = "APSS", 154 "MPSS", 155 "LPSS", 156 "PRONTO"; 157 }; 158 159 smd-edge { 160 interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>; 161 mboxes = <&apcs 0>; 162 qcom,smd-edge = <15>; 163 164 rpm_requests: rpm-requests { 165 compatible = "qcom,rpm-msm8226", "qcom,smd-rpm"; 166 qcom,smd-channels = "rpm_requests"; 167 168 rpmcc: clock-controller { 169 compatible = "qcom,rpmcc-msm8226", "qcom,rpmcc"; 170 #clock-cells = <1>; 171 clocks = <&xo_board>; 172 clock-names = "xo"; 173 }; 174 175 rpmpd: power-controller { 176 compatible = "qcom,msm8226-rpmpd"; 177 #power-domain-cells = <1>; 178 operating-points-v2 = <&rpmpd_opp_table>; 179 180 rpmpd_opp_table: opp-table { 181 compatible = "operating-points-v2"; 182 183 rpmpd_opp_ret: opp1 { 184 opp-level = <1>; 185 }; 186 rpmpd_opp_svs_krait: opp2 { 187 opp-level = <2>; 188 }; 189 rpmpd_opp_svs_soc: opp3 { 190 opp-level = <3>; 191 }; 192 rpmpd_opp_nom: opp4 { 193 opp-level = <4>; 194 }; 195 rpmpd_opp_turbo: opp5 { 196 opp-level = <5>; 197 }; 198 rpmpd_opp_super_turbo: opp6 { 199 opp-level = <6>; 200 }; 201 }; 202 }; 203 }; 204 }; 205 }; 206 207 reserved-memory { 208 #address-cells = <1>; 209 #size-cells = <1>; 210 ranges; 211 212 smem_region: smem@3000000 { 213 reg = <0x3000000 0x100000>; 214 no-map; 215 }; 216 217 mpss_region: mpss@8000000 { 218 reg = <0x08000000 0x5100000>; 219 no-map; 220 status = "disabled"; 221 }; 222 223 mba_region: mba@d100000 { 224 reg = <0x0d100000 0x100000>; 225 no-map; 226 status = "disabled"; 227 }; 228 229 adsp_region: adsp@dc00000 { 230 reg = <0x0dc00000 0x1900000>; 231 no-map; 232 }; 233 }; 234 235 smem { 236 compatible = "qcom,smem"; 237 238 memory-region = <&smem_region>; 239 qcom,rpm-msg-ram = <&rpm_msg_ram>; 240 241 hwlocks = <&tcsr_mutex 3>; 242 }; 243 244 smp2p-adsp { 245 compatible = "qcom,smp2p"; 246 qcom,smem = <443>, <429>; 247 248 interrupt-parent = <&intc>; 249 interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>; 250 251 mboxes = <&apcs 10>; 252 253 qcom,local-pid = <0>; 254 qcom,remote-pid = <2>; 255 256 adsp_smp2p_out: master-kernel { 257 qcom,entry-name = "master-kernel"; 258 #qcom,smem-state-cells = <1>; 259 }; 260 261 adsp_smp2p_in: slave-kernel { 262 qcom,entry-name = "slave-kernel"; 263 264 interrupt-controller; 265 #interrupt-cells = <2>; 266 }; 267 }; 268 269 smp2p-modem { 270 compatible = "qcom,smp2p"; 271 qcom,smem = <435>, <428>; 272 273 interrupt-parent = <&intc>; 274 interrupts = <GIC_SPI 27 IRQ_TYPE_EDGE_RISING>; 275 276 mboxes = <&apcs 14>; 277 278 qcom,local-pid = <0>; 279 qcom,remote-pid = <1>; 280 281 modem_smp2p_out: master-kernel { 282 qcom,entry-name = "master-kernel"; 283 #qcom,smem-state-cells = <1>; 284 }; 285 286 modem_smp2p_in: slave-kernel { 287 qcom,entry-name = "slave-kernel"; 288 289 interrupt-controller; 290 #interrupt-cells = <2>; 291 }; 292 }; 293 294 smsm { 295 compatible = "qcom,smsm"; 296 #address-cells = <1>; 297 #size-cells = <0>; 298 299 mboxes = <0>, <&apcs 13>, <&apcs 9>, <&apcs 19>; 300 301 apps_smsm: apps@0 { 302 reg = <0>; 303 #qcom,smem-state-cells = <1>; 304 }; 305 306 modem_smsm: modem@1 { 307 reg = <1>; 308 interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>; 309 interrupt-controller; 310 #interrupt-cells = <2>; 311 }; 312 313 adsp_smsm: adsp@2 { 314 reg = <2>; 315 interrupts = <GIC_SPI 157 IRQ_TYPE_EDGE_RISING>; 316 interrupt-controller; 317 #interrupt-cells = <2>; 318 }; 319 320 wcnss_smsm: wcnss@7 { 321 reg = <7>; 322 interrupts = <GIC_SPI 144 IRQ_TYPE_EDGE_RISING>; 323 interrupt-controller; 324 #interrupt-cells = <2>; 325 }; 326 }; 327 328 soc: soc { 329 compatible = "simple-bus"; 330 #address-cells = <1>; 331 #size-cells = <1>; 332 ranges; 333 334 intc: interrupt-controller@f9000000 { 335 compatible = "qcom,msm-qgic2"; 336 reg = <0xf9000000 0x1000>, 337 <0xf9002000 0x1000>; 338 interrupt-controller; 339 #interrupt-cells = <3>; 340 }; 341 342 apcs: mailbox@f9011000 { 343 compatible = "qcom,msm8226-apcs-kpss-global", 344 "qcom,msm8916-apcs-kpss-global", "syscon"; 345 reg = <0xf9011000 0x1000>; 346 #mbox-cells = <1>; 347 clocks = <&a7pll>, <&gcc GPLL0_VOTE>; 348 clock-names = "pll", "aux"; 349 #clock-cells = <0>; 350 }; 351 352 a7pll: clock@f9016000 { 353 compatible = "qcom,msm8226-a7pll"; 354 reg = <0xf9016000 0x40>; 355 #clock-cells = <0>; 356 clocks = <&xo_board>; 357 clock-names = "xo"; 358 operating-points-v2 = <&a7pll_opp_table>; 359 360 a7pll_opp_table: opp-table { 361 compatible = "operating-points-v2"; 362 363 opp-768000000 { 364 opp-hz = /bits/ 64 <768000000>; 365 }; 366 367 opp-787200000 { 368 opp-hz = /bits/ 64 <787200000>; 369 }; 370 371 opp-998400000 { 372 opp-hz = /bits/ 64 <998400000>; 373 }; 374 375 opp-1094400000 { 376 opp-hz = /bits/ 64 <1094400000>; 377 }; 378 379 opp-1190400000 { 380 opp-hz = /bits/ 64 <1190400000>; 381 }; 382 383 opp-1305600000 { 384 opp-hz = /bits/ 64 <1305600000>; 385 }; 386 387 opp-1344000000 { 388 opp-hz = /bits/ 64 <1344000000>; 389 }; 390 391 opp-1401600000 { 392 opp-hz = /bits/ 64 <1401600000>; 393 }; 394 395 opp-1497600000 { 396 opp-hz = /bits/ 64 <1497600000>; 397 }; 398 399 opp-1593600000 { 400 opp-hz = /bits/ 64 <1593600000>; 401 }; 402 403 opp-1689600000 { 404 opp-hz = /bits/ 64 <1689600000>; 405 }; 406 407 opp-1785600000 { 408 opp-hz = /bits/ 64 <1785600000>; 409 }; 410 }; 411 }; 412 413 saw_l2: power-manager@f9012000 { 414 compatible = "qcom,msm8226-saw2-v2.1-l2", "qcom,saw2"; 415 reg = <0xf9012000 0x1000>; 416 }; 417 418 watchdog@f9017000 { 419 compatible = "qcom,apss-wdt-msm8226", "qcom,kpss-wdt"; 420 reg = <0xf9017000 0x1000>; 421 interrupts = <GIC_SPI 3 IRQ_TYPE_EDGE_RISING>, 422 <GIC_SPI 4 IRQ_TYPE_EDGE_RISING>; 423 clocks = <&sleep_clk>; 424 }; 425 426 timer@f9020000 { 427 compatible = "arm,armv7-timer-mem"; 428 reg = <0xf9020000 0x1000>; 429 #address-cells = <1>; 430 #size-cells = <1>; 431 ranges; 432 433 frame@f9021000 { 434 frame-number = <0>; 435 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 436 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 437 reg = <0xf9021000 0x1000>, 438 <0xf9022000 0x1000>; 439 }; 440 441 frame@f9023000 { 442 frame-number = <1>; 443 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 444 reg = <0xf9023000 0x1000>; 445 status = "disabled"; 446 }; 447 448 frame@f9024000 { 449 frame-number = <2>; 450 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 451 reg = <0xf9024000 0x1000>; 452 status = "disabled"; 453 }; 454 455 frame@f9025000 { 456 frame-number = <3>; 457 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 458 reg = <0xf9025000 0x1000>; 459 status = "disabled"; 460 }; 461 462 frame@f9026000 { 463 frame-number = <4>; 464 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 465 reg = <0xf9026000 0x1000>; 466 status = "disabled"; 467 }; 468 469 frame@f9027000 { 470 frame-number = <5>; 471 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 472 reg = <0xf9027000 0x1000>; 473 status = "disabled"; 474 }; 475 476 frame@f9028000 { 477 frame-number = <6>; 478 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 479 reg = <0xf9028000 0x1000>; 480 status = "disabled"; 481 }; 482 }; 483 484 acc0: power-manager@f9088000 { 485 compatible = "qcom,kpss-acc-v2"; 486 reg = <0xf9088000 0x1000>, <0xf9008000 0x1000>; 487 }; 488 489 saw0: power-manager@f9089000 { 490 compatible = "qcom,msm8226-saw2-v2.1-cpu", "qcom,saw2"; 491 reg = <0xf9089000 0x1000>; 492 }; 493 494 acc1: power-manager@f9098000 { 495 compatible = "qcom,kpss-acc-v2"; 496 reg = <0xf9098000 0x1000>, <0xf9008000 0x1000>; 497 }; 498 499 saw1: power-manager@f9099000 { 500 compatible = "qcom,msm8226-saw2-v2.1-cpu", "qcom,saw2"; 501 reg = <0xf9099000 0x1000>; 502 }; 503 504 acc2: power-manager@f90a8000 { 505 compatible = "qcom,kpss-acc-v2"; 506 reg = <0xf90a8000 0x1000>, <0xf9008000 0x1000>; 507 }; 508 509 saw2: power-manager@f90a9000 { 510 compatible = "qcom,msm8226-saw2-v2.1-cpu", "qcom,saw2"; 511 reg = <0xf90a9000 0x1000>; 512 }; 513 514 acc3: power-manager@f90b8000 { 515 compatible = "qcom,kpss-acc-v2"; 516 reg = <0xf90b8000 0x1000>, <0xf9008000 0x1000>; 517 }; 518 519 saw3: power-manager@f90b9000 { 520 compatible = "qcom,msm8226-saw2-v2.1-cpu", "qcom,saw2"; 521 reg = <0xf90b9000 0x1000>; 522 }; 523 524 sdhc_1: mmc@f9824900 { 525 compatible = "qcom,msm8226-sdhci", "qcom,sdhci-msm-v4"; 526 reg = <0xf9824900 0x11c>, <0xf9824000 0x800>; 527 reg-names = "hc", "core"; 528 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 529 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 530 interrupt-names = "hc_irq", "pwr_irq"; 531 clocks = <&gcc GCC_SDCC1_AHB_CLK>, 532 <&gcc GCC_SDCC1_APPS_CLK>, 533 <&rpmcc RPM_SMD_XO_CLK_SRC>; 534 clock-names = "iface", "core", "xo"; 535 pinctrl-names = "default"; 536 pinctrl-0 = <&sdhc1_default_state>; 537 status = "disabled"; 538 }; 539 540 sdhc_3: mmc@f9864900 { 541 compatible = "qcom,msm8226-sdhci", "qcom,sdhci-msm-v4"; 542 reg = <0xf9864900 0x11c>, <0xf9864000 0x800>; 543 reg-names = "hc", "core"; 544 interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>, 545 <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>; 546 interrupt-names = "hc_irq", "pwr_irq"; 547 clocks = <&gcc GCC_SDCC3_AHB_CLK>, 548 <&gcc GCC_SDCC3_APPS_CLK>, 549 <&rpmcc RPM_SMD_XO_CLK_SRC>; 550 clock-names = "iface", "core", "xo"; 551 pinctrl-names = "default"; 552 pinctrl-0 = <&sdhc3_default_state>; 553 status = "disabled"; 554 }; 555 556 sdhc_2: mmc@f98a4900 { 557 compatible = "qcom,msm8226-sdhci", "qcom,sdhci-msm-v4"; 558 reg = <0xf98a4900 0x11c>, <0xf98a4000 0x800>; 559 reg-names = "hc", "core"; 560 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 561 <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>; 562 interrupt-names = "hc_irq", "pwr_irq"; 563 clocks = <&gcc GCC_SDCC2_AHB_CLK>, 564 <&gcc GCC_SDCC2_APPS_CLK>, 565 <&rpmcc RPM_SMD_XO_CLK_SRC>; 566 clock-names = "iface", "core", "xo"; 567 pinctrl-names = "default"; 568 pinctrl-0 = <&sdhc2_default_state>; 569 status = "disabled"; 570 }; 571 572 blsp1_uart1: serial@f991d000 { 573 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 574 reg = <0xf991d000 0x1000>; 575 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; 576 clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; 577 clock-names = "core", "iface"; 578 status = "disabled"; 579 }; 580 581 blsp1_uart2: serial@f991e000 { 582 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 583 reg = <0xf991e000 0x1000>; 584 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 585 clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, 586 <&gcc GCC_BLSP1_AHB_CLK>; 587 clock-names = "core", 588 "iface"; 589 status = "disabled"; 590 }; 591 592 blsp1_uart3: serial@f991f000 { 593 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 594 reg = <0xf991f000 0x1000>; 595 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; 596 clocks = <&gcc GCC_BLSP1_UART3_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; 597 clock-names = "core", "iface"; 598 status = "disabled"; 599 }; 600 601 blsp1_uart4: serial@f9920000 { 602 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 603 reg = <0xf9920000 0x1000>; 604 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; 605 clocks = <&gcc GCC_BLSP1_UART4_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; 606 clock-names = "core", "iface"; 607 status = "disabled"; 608 }; 609 610 blsp1_i2c1: i2c@f9923000 { 611 compatible = "qcom,i2c-qup-v2.1.1"; 612 reg = <0xf9923000 0x1000>; 613 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 614 clocks = <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; 615 clock-names = "core", "iface"; 616 pinctrl-names = "default"; 617 pinctrl-0 = <&blsp1_i2c1_pins>; 618 #address-cells = <1>; 619 #size-cells = <0>; 620 status = "disabled"; 621 }; 622 623 blsp1_i2c2: i2c@f9924000 { 624 compatible = "qcom,i2c-qup-v2.1.1"; 625 reg = <0xf9924000 0x1000>; 626 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 627 clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; 628 clock-names = "core", "iface"; 629 pinctrl-names = "default"; 630 pinctrl-0 = <&blsp1_i2c2_pins>; 631 #address-cells = <1>; 632 #size-cells = <0>; 633 status = "disabled"; 634 }; 635 636 blsp1_i2c3: i2c@f9925000 { 637 compatible = "qcom,i2c-qup-v2.1.1"; 638 reg = <0xf9925000 0x1000>; 639 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 640 clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; 641 clock-names = "core", "iface"; 642 pinctrl-names = "default"; 643 pinctrl-0 = <&blsp1_i2c3_pins>; 644 #address-cells = <1>; 645 #size-cells = <0>; 646 status = "disabled"; 647 }; 648 649 blsp1_i2c4: i2c@f9926000 { 650 compatible = "qcom,i2c-qup-v2.1.1"; 651 reg = <0xf9926000 0x1000>; 652 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 653 clocks = <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; 654 clock-names = "core", "iface"; 655 pinctrl-names = "default"; 656 pinctrl-0 = <&blsp1_i2c4_pins>; 657 #address-cells = <1>; 658 #size-cells = <0>; 659 status = "disabled"; 660 }; 661 662 blsp1_i2c5: i2c@f9927000 { 663 compatible = "qcom,i2c-qup-v2.1.1"; 664 reg = <0xf9927000 0x1000>; 665 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; 666 clocks = <&gcc GCC_BLSP1_QUP5_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; 667 clock-names = "core", "iface"; 668 pinctrl-names = "default"; 669 pinctrl-0 = <&blsp1_i2c5_pins>; 670 #address-cells = <1>; 671 #size-cells = <0>; 672 status = "disabled"; 673 }; 674 675 blsp1_i2c6: i2c@f9928000 { 676 compatible = "qcom,i2c-qup-v2.1.1"; 677 reg = <0xf9928000 0x1000>; 678 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; 679 clocks = <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>, 680 <&gcc GCC_BLSP1_AHB_CLK>; 681 clock-names = "core", 682 "iface"; 683 pinctrl-0 = <&blsp1_i2c6_pins>; 684 pinctrl-names = "default"; 685 #address-cells = <1>; 686 #size-cells = <0>; 687 status = "disabled"; 688 }; 689 690 usb: usb@f9a55000 { 691 compatible = "qcom,ci-hdrc"; 692 reg = <0xf9a55000 0x200>, 693 <0xf9a55200 0x200>; 694 interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>; 695 clocks = <&gcc GCC_USB_HS_AHB_CLK>, 696 <&gcc GCC_USB_HS_SYSTEM_CLK>; 697 clock-names = "iface", "core"; 698 assigned-clocks = <&gcc GCC_USB_HS_SYSTEM_CLK>; 699 assigned-clock-rates = <75000000>; 700 resets = <&gcc GCC_USB_HS_BCR>; 701 reset-names = "core"; 702 phy_type = "ulpi"; 703 dr_mode = "otg"; 704 hnp-disable; 705 srp-disable; 706 adp-disable; 707 ahb-burst-config = <0>; 708 phy-names = "usb-phy"; 709 phys = <&usb_hs_phy>; 710 status = "disabled"; 711 #reset-cells = <1>; 712 713 ulpi { 714 usb_hs_phy: phy { 715 compatible = "qcom,usb-hs-phy-msm8226", 716 "qcom,usb-hs-phy"; 717 #phy-cells = <0>; 718 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, 719 <&gcc GCC_USB2A_PHY_SLEEP_CLK>; 720 clock-names = "ref", "sleep"; 721 resets = <&gcc GCC_USB2A_PHY_BCR>, <&usb 0>; 722 reset-names = "phy", "por"; 723 qcom,init-seq = /bits/ 8 <0x0 0x44 724 0x1 0x68 0x2 0x24 0x3 0x13>; 725 }; 726 }; 727 }; 728 729 rng@f9bff000 { 730 compatible = "qcom,prng"; 731 reg = <0xf9bff000 0x200>; 732 clocks = <&gcc GCC_PRNG_AHB_CLK>; 733 clock-names = "core"; 734 }; 735 736 sram@fc190000 { 737 compatible = "qcom,msm8226-rpm-stats"; 738 reg = <0xfc190000 0x10000>; 739 }; 740 741 gcc: clock-controller@fc400000 { 742 compatible = "qcom,gcc-msm8226"; 743 reg = <0xfc400000 0x4000>; 744 #clock-cells = <1>; 745 #reset-cells = <1>; 746 #power-domain-cells = <1>; 747 748 clocks = <&xo_board>, 749 <&sleep_clk>; 750 clock-names = "xo", 751 "sleep_clk"; 752 }; 753 754 rpm_msg_ram: sram@fc428000 { 755 compatible = "qcom,rpm-msg-ram"; 756 reg = <0xfc428000 0x4000>; 757 758 #address-cells = <1>; 759 #size-cells = <1>; 760 ranges = <0 0xfc428000 0x4000>; 761 762 apss_master_stats: sram@150 { 763 reg = <0x150 0x14>; 764 }; 765 766 mpss_master_stats: sram@b50 { 767 reg = <0xb50 0x14>; 768 }; 769 770 lpss_master_stats: sram@1550 { 771 reg = <0x1550 0x14>; 772 }; 773 774 pronto_master_stats: sram@1f50 { 775 reg = <0x1f50 0x14>; 776 }; 777 }; 778 779 tsens: thermal-sensor@fc4a9000 { 780 compatible = "qcom,msm8226-tsens", "qcom,tsens-v0_1"; 781 reg = <0xfc4a9000 0x1000>, /* TM */ 782 <0xfc4a8000 0x1000>; /* SROT */ 783 nvmem-cells = <&tsens_mode>, 784 <&tsens_base1>, <&tsens_base2>, 785 <&tsens_s0_p1>, <&tsens_s0_p2>, 786 <&tsens_s1_p1>, <&tsens_s1_p2>, 787 <&tsens_s2_p1>, <&tsens_s2_p2>, 788 <&tsens_s3_p1>, <&tsens_s3_p2>, 789 <&tsens_s4_p1>, <&tsens_s4_p2>, 790 <&tsens_s5_p1>, <&tsens_s5_p2>, 791 <&tsens_s6_p1>, <&tsens_s6_p2>; 792 nvmem-cell-names = "mode", 793 "base1", "base2", 794 "s0_p1", "s0_p2", 795 "s1_p1", "s1_p2", 796 "s2_p1", "s2_p2", 797 "s3_p1", "s3_p2", 798 "s4_p1", "s4_p2", 799 "s5_p1", "s5_p2", 800 "s6_p1", "s6_p2"; 801 #qcom,sensors = <6>; 802 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; 803 interrupt-names = "uplow"; 804 #thermal-sensor-cells = <1>; 805 }; 806 807 restart@fc4ab000 { 808 compatible = "qcom,pshold"; 809 reg = <0xfc4ab000 0x4>; 810 }; 811 812 qfprom: efuse@fc4bc000 { 813 compatible = "qcom,msm8226-qfprom", "qcom,qfprom"; 814 reg = <0xfc4bc000 0x1000>; 815 #address-cells = <1>; 816 #size-cells = <1>; 817 818 tsens_base1: base1@1c1 { 819 reg = <0x1c1 0x2>; 820 bits = <5 8>; 821 }; 822 823 tsens_s0_p1: s0-p1@1c2 { 824 reg = <0x1c2 0x2>; 825 bits = <5 6>; 826 }; 827 828 tsens_s1_p1: s1-p1@1c4 { 829 reg = <0x1c4 0x1>; 830 bits = <0 6>; 831 }; 832 833 tsens_s2_p1: s2-p1@1c4 { 834 reg = <0x1c4 0x2>; 835 bits = <6 6>; 836 }; 837 838 tsens_s3_p1: s3-p1@1c5 { 839 reg = <0x1c5 0x2>; 840 bits = <4 6>; 841 }; 842 843 tsens_s4_p1: s4-p1@1c6 { 844 reg = <0x1c6 0x1>; 845 bits = <2 6>; 846 }; 847 848 tsens_s5_p1: s5-p1@1c7 { 849 reg = <0x1c7 0x1>; 850 bits = <0 6>; 851 }; 852 853 tsens_s6_p1: s6-p1@1ca { 854 reg = <0x1ca 0x2>; 855 bits = <4 6>; 856 }; 857 858 tsens_base2: base2@1cc { 859 reg = <0x1cc 0x1>; 860 bits = <0 8>; 861 }; 862 863 tsens_s0_p2: s0-p2@1cd { 864 reg = <0x1cd 0x1>; 865 bits = <0 6>; 866 }; 867 868 tsens_s1_p2: s1-p2@1cd { 869 reg = <0x1cd 0x2>; 870 bits = <6 6>; 871 }; 872 873 tsens_s2_p2: s2-p2@1ce { 874 reg = <0x1ce 0x2>; 875 bits = <4 6>; 876 }; 877 878 tsens_s3_p2: s3-p2@1cf { 879 reg = <0x1cf 0x1>; 880 bits = <2 6>; 881 }; 882 883 tsens_s4_p2: s4-p2@446 { 884 reg = <0x446 0x2>; 885 bits = <4 6>; 886 }; 887 888 tsens_s5_p2: s5-p2@447 { 889 reg = <0x447 0x1>; 890 bits = <2 6>; 891 }; 892 893 tsens_s6_p2: s6-p2@44e { 894 reg = <0x44e 0x1>; 895 bits = <1 6>; 896 }; 897 898 tsens_mode: mode@44f { 899 reg = <0x44f 0x1>; 900 bits = <5 3>; 901 }; 902 }; 903 904 spmi_bus: spmi@fc4cf000 { 905 compatible = "qcom,spmi-pmic-arb"; 906 reg-names = "core", "intr", "cnfg"; 907 reg = <0xfc4cf000 0x1000>, 908 <0xfc4cb000 0x1000>, 909 <0xfc4ca000 0x1000>; 910 interrupt-names = "periph_irq"; 911 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>; 912 qcom,ee = <0>; 913 qcom,channel = <0>; 914 #address-cells = <2>; 915 #size-cells = <0>; 916 interrupt-controller; 917 #interrupt-cells = <4>; 918 }; 919 920 bam_dmux_dma: dma-controller@fc834000 { 921 compatible = "qcom,bam-v1.4.0"; 922 reg = <0xfc834000 0x7000>; 923 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 924 #dma-cells = <1>; 925 qcom,ee = <0>; 926 927 num-channels = <6>; 928 qcom,num-ees = <1>; 929 qcom,powered-remotely; 930 }; 931 932 modem: remoteproc@fc880000 { 933 compatible = "qcom,msm8226-mss-pil"; 934 reg = <0xfc880000 0x4040>, 935 <0xfc820000 0x10000>; 936 reg-names = "qdsp6", 937 "rmb"; 938 939 interrupts-extended = <&intc GIC_SPI 24 IRQ_TYPE_EDGE_RISING>, 940 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 941 <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 942 <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 943 <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 944 interrupt-names = "wdog", 945 "fatal", 946 "ready", 947 "handover", 948 "stop-ack"; 949 950 clocks = <&gcc GCC_MSS_Q6_BIMC_AXI_CLK>, 951 <&gcc GCC_MSS_CFG_AHB_CLK>, 952 <&gcc GCC_BOOT_ROM_AHB_CLK>, 953 <&rpmcc RPM_SMD_XO_CLK_SRC>; 954 clock-names = "iface", 955 "bus", 956 "mem", 957 "xo"; 958 959 resets = <&gcc GCC_MSS_RESTART>; 960 reset-names = "mss_restart"; 961 962 power-domains = <&rpmpd MSM8226_VDDCX>; 963 power-domain-names = "cx"; 964 965 qcom,ext-bhs-reg = <&tcsr_regs_1 0x194>; 966 qcom,halt-regs = <&tcsr_regs_1 0x180 0x200 0x280>; 967 968 qcom,smem-states = <&modem_smp2p_out 0>; 969 qcom,smem-state-names = "stop"; 970 971 memory-region = <&mba_region>, <&mpss_region>; 972 973 status = "disabled"; 974 975 bam_dmux: bam-dmux { 976 compatible = "qcom,bam-dmux"; 977 978 interrupt-parent = <&modem_smsm>; 979 interrupts = <1 IRQ_TYPE_EDGE_BOTH>, <11 IRQ_TYPE_EDGE_BOTH>; 980 interrupt-names = "pc", "pc-ack"; 981 982 qcom,smem-states = <&apps_smsm 1>, <&apps_smsm 11>; 983 qcom,smem-state-names = "pc", "pc-ack"; 984 985 dmas = <&bam_dmux_dma 4>, <&bam_dmux_dma 5>; 986 dma-names = "tx", "rx"; 987 }; 988 989 smd-edge { 990 interrupts = <GIC_SPI 25 IRQ_TYPE_EDGE_RISING>; 991 992 mboxes = <&apcs 12>; 993 qcom,smd-edge = <0>; 994 995 label = "modem"; 996 }; 997 }; 998 999 tcsr_mutex: hwlock@fd484000 { 1000 compatible = "qcom,msm8226-tcsr-mutex", "qcom,tcsr-mutex"; 1001 reg = <0xfd484000 0x1000>; 1002 #hwlock-cells = <1>; 1003 }; 1004 1005 tcsr_regs_1: syscon@fd485000 { 1006 compatible = "qcom,tcsr-msm8226", "syscon"; 1007 reg = <0xfd485000 0x1000>; 1008 }; 1009 1010 tlmm: pinctrl@fd510000 { 1011 compatible = "qcom,msm8226-pinctrl"; 1012 reg = <0xfd510000 0x4000>; 1013 gpio-controller; 1014 #gpio-cells = <2>; 1015 gpio-ranges = <&tlmm 0 0 117>; 1016 interrupt-controller; 1017 #interrupt-cells = <2>; 1018 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 1019 1020 blsp1_i2c1_pins: blsp1-i2c1-state { 1021 pins = "gpio2", "gpio3"; 1022 function = "blsp_i2c1"; 1023 drive-strength = <2>; 1024 bias-disable; 1025 }; 1026 1027 blsp1_i2c2_pins: blsp1-i2c2-state { 1028 pins = "gpio6", "gpio7"; 1029 function = "blsp_i2c2"; 1030 drive-strength = <2>; 1031 bias-disable; 1032 }; 1033 1034 blsp1_i2c3_pins: blsp1-i2c3-state { 1035 pins = "gpio10", "gpio11"; 1036 function = "blsp_i2c3"; 1037 drive-strength = <2>; 1038 bias-disable; 1039 }; 1040 1041 blsp1_i2c4_pins: blsp1-i2c4-state { 1042 pins = "gpio14", "gpio15"; 1043 function = "blsp_i2c4"; 1044 drive-strength = <2>; 1045 bias-disable; 1046 }; 1047 1048 blsp1_i2c5_pins: blsp1-i2c5-state { 1049 pins = "gpio18", "gpio19"; 1050 function = "blsp_i2c5"; 1051 drive-strength = <2>; 1052 bias-disable; 1053 }; 1054 1055 blsp1_i2c6_pins: blsp1-i2c6-state { 1056 pins = "gpio22", "gpio23"; 1057 function = "blsp_i2c6"; 1058 drive-strength = <2>; 1059 bias-disable; 1060 }; 1061 1062 cci_default: cci-default-state { 1063 pins = "gpio29", "gpio30"; 1064 function = "cci_i2c0"; 1065 1066 drive-strength = <2>; 1067 bias-disable; 1068 }; 1069 1070 cci_sleep: cci-sleep-state { 1071 pins = "gpio29", "gpio30"; 1072 function = "gpio"; 1073 1074 drive-strength = <2>; 1075 bias-disable; 1076 }; 1077 1078 sdhc1_default_state: sdhc1-default-state { 1079 clk-pins { 1080 pins = "sdc1_clk"; 1081 drive-strength = <10>; 1082 bias-disable; 1083 }; 1084 1085 cmd-data-pins { 1086 pins = "sdc1_cmd", "sdc1_data"; 1087 drive-strength = <10>; 1088 bias-pull-up; 1089 }; 1090 }; 1091 1092 sdhc2_default_state: sdhc2-default-state { 1093 clk-pins { 1094 pins = "sdc2_clk"; 1095 drive-strength = <10>; 1096 bias-disable; 1097 }; 1098 1099 cmd-data-pins { 1100 pins = "sdc2_cmd", "sdc2_data"; 1101 drive-strength = <10>; 1102 bias-pull-up; 1103 }; 1104 }; 1105 1106 sdhc3_default_state: sdhc3-default-state { 1107 clk-pins { 1108 pins = "gpio44"; 1109 function = "sdc3"; 1110 drive-strength = <8>; 1111 bias-disable; 1112 }; 1113 1114 cmd-pins { 1115 pins = "gpio43"; 1116 function = "sdc3"; 1117 drive-strength = <8>; 1118 bias-pull-up; 1119 }; 1120 1121 data-pins { 1122 pins = "gpio39", "gpio40", "gpio41", "gpio42"; 1123 function = "sdc3"; 1124 drive-strength = <8>; 1125 bias-pull-up; 1126 }; 1127 }; 1128 }; 1129 1130 mmcc: clock-controller@fd8c0000 { 1131 compatible = "qcom,mmcc-msm8226"; 1132 reg = <0xfd8c0000 0x6000>; 1133 #clock-cells = <1>; 1134 #reset-cells = <1>; 1135 #power-domain-cells = <1>; 1136 1137 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, 1138 <&gcc GCC_MMSS_GPLL0_CLK_SRC>, 1139 <&gcc GPLL0_VOTE>, 1140 <&gcc GPLL1_VOTE>, 1141 <&rpmcc RPM_SMD_GFX3D_CLK_SRC>, 1142 <&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>, 1143 <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>; 1144 clock-names = "xo", 1145 "mmss_gpll0_vote", 1146 "gpll0_vote", 1147 "gpll1_vote", 1148 "gfx3d_clk_src", 1149 "dsi0pll", 1150 "dsi0pllbyte"; 1151 }; 1152 1153 mdss: display-subsystem@fd900000 { 1154 compatible = "qcom,mdss"; 1155 reg = <0xfd900000 0x100>, <0xfd924000 0x1000>; 1156 reg-names = "mdss_phys", "vbif_phys"; 1157 1158 power-domains = <&mmcc MDSS_GDSC>; 1159 1160 clocks = <&mmcc MDSS_AHB_CLK>, 1161 <&mmcc MDSS_AXI_CLK>, 1162 <&mmcc MDSS_VSYNC_CLK>; 1163 clock-names = "iface", 1164 "bus", 1165 "vsync"; 1166 1167 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 1168 1169 interrupt-controller; 1170 #interrupt-cells = <1>; 1171 1172 #address-cells = <1>; 1173 #size-cells = <1>; 1174 ranges; 1175 1176 status = "disabled"; 1177 1178 mdss_mdp: display-controller@fd900000 { 1179 compatible = "qcom,msm8226-mdp5", "qcom,mdp5"; 1180 reg = <0xfd900100 0x22000>; 1181 reg-names = "mdp_phys"; 1182 1183 interrupt-parent = <&mdss>; 1184 interrupts = <0>; 1185 1186 clocks = <&mmcc MDSS_AHB_CLK>, 1187 <&mmcc MDSS_AXI_CLK>, 1188 <&mmcc MDSS_MDP_CLK>, 1189 <&mmcc MDSS_VSYNC_CLK>; 1190 clock-names = "iface", 1191 "bus", 1192 "core", 1193 "vsync"; 1194 1195 ports { 1196 #address-cells = <1>; 1197 #size-cells = <0>; 1198 1199 port@0 { 1200 reg = <0>; 1201 mdss_mdp_intf1_out: endpoint { 1202 remote-endpoint = <&mdss_dsi0_in>; 1203 }; 1204 }; 1205 }; 1206 }; 1207 1208 mdss_dsi0: dsi@fd922800 { 1209 compatible = "qcom,msm8226-dsi-ctrl", 1210 "qcom,mdss-dsi-ctrl"; 1211 reg = <0xfd922800 0x1f8>; 1212 reg-names = "dsi_ctrl"; 1213 1214 interrupt-parent = <&mdss>; 1215 interrupts = <4>; 1216 1217 assigned-clocks = <&mmcc BYTE0_CLK_SRC>, 1218 <&mmcc PCLK0_CLK_SRC>; 1219 assigned-clock-parents = <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>, 1220 <&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>; 1221 1222 clocks = <&mmcc MDSS_MDP_CLK>, 1223 <&mmcc MDSS_AHB_CLK>, 1224 <&mmcc MDSS_AXI_CLK>, 1225 <&mmcc MDSS_BYTE0_CLK>, 1226 <&mmcc MDSS_PCLK0_CLK>, 1227 <&mmcc MDSS_ESC0_CLK>, 1228 <&mmcc MMSS_MISC_AHB_CLK>; 1229 clock-names = "mdp_core", 1230 "iface", 1231 "bus", 1232 "byte", 1233 "pixel", 1234 "core", 1235 "core_mmss"; 1236 1237 phys = <&mdss_dsi0_phy>; 1238 1239 #address-cells = <1>; 1240 #size-cells = <0>; 1241 1242 ports { 1243 #address-cells = <1>; 1244 #size-cells = <0>; 1245 1246 port@0 { 1247 reg = <0>; 1248 mdss_dsi0_in: endpoint { 1249 remote-endpoint = <&mdss_mdp_intf1_out>; 1250 }; 1251 }; 1252 1253 port@1 { 1254 reg = <1>; 1255 mdss_dsi0_out: endpoint { 1256 }; 1257 }; 1258 }; 1259 }; 1260 1261 mdss_dsi0_phy: phy@fd922a00 { 1262 compatible = "qcom,dsi-phy-28nm-8226"; 1263 reg = <0xfd922a00 0xd4>, 1264 <0xfd922b00 0x280>, 1265 <0xfd922d80 0x30>; 1266 reg-names = "dsi_pll", 1267 "dsi_phy", 1268 "dsi_phy_regulator"; 1269 1270 #clock-cells = <1>; 1271 #phy-cells = <0>; 1272 1273 clocks = <&mmcc MDSS_AHB_CLK>, 1274 <&rpmcc RPM_SMD_XO_CLK_SRC>; 1275 clock-names = "iface", 1276 "ref"; 1277 }; 1278 }; 1279 1280 cci: cci@fda0c000 { 1281 compatible = "qcom,msm8226-cci"; 1282 reg = <0xfda0c000 0x1000>; 1283 #address-cells = <1>; 1284 #size-cells = <0>; 1285 interrupts = <GIC_SPI 50 IRQ_TYPE_EDGE_RISING>; 1286 clocks = <&mmcc CAMSS_TOP_AHB_CLK>, 1287 <&mmcc CAMSS_CCI_CCI_AHB_CLK>, 1288 <&mmcc CAMSS_CCI_CCI_CLK>; 1289 clock-names = "camss_top_ahb", 1290 "cci_ahb", 1291 "cci"; 1292 1293 pinctrl-names = "default", "sleep"; 1294 pinctrl-0 = <&cci_default>; 1295 pinctrl-1 = <&cci_sleep>; 1296 1297 status = "disabled"; 1298 1299 cci_i2c0: i2c-bus@0 { 1300 reg = <0>; 1301 clock-frequency = <400000>; 1302 #address-cells = <1>; 1303 #size-cells = <0>; 1304 }; 1305 }; 1306 1307 gpu: gpu@fdb00000 { 1308 compatible = "qcom,adreno-305.18", "qcom,adreno"; 1309 reg = <0xfdb00000 0x10000>; 1310 reg-names = "kgsl_3d0_reg_memory"; 1311 1312 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 1313 interrupt-names = "kgsl_3d0_irq"; 1314 1315 clocks = <&mmcc OXILI_GFX3D_CLK>, 1316 <&mmcc OXILICX_AHB_CLK>, 1317 <&mmcc OXILICX_AXI_CLK>; 1318 clock-names = "core", "iface", "mem_iface"; 1319 1320 sram = <&gmu_sram>; 1321 power-domains = <&mmcc OXILICX_GDSC>; 1322 operating-points-v2 = <&gpu_opp_table>; 1323 1324 status = "disabled"; 1325 1326 gpu_opp_table: opp-table { 1327 compatible = "operating-points-v2"; 1328 1329 opp-450000000 { 1330 opp-hz = /bits/ 64 <450000000>; 1331 }; 1332 1333 opp-320000000 { 1334 opp-hz = /bits/ 64 <320000000>; 1335 }; 1336 1337 opp-200000000 { 1338 opp-hz = /bits/ 64 <200000000>; 1339 }; 1340 1341 opp-19000000 { 1342 opp-hz = /bits/ 64 <19000000>; 1343 }; 1344 }; 1345 }; 1346 1347 sram@fdd00000 { 1348 compatible = "qcom,msm8226-ocmem"; 1349 reg = <0xfdd00000 0x2000>, 1350 <0xfec00000 0x20000>; 1351 reg-names = "ctrl", "mem"; 1352 ranges = <0 0xfec00000 0x20000>; 1353 clocks = <&rpmcc RPM_SMD_OCMEMGX_CLK>; 1354 clock-names = "core"; 1355 1356 #address-cells = <1>; 1357 #size-cells = <1>; 1358 1359 gmu_sram: gmu-sram@0 { 1360 reg = <0x0 0x20000>; 1361 }; 1362 }; 1363 1364 adsp: remoteproc@fe200000 { 1365 compatible = "qcom,msm8226-adsp-pil"; 1366 reg = <0xfe200000 0x100>; 1367 1368 interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>, 1369 <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 1370 <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 1371 <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 1372 <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 1373 interrupt-names = "wdog", "fatal", "ready", "handover", "stop-ack"; 1374 1375 power-domains = <&rpmpd MSM8226_VDDCX>; 1376 power-domain-names = "cx"; 1377 1378 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>; 1379 clock-names = "xo"; 1380 1381 memory-region = <&adsp_region>; 1382 1383 qcom,smem-states = <&adsp_smp2p_out 0>; 1384 qcom,smem-state-names = "stop"; 1385 1386 status = "disabled"; 1387 1388 smd-edge { 1389 interrupts = <GIC_SPI 156 IRQ_TYPE_EDGE_RISING>; 1390 1391 mboxes = <&apcs 8>; 1392 qcom,smd-edge = <1>; 1393 1394 label = "lpass"; 1395 }; 1396 }; 1397 1398 sram@fe805000 { 1399 compatible = "qcom,msm8226-imem", "syscon", "simple-mfd"; 1400 reg = <0xfe805000 0x1000>; 1401 1402 reboot-mode { 1403 compatible = "syscon-reboot-mode"; 1404 offset = <0x65c>; 1405 1406 mode-bootloader = <0x77665500>; 1407 mode-normal = <0x77665501>; 1408 mode-recovery = <0x77665502>; 1409 }; 1410 }; 1411 }; 1412 1413 thermal-zones { 1414 cpu0-thermal { 1415 polling-delay-passive = <250>; 1416 polling-delay = <1000>; 1417 1418 thermal-sensors = <&tsens 5>; 1419 1420 cooling-maps { 1421 map0 { 1422 trip = <&cpu_alert0>; 1423 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1424 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1425 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1426 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1427 }; 1428 }; 1429 1430 trips { 1431 cpu_alert0: trip0 { 1432 temperature = <75000>; 1433 hysteresis = <2000>; 1434 type = "passive"; 1435 }; 1436 1437 cpu_crit0: trip1 { 1438 temperature = <110000>; 1439 hysteresis = <2000>; 1440 type = "critical"; 1441 }; 1442 }; 1443 }; 1444 1445 cpu1-thermal { 1446 polling-delay-passive = <250>; 1447 polling-delay = <1000>; 1448 1449 thermal-sensors = <&tsens 2>; 1450 1451 cooling-maps { 1452 map0 { 1453 trip = <&cpu_alert1>; 1454 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1455 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1456 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1457 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1458 }; 1459 }; 1460 1461 trips { 1462 cpu_alert1: trip0 { 1463 temperature = <75000>; 1464 hysteresis = <2000>; 1465 type = "passive"; 1466 }; 1467 1468 cpu_crit1: trip1 { 1469 temperature = <110000>; 1470 hysteresis = <2000>; 1471 type = "critical"; 1472 }; 1473 }; 1474 }; 1475 }; 1476 1477 timer { 1478 compatible = "arm,armv7-timer"; 1479 interrupts = <GIC_PPI 2 1480 (GIC_CPU_MASK_RAW(15) | IRQ_TYPE_LEVEL_LOW)>, 1481 <GIC_PPI 3 1482 (GIC_CPU_MASK_RAW(15) | IRQ_TYPE_LEVEL_LOW)>, 1483 <GIC_PPI 4 1484 (GIC_CPU_MASK_RAW(15) | IRQ_TYPE_LEVEL_LOW)>, 1485 <GIC_PPI 1 1486 (GIC_CPU_MASK_RAW(15) | IRQ_TYPE_LEVEL_LOW)>; 1487 }; 1488};
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