qcom-ipq8064.dtsi

   1// SPDX-License-Identifier: GPL-2.0
   2/dts-v1/;
   3
   4#include <dt-bindings/interrupt-controller/arm-gic.h>
   5#include <dt-bindings/mfd/qcom-rpm.h>
   6#include <dt-bindings/clock/qcom,rpmcc.h>
   7#include <dt-bindings/clock/qcom,gcc-ipq806x.h>
   8#include <dt-bindings/clock/qcom,lcc-ipq806x.h>
   9#include <dt-bindings/gpio/gpio.h>
  10#include <dt-bindings/reset/qcom,gcc-ipq806x.h>
  11#include <dt-bindings/soc/qcom,gsbi.h>
  12#include <dt-bindings/interrupt-controller/arm-gic.h>
  13
  14/ {
  15	#address-cells = <1>;
  16	#size-cells = <1>;
  17	model = "Qualcomm IPQ8064";
  18	compatible = "qcom,ipq8064";
  19	interrupt-parent = <&intc>;
  20
  21	cpus {
  22		#address-cells = <1>;
  23		#size-cells = <0>;
  24
  25		cpu0: cpu@0 {
  26			compatible = "qcom,krait";
  27			enable-method = "qcom,kpss-acc-v1";
  28			device_type = "cpu";
  29			reg = <0>;
  30			next-level-cache = <&l2>;
  31			qcom,acc = <&acc0>;
  32			qcom,saw = <&saw0>;
  33		};
  34
  35		cpu1: cpu@1 {
  36			compatible = "qcom,krait";
  37			enable-method = "qcom,kpss-acc-v1";
  38			device_type = "cpu";
  39			reg = <1>;
  40			next-level-cache = <&l2>;
  41			qcom,acc = <&acc1>;
  42			qcom,saw = <&saw1>;
  43		};
  44
  45		l2: l2-cache {
  46			compatible = "cache";
  47			cache-level = <2>;
  48			cache-unified;
  49		};
  50	};
  51
  52	thermal-zones {
  53		sensor0-thermal {
  54			polling-delay-passive = <0>;
  55			polling-delay = <0>;
  56			thermal-sensors = <&tsens 0>;
  57
  58			trips {
  59				cpu-critical {
  60					temperature = <105000>;
  61					hysteresis = <2000>;
  62					type = "critical";
  63				};
  64
  65				cpu-hot {
  66					temperature = <95000>;
  67					hysteresis = <2000>;
  68					type = "hot";
  69				};
  70			};
  71		};
  72
  73		sensor1-thermal {
  74			polling-delay-passive = <0>;
  75			polling-delay = <0>;
  76			thermal-sensors = <&tsens 1>;
  77
  78			trips {
  79				cpu-critical {
  80					temperature = <105000>;
  81					hysteresis = <2000>;
  82					type = "critical";
  83				};
  84
  85				cpu-hot {
  86					temperature = <95000>;
  87					hysteresis = <2000>;
  88					type = "hot";
  89				};
  90			};
  91		};
  92
  93		sensor2-thermal {
  94			polling-delay-passive = <0>;
  95			polling-delay = <0>;
  96			thermal-sensors = <&tsens 2>;
  97
  98			trips {
  99				cpu-critical {
 100					temperature = <105000>;
 101					hysteresis = <2000>;
 102					type = "critical";
 103				};
 104
 105				cpu-hot {
 106					temperature = <95000>;
 107					hysteresis = <2000>;
 108					type = "hot";
 109				};
 110			};
 111		};
 112
 113		sensor3-thermal {
 114			polling-delay-passive = <0>;
 115			polling-delay = <0>;
 116			thermal-sensors = <&tsens 3>;
 117
 118			trips {
 119				cpu-critical {
 120					temperature = <105000>;
 121					hysteresis = <2000>;
 122					type = "critical";
 123				};
 124
 125				cpu-hot {
 126					temperature = <95000>;
 127					hysteresis = <2000>;
 128					type = "hot";
 129				};
 130			};
 131		};
 132
 133		sensor4-thermal {
 134			polling-delay-passive = <0>;
 135			polling-delay = <0>;
 136			thermal-sensors = <&tsens 4>;
 137
 138			trips {
 139				cpu-critical {
 140					temperature = <105000>;
 141					hysteresis = <2000>;
 142					type = "critical";
 143				};
 144
 145				cpu-hot {
 146					temperature = <95000>;
 147					hysteresis = <2000>;
 148					type = "hot";
 149				};
 150			};
 151		};
 152
 153		sensor5-thermal {
 154			polling-delay-passive = <0>;
 155			polling-delay = <0>;
 156			thermal-sensors = <&tsens 5>;
 157
 158			trips {
 159				cpu-critical {
 160					temperature = <105000>;
 161					hysteresis = <2000>;
 162					type = "critical";
 163				};
 164
 165				cpu-hot {
 166					temperature = <95000>;
 167					hysteresis = <2000>;
 168					type = "hot";
 169				};
 170			};
 171		};
 172
 173		sensor6-thermal {
 174			polling-delay-passive = <0>;
 175			polling-delay = <0>;
 176			thermal-sensors = <&tsens 6>;
 177
 178			trips {
 179				cpu-critical {
 180					temperature = <105000>;
 181					hysteresis = <2000>;
 182					type = "critical";
 183				};
 184
 185				cpu-hot {
 186					temperature = <95000>;
 187					hysteresis = <2000>;
 188					type = "hot";
 189				};
 190			};
 191		};
 192
 193		sensor7-thermal {
 194			polling-delay-passive = <0>;
 195			polling-delay = <0>;
 196			thermal-sensors = <&tsens 7>;
 197
 198			trips {
 199				cpu-critical {
 200					temperature = <105000>;
 201					hysteresis = <2000>;
 202					type = "critical";
 203				};
 204
 205				cpu-hot {
 206					temperature = <95000>;
 207					hysteresis = <2000>;
 208					type = "hot";
 209				};
 210			};
 211		};
 212
 213		sensor8-thermal {
 214			polling-delay-passive = <0>;
 215			polling-delay = <0>;
 216			thermal-sensors = <&tsens 8>;
 217
 218			trips {
 219				cpu-critical {
 220					temperature = <105000>;
 221					hysteresis = <2000>;
 222					type = "critical";
 223				};
 224
 225				cpu-hot {
 226					temperature = <95000>;
 227					hysteresis = <2000>;
 228					type = "hot";
 229				};
 230			};
 231		};
 232
 233		sensor9-thermal {
 234			polling-delay-passive = <0>;
 235			polling-delay = <0>;
 236			thermal-sensors = <&tsens 9>;
 237
 238			trips {
 239				cpu-critical {
 240					temperature = <105000>;
 241					hysteresis = <2000>;
 242					type = "critical";
 243				};
 244
 245				cpu-hot {
 246					temperature = <95000>;
 247					hysteresis = <2000>;
 248					type = "hot";
 249				};
 250			};
 251		};
 252
 253		sensor10-thermal {
 254			polling-delay-passive = <0>;
 255			polling-delay = <0>;
 256			thermal-sensors = <&tsens 10>;
 257
 258			trips {
 259				cpu-critical {
 260					temperature = <105000>;
 261					hysteresis = <2000>;
 262					type = "critical";
 263				};
 264
 265				cpu-hot {
 266					temperature = <95000>;
 267					hysteresis = <2000>;
 268					type = "hot";
 269				};
 270			};
 271		};
 272	};
 273
 274	memory {
 275		device_type = "memory";
 276		reg = <0x0 0x0>;
 277	};
 278
 279	cpu-pmu {
 280		compatible = "qcom,krait-pmu";
 281		interrupts = <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) |
 282					  IRQ_TYPE_LEVEL_HIGH)>;
 283	};
 284
 285	reserved-memory {
 286		#address-cells = <1>;
 287		#size-cells = <1>;
 288		ranges;
 289
 290		nss@40000000 {
 291			reg = <0x40000000 0x1000000>;
 292			no-map;
 293		};
 294
 295		smem: smem@41000000 {
 296			compatible = "qcom,smem";
 297			reg = <0x41000000 0x200000>;
 298			no-map;
 299
 300			hwlocks = <&sfpb_mutex 3>;
 301		};
 302	};
 303
 304	clocks {
 305		cxo_board: cxo_board {
 306			compatible = "fixed-clock";
 307			#clock-cells = <0>;
 308			clock-frequency = <25000000>;
 309		};
 310
 311		pxo_board: pxo_board {
 312			compatible = "fixed-clock";
 313			#clock-cells = <0>;
 314			clock-frequency = <25000000>;
 315		};
 316
 317		sleep_clk: sleep_clk {
 318			compatible = "fixed-clock";
 319			clock-frequency = <32768>;
 320			#clock-cells = <0>;
 321		};
 322	};
 323
 324	firmware {
 325		scm {
 326			compatible = "qcom,scm-ipq806x", "qcom,scm";
 327		};
 328	};
 329
 330	stmmac_axi_setup: stmmac-axi-config {
 331		snps,wr_osr_lmt = <7>;
 332		snps,rd_osr_lmt = <7>;
 333		snps,blen = <16 0 0 0 0 0 0>;
 334	};
 335
 336	vsdcc_fixed: vsdcc-regulator {
 337		compatible = "regulator-fixed";
 338		regulator-name = "SDCC Power";
 339		regulator-min-microvolt = <3300000>;
 340		regulator-max-microvolt = <3300000>;
 341		regulator-always-on;
 342	};
 343
 344	soc: soc {
 345		#address-cells = <1>;
 346		#size-cells = <1>;
 347		ranges;
 348		compatible = "simple-bus";
 349
 350		rpm: rpm@108000 {
 351			compatible = "qcom,rpm-ipq8064";
 352			reg = <0x00108000 0x1000>;
 353			qcom,ipc = <&l2cc 0x8 2>;
 354
 355			interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
 356					<GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
 357					<GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
 358			interrupt-names = "ack", "err", "wakeup";
 359
 360			clocks = <&gcc RPM_MSG_RAM_H_CLK>;
 361			clock-names = "ram";
 362
 363			rpmcc: clock-controller {
 364				compatible = "qcom,rpmcc-ipq806x", "qcom,rpmcc";
 365				#clock-cells = <1>;
 366			};
 367		};
 368
 369		ssbi@500000 {
 370			compatible = "qcom,ssbi";
 371			reg = <0x00500000 0x1000>;
 372			qcom,controller-type = "pmic-arbiter";
 373		};
 374
 375		qfprom: efuse@700000 {
 376			compatible = "qcom,ipq8064-qfprom", "qcom,qfprom";
 377			reg = <0x00700000 0x1000>;
 378			#address-cells = <1>;
 379			#size-cells = <1>;
 380			speedbin_efuse: speedbin@c0 {
 381				reg = <0xc0 0x4>;
 382			};
 383			tsens_calib: calib@400 {
 384				reg = <0x400 0xb>;
 385			};
 386			tsens_calib_backup: calib-backup@410 {
 387				reg = <0x410 0xb>;
 388			};
 389		};
 390
 391		qcom_pinmux: pinmux@800000 {
 392			compatible = "qcom,ipq8064-pinctrl";
 393			reg = <0x00800000 0x4000>;
 394
 395			gpio-controller;
 396			gpio-ranges = <&qcom_pinmux 0 0 69>;
 397			#gpio-cells = <2>;
 398			interrupt-controller;
 399			#interrupt-cells = <2>;
 400			interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
 401
 402			pcie0_pins: pcie0-state {
 403				pins = "gpio3";
 404				function = "pcie1_rst";
 405				drive-strength = <12>;
 406				bias-disable;
 407			};
 408
 409			pcie1_pins: pcie1-state {
 410				pins = "gpio48";
 411				function = "pcie2_rst";
 412				drive-strength = <12>;
 413				bias-disable;
 414			};
 415
 416			pcie2_pins: pcie2-state {
 417				pins = "gpio63";
 418				function = "pcie3_rst";
 419				drive-strength = <12>;
 420				bias-disable;
 421			};
 422
 423			i2c4_pins: i2c4-state {
 424				pins = "gpio12", "gpio13";
 425				function = "gsbi4";
 426				drive-strength = <12>;
 427				bias-disable;
 428			};
 429
 430			spi_pins: spi-state {
 431				pins = "gpio18", "gpio19", "gpio21";
 432				function = "gsbi5";
 433				drive-strength = <10>;
 434				bias-disable;
 435			};
 436
 437			leds_pins: leds-state {
 438				pins = "gpio7", "gpio8", "gpio9",
 439					"gpio26", "gpio53";
 440				function = "gpio";
 441				drive-strength = <2>;
 442				bias-pull-down;
 443				output-low;
 444			};
 445
 446			buttons_pins: buttons-state {
 447				pins = "gpio54";
 448				drive-strength = <2>;
 449				bias-pull-up;
 450			};
 451
 452			nand_pins: nand-state {
 453				nand-pins {
 454					pins = "gpio34", "gpio35", "gpio36",
 455					       "gpio37", "gpio38", "gpio39",
 456					       "gpio40", "gpio41", "gpio42",
 457					       "gpio43", "gpio44", "gpio45",
 458					       "gpio46", "gpio47";
 459					function = "nand";
 460					drive-strength = <10>;
 461					bias-disable;
 462				};
 463
 464				nand-pullup-pins {
 465					pins = "gpio39";
 466					function = "nand";
 467					drive-strength = <10>;
 468					bias-pull-up;
 469				};
 470
 471				nand-hold-pins {
 472					pins = "gpio40", "gpio41", "gpio42",
 473					       "gpio43", "gpio44", "gpio45",
 474					       "gpio46", "gpio47";
 475					function = "nand";
 476					drive-strength = <10>;
 477					bias-bus-hold;
 478				};
 479			};
 480
 481			mdio0_pins: mdio0-state {
 482				pins = "gpio0", "gpio1";
 483				function = "mdio";
 484				drive-strength = <8>;
 485				bias-disable;
 486			};
 487
 488			rgmii2_pins: rgmii2-state {
 489				pins = "gpio27", "gpio28", "gpio29",
 490					"gpio30", "gpio31", "gpio32",
 491					"gpio51", "gpio52", "gpio59",
 492					"gpio60", "gpio61", "gpio62";
 493				function = "rgmii2";
 494				drive-strength = <8>;
 495				bias-disable;
 496			};
 497		};
 498
 499		gcc: clock-controller@900000 {
 500			compatible = "qcom,gcc-ipq8064", "syscon";
 501			clocks = <&pxo_board>, <&cxo_board>, <&lcc PLL4>;
 502			clock-names = "pxo", "cxo", "pll4";
 503			reg = <0x00900000 0x4000>;
 504			#clock-cells = <1>;
 505			#reset-cells = <1>;
 506
 507			tsens: thermal-sensor {
 508				compatible = "qcom,ipq8064-tsens";
 509
 510				nvmem-cells = <&tsens_calib>, <&tsens_calib_backup>;
 511				nvmem-cell-names = "calib", "calib_backup";
 512				interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>;
 513				interrupt-names = "uplow";
 514
 515				#qcom,sensors = <11>;
 516				#thermal-sensor-cells = <1>;
 517			};
 518		};
 519
 520		sfpb_mutex: hwlock@1200600 {
 521			compatible = "qcom,sfpb-mutex";
 522			reg = <0x01200600 0x100>;
 523
 524			#hwlock-cells = <1>;
 525		};
 526
 527		intc: interrupt-controller@2000000 {
 528			compatible = "qcom,msm-qgic2";
 529			interrupt-controller;
 530			#address-cells = <0>;
 531			#interrupt-cells = <3>;
 532			reg = <0x02000000 0x1000>,
 533			      <0x02002000 0x1000>;
 534		};
 535
 536		timer@200a000 {
 537			compatible = "qcom,kpss-wdt-ipq8064", "qcom,kpss-timer",
 538				     "qcom,msm-timer";
 539			interrupts = <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(2) |
 540						 IRQ_TYPE_EDGE_RISING)>,
 541				     <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(2) |
 542						 IRQ_TYPE_EDGE_RISING)>,
 543				     <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(2) |
 544						 IRQ_TYPE_EDGE_RISING)>,
 545				     <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(2) |
 546						 IRQ_TYPE_EDGE_RISING)>,
 547				     <GIC_PPI 5 (GIC_CPU_MASK_SIMPLE(2) |
 548						 IRQ_TYPE_EDGE_RISING)>;
 549			reg = <0x0200a000 0x100>;
 550			clock-frequency = <25000000>;
 551			clocks = <&sleep_clk>;
 552			clock-names = "sleep";
 553			cpu-offset = <0x80000>;
 554		};
 555
 556		l2cc: clock-controller@2011000 {
 557			compatible = "qcom,kpss-gcc-ipq8064", "qcom,kpss-gcc", "syscon";
 558			reg = <0x02011000 0x1000>;
 559			clocks = <&gcc PLL8_VOTE>, <&pxo_board>;
 560			clock-names = "pll8_vote", "pxo";
 561			#clock-cells = <0>;
 562		};
 563
 564		acc0: clock-controller@2088000 {
 565			compatible = "qcom,kpss-acc-v1";
 566			reg = <0x02088000 0x1000>, <0x02008000 0x1000>;
 567			clocks = <&gcc PLL8_VOTE>, <&pxo_board>;
 568			clock-names = "pll8_vote", "pxo";
 569			clock-output-names = "acpu0_aux";
 570			#clock-cells = <0>;
 571		};
 572
 573		saw0: power-manager@2089000 {
 574			compatible = "qcom,ipq8064-saw2-cpu", "qcom,saw2";
 575			reg = <0x02089000 0x1000>, <0x02009000 0x1000>;
 576		};
 577
 578		acc1: clock-controller@2098000 {
 579			compatible = "qcom,kpss-acc-v1";
 580			reg = <0x02098000 0x1000>, <0x02008000 0x1000>;
 581			clocks = <&gcc PLL8_VOTE>, <&pxo_board>;
 582			clock-names = "pll8_vote", "pxo";
 583			clock-output-names = "acpu1_aux";
 584			#clock-cells = <0>;
 585		};
 586
 587		saw1: power-manager@2099000 {
 588			compatible = "qcom,ipq8064-saw2-cpu", "qcom,saw2";
 589			reg = <0x02099000 0x1000>, <0x02009000 0x1000>;
 590		};
 591
 592		nss_common: syscon@3000000 {
 593			compatible = "syscon";
 594			reg = <0x03000000 0x0000FFFF>;
 595		};
 596
 597		usb3_0: usb@100f8800 {
 598			compatible = "qcom,ipq8064-dwc3", "qcom,dwc3";
 599			#address-cells = <1>;
 600			#size-cells = <1>;
 601			reg = <0x100f8800 0x8000>;
 602			clocks = <&gcc USB30_0_MASTER_CLK>;
 603			clock-names = "core";
 604
 605			ranges;
 606
 607			resets = <&gcc USB30_0_MASTER_RESET>;
 608
 609			status = "disabled";
 610
 611			dwc3_0: usb@10000000 {
 612				compatible = "snps,dwc3";
 613				reg = <0x10000000 0xcd00>;
 614				interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>;
 615				phys = <&hs_phy_0>, <&ss_phy_0>;
 616				phy-names = "usb2-phy", "usb3-phy";
 617				dr_mode = "host";
 618				snps,dis_u3_susphy_quirk;
 619			};
 620		};
 621
 622		hs_phy_0: phy@100f8800 {
 623			compatible = "qcom,ipq806x-usb-phy-hs";
 624			reg = <0x100f8800 0x30>;
 625			clocks = <&gcc USB30_0_UTMI_CLK>;
 626			clock-names = "ref";
 627			#phy-cells = <0>;
 628
 629			status = "disabled";
 630		};
 631
 632		ss_phy_0: phy@100f8830 {
 633			compatible = "qcom,ipq806x-usb-phy-ss";
 634			reg = <0x100f8830 0x30>;
 635			clocks = <&gcc USB30_0_MASTER_CLK>;
 636			clock-names = "ref";
 637			#phy-cells = <0>;
 638
 639			status = "disabled";
 640		};
 641
 642		usb3_1: usb@110f8800 {
 643			compatible = "qcom,ipq8064-dwc3", "qcom,dwc3";
 644			#address-cells = <1>;
 645			#size-cells = <1>;
 646			reg = <0x110f8800 0x8000>;
 647			clocks = <&gcc USB30_1_MASTER_CLK>;
 648			clock-names = "core";
 649
 650			ranges;
 651
 652			resets = <&gcc USB30_1_MASTER_RESET>;
 653
 654			status = "disabled";
 655
 656			dwc3_1: usb@11000000 {
 657				compatible = "snps,dwc3";
 658				reg = <0x11000000 0xcd00>;
 659				interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
 660				phys = <&hs_phy_1>, <&ss_phy_1>;
 661				phy-names = "usb2-phy", "usb3-phy";
 662				dr_mode = "host";
 663				snps,dis_u3_susphy_quirk;
 664			};
 665		};
 666
 667		hs_phy_1: phy@110f8800 {
 668			compatible = "qcom,ipq806x-usb-phy-hs";
 669			reg = <0x110f8800 0x30>;
 670			clocks = <&gcc USB30_1_UTMI_CLK>;
 671			clock-names = "ref";
 672			#phy-cells = <0>;
 673
 674			status = "disabled";
 675		};
 676
 677		ss_phy_1: phy@110f8830 {
 678			compatible = "qcom,ipq806x-usb-phy-ss";
 679			reg = <0x110f8830 0x30>;
 680			clocks = <&gcc USB30_1_MASTER_CLK>;
 681			clock-names = "ref";
 682			#phy-cells = <0>;
 683
 684			status = "disabled";
 685		};
 686
 687		sdcc3bam: dma-controller@12182000 {
 688			compatible = "qcom,bam-v1.3.0";
 689			reg = <0x12182000 0x8000>;
 690			interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
 691			clocks = <&gcc SDC3_H_CLK>;
 692			clock-names = "bam_clk";
 693			#dma-cells = <1>;
 694			qcom,ee = <0>;
 695		};
 696
 697		sdcc1bam: dma-controller@12402000 {
 698			compatible = "qcom,bam-v1.3.0";
 699			reg = <0x12402000 0x8000>;
 700			interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
 701			clocks = <&gcc SDC1_H_CLK>;
 702			clock-names = "bam_clk";
 703			#dma-cells = <1>;
 704			qcom,ee = <0>;
 705		};
 706
 707		amba: amba {
 708			compatible = "simple-bus";
 709			#address-cells = <1>;
 710			#size-cells = <1>;
 711			ranges;
 712
 713			sdcc3: mmc@12180000 {
 714				compatible = "arm,pl18x", "arm,primecell";
 715				arm,primecell-periphid = <0x00051180>;
 716				status = "disabled";
 717				reg = <0x12180000 0x2000>;
 718				interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
 719				clocks = <&gcc SDC3_CLK>, <&gcc SDC3_H_CLK>;
 720				clock-names = "mclk", "apb_pclk";
 721				bus-width = <8>;
 722				cap-sd-highspeed;
 723				cap-mmc-highspeed;
 724				max-frequency = <192000000>;
 725				sd-uhs-sdr104;
 726				sd-uhs-ddr50;
 727				vqmmc-supply = <&vsdcc_fixed>;
 728				dmas = <&sdcc3bam 2>, <&sdcc3bam 1>;
 729				dma-names = "tx", "rx";
 730			};
 731
 732			sdcc1: mmc@12400000 {
 733				status = "disabled";
 734				compatible = "arm,pl18x", "arm,primecell";
 735				arm,primecell-periphid = <0x00051180>;
 736				reg = <0x12400000 0x2000>;
 737				interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
 738				clocks = <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>;
 739				clock-names = "mclk", "apb_pclk";
 740				bus-width = <8>;
 741				max-frequency = <96000000>;
 742				non-removable;
 743				cap-sd-highspeed;
 744				cap-mmc-highspeed;
 745				vmmc-supply = <&vsdcc_fixed>;
 746				dmas = <&sdcc1bam 2>, <&sdcc1bam 1>;
 747				dma-names = "tx", "rx";
 748			};
 749		};
 750
 751		gsbi1: gsbi@12440000 {
 752			compatible = "qcom,gsbi-v1.0.0";
 753			reg = <0x12440000 0x100>;
 754			cell-index = <1>;
 755			clocks = <&gcc GSBI1_H_CLK>;
 756			clock-names = "iface";
 757			#address-cells = <1>;
 758			#size-cells = <1>;
 759			ranges;
 760
 761			syscon-tcsr = <&tcsr>;
 762
 763			status = "disabled";
 764
 765			gsbi1_serial: serial@12450000 {
 766				compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
 767				reg = <0x12450000 0x100>,
 768				      <0x12400000 0x03>;
 769				interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>;
 770				clocks = <&gcc GSBI1_UART_CLK>, <&gcc GSBI1_H_CLK>;
 771				clock-names = "core", "iface";
 772
 773				status = "disabled";
 774			};
 775
 776			gsbi1_i2c: i2c@12460000 {
 777				compatible = "qcom,i2c-qup-v1.1.1";
 778				reg = <0x12460000 0x1000>;
 779				interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>;
 780				clocks = <&gcc GSBI1_QUP_CLK>, <&gcc GSBI1_H_CLK>;
 781				clock-names = "core", "iface";
 782				#address-cells = <1>;
 783				#size-cells = <0>;
 784
 785				status = "disabled";
 786			};
 787		};
 788
 789		gsbi2: gsbi@12480000 {
 790			compatible = "qcom,gsbi-v1.0.0";
 791			cell-index = <2>;
 792			reg = <0x12480000 0x100>;
 793			clocks = <&gcc GSBI2_H_CLK>;
 794			clock-names = "iface";
 795			#address-cells = <1>;
 796			#size-cells = <1>;
 797			ranges;
 798			status = "disabled";
 799
 800			syscon-tcsr = <&tcsr>;
 801
 802			gsbi2_serial: serial@12490000 {
 803				compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
 804				reg = <0x12490000 0x1000>,
 805				      <0x12480000 0x1000>;
 806				interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>;
 807				clocks = <&gcc GSBI2_UART_CLK>, <&gcc GSBI2_H_CLK>;
 808				clock-names = "core", "iface";
 809				status = "disabled";
 810			};
 811
 812			gsbi2_i2c: i2c@124a0000 {
 813				compatible = "qcom,i2c-qup-v1.1.1";
 814				reg = <0x124a0000 0x1000>;
 815				interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>;
 816
 817				clocks = <&gcc GSBI2_QUP_CLK>, <&gcc GSBI2_H_CLK>;
 818				clock-names = "core", "iface";
 819				status = "disabled";
 820
 821				#address-cells = <1>;
 822				#size-cells = <0>;
 823			};
 824		};
 825
 826		gsbi4: gsbi@16300000 {
 827			compatible = "qcom,gsbi-v1.0.0";
 828			cell-index = <4>;
 829			reg = <0x16300000 0x100>;
 830			clocks = <&gcc GSBI4_H_CLK>;
 831			clock-names = "iface";
 832			#address-cells = <1>;
 833			#size-cells = <1>;
 834			ranges;
 835			status = "disabled";
 836
 837			syscon-tcsr = <&tcsr>;
 838
 839			gsbi4_serial: serial@16340000 {
 840				compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
 841				reg = <0x16340000 0x1000>,
 842				      <0x16300000 0x1000>;
 843				interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
 844				clocks = <&gcc GSBI4_UART_CLK>, <&gcc GSBI4_H_CLK>;
 845				clock-names = "core", "iface";
 846				status = "disabled";
 847			};
 848
 849			i2c@16380000 {
 850				compatible = "qcom,i2c-qup-v1.1.1";
 851				reg = <0x16380000 0x1000>;
 852				interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
 853
 854				clocks = <&gcc GSBI4_QUP_CLK>, <&gcc GSBI4_H_CLK>;
 855				clock-names = "core", "iface";
 856				status = "disabled";
 857
 858				#address-cells = <1>;
 859				#size-cells = <0>;
 860			};
 861		};
 862
 863		gsbi6: gsbi@16500000 {
 864			compatible = "qcom,gsbi-v1.0.0";
 865			reg = <0x16500000 0x100>;
 866			cell-index = <6>;
 867			clocks = <&gcc GSBI6_H_CLK>;
 868			clock-names = "iface";
 869			#address-cells = <1>;
 870			#size-cells = <1>;
 871			ranges;
 872
 873			syscon-tcsr = <&tcsr>;
 874
 875			status = "disabled";
 876
 877			gsbi6_i2c: i2c@16580000 {
 878				compatible = "qcom,i2c-qup-v1.1.1";
 879				reg = <0x16580000 0x1000>;
 880				interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
 881
 882				clocks = <&gcc GSBI6_QUP_CLK>, <&gcc GSBI6_H_CLK>;
 883				clock-names = "core", "iface";
 884
 885				#address-cells = <1>;
 886				#size-cells = <0>;
 887
 888				status = "disabled";
 889			};
 890
 891			gsbi6_spi: spi@16580000 {
 892				compatible = "qcom,spi-qup-v1.1.1";
 893				reg = <0x16580000 0x1000>;
 894				interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
 895
 896				clocks = <&gcc GSBI6_QUP_CLK>, <&gcc GSBI6_H_CLK>;
 897				clock-names = "core", "iface";
 898
 899				#address-cells = <1>;
 900				#size-cells = <0>;
 901
 902				status = "disabled";
 903			};
 904		};
 905
 906		gsbi7: gsbi@16600000 {
 907			status = "disabled";
 908			compatible = "qcom,gsbi-v1.0.0";
 909			cell-index = <7>;
 910			reg = <0x16600000 0x100>;
 911			clocks = <&gcc GSBI7_H_CLK>;
 912			clock-names = "iface";
 913			#address-cells = <1>;
 914			#size-cells = <1>;
 915			ranges;
 916			syscon-tcsr = <&tcsr>;
 917
 918			gsbi7_serial: serial@16640000 {
 919				compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
 920				reg = <0x16640000 0x1000>,
 921				      <0x16600000 0x1000>;
 922				interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
 923				clocks = <&gcc GSBI7_UART_CLK>, <&gcc GSBI7_H_CLK>;
 924				clock-names = "core", "iface";
 925				status = "disabled";
 926			};
 927
 928			gsbi7_i2c: i2c@16680000 {
 929				compatible = "qcom,i2c-qup-v1.1.1";
 930				reg = <0x16680000 0x1000>;
 931				interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
 932
 933				clocks = <&gcc GSBI7_QUP_CLK>, <&gcc GSBI7_H_CLK>;
 934				clock-names = "core", "iface";
 935
 936				#address-cells = <1>;
 937				#size-cells = <0>;
 938
 939				status = "disabled";
 940			};
 941		};
 942
 943		adm_dma: dma-controller@18300000 {
 944			compatible = "qcom,adm";
 945			reg = <0x18300000 0x100000>;
 946			interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
 947			#dma-cells = <1>;
 948
 949			clocks = <&gcc ADM0_CLK>, <&gcc ADM0_PBUS_CLK>;
 950			clock-names = "core", "iface";
 951
 952			resets = <&gcc ADM0_RESET>,
 953				 <&gcc ADM0_PBUS_RESET>,
 954				 <&gcc ADM0_C0_RESET>,
 955				 <&gcc ADM0_C1_RESET>,
 956				 <&gcc ADM0_C2_RESET>;
 957			reset-names = "clk", "pbus", "c0", "c1", "c2";
 958			qcom,ee = <0>;
 959
 960			status = "disabled";
 961		};
 962
 963		gsbi5: gsbi@1a200000 {
 964			compatible = "qcom,gsbi-v1.0.0";
 965			cell-index = <5>;
 966			reg = <0x1a200000 0x100>;
 967			clocks = <&gcc GSBI5_H_CLK>;
 968			clock-names = "iface";
 969			#address-cells = <1>;
 970
 971			#size-cells = <1>;
 972			ranges;
 973			status = "disabled";
 974
 975			syscon-tcsr = <&tcsr>;
 976
 977			gsbi5_serial: serial@1a240000 {
 978				compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
 979				reg = <0x1a240000 0x1000>,
 980				      <0x1a200000 0x1000>;
 981				interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
 982				clocks = <&gcc GSBI5_UART_CLK>, <&gcc GSBI5_H_CLK>;
 983				clock-names = "core", "iface";
 984				status = "disabled";
 985			};
 986
 987			i2c@1a280000 {
 988				compatible = "qcom,i2c-qup-v1.1.1";
 989				reg = <0x1a280000 0x1000>;
 990				interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
 991
 992				clocks = <&gcc GSBI5_QUP_CLK>, <&gcc GSBI5_H_CLK>;
 993				clock-names = "core", "iface";
 994				status = "disabled";
 995
 996				#address-cells = <1>;
 997				#size-cells = <0>;
 998			};
 999
1000			spi@1a280000 {
1001				compatible = "qcom,spi-qup-v1.1.1";
1002				reg = <0x1a280000 0x1000>;
1003				interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
1004
1005				clocks = <&gcc GSBI5_QUP_CLK>, <&gcc GSBI5_H_CLK>;
1006				clock-names = "core", "iface";
1007				status = "disabled";
1008
1009				#address-cells = <1>;
1010				#size-cells = <0>;
1011			};
1012		};
1013
1014		tcsr: syscon@1a400000 {
1015			compatible = "qcom,tcsr-ipq8064", "syscon";
1016			reg = <0x1a400000 0x100>;
1017		};
1018
1019		rng@1a500000 {
1020			compatible = "qcom,prng";
1021			reg = <0x1a500000 0x200>;
1022			clocks = <&gcc PRNG_CLK>;
1023			clock-names = "core";
1024		};
1025
1026		nand: nand-controller@1ac00000 {
1027			compatible = "qcom,ipq806x-nand";
1028			reg = <0x1ac00000 0x800>;
1029
1030			pinctrl-0 = <&nand_pins>;
1031			pinctrl-names = "default";
1032
1033			clocks = <&gcc EBI2_CLK>,
1034				 <&gcc EBI2_AON_CLK>;
1035			clock-names = "core", "aon";
1036
1037			dmas = <&adm_dma 3>;
1038			dma-names = "rxtx";
1039			qcom,cmd-crci = <15>;
1040			qcom,data-crci = <3>;
1041
1042			#address-cells = <1>;
1043			#size-cells = <0>;
1044
1045			status = "disabled";
1046		};
1047
1048		sata_phy: sata-phy@1b400000 {
1049			compatible = "qcom,ipq806x-sata-phy";
1050			reg = <0x1b400000 0x200>;
1051
1052			clocks = <&gcc SATA_PHY_CFG_CLK>;
1053			clock-names = "cfg";
1054
1055			#phy-cells = <0>;
1056			status = "disabled";
1057		};
1058
1059		pcie0: pcie@1b500000 {
1060			compatible = "qcom,pcie-ipq8064";
1061			reg = <0x1b500000 0x1000
1062			       0x1b502000 0x80
1063			       0x1b600000 0x100
1064			       0x0ff00000 0x100000>;
1065			reg-names = "dbi", "elbi", "parf", "config";
1066			device_type = "pci";
1067			linux,pci-domain = <0>;
1068			bus-range = <0x00 0xff>;
1069			num-lanes = <1>;
1070			#address-cells = <3>;
1071			#size-cells = <2>;
1072
1073			ranges = <0x81000000 0x0 0x00000000 0x0fe00000 0x0 0x00010000   /* I/O */
1074				  0x82000000 0x0 0x08000000 0x08000000 0x0 0x07e00000>; /* MEM */
1075
1076			interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
1077			interrupt-names = "msi";
1078			#interrupt-cells = <1>;
1079			interrupt-map-mask = <0 0 0 0x7>;
1080			interrupt-map = <0 0 0 1 &intc GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1081					<0 0 0 2 &intc GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1082					<0 0 0 3 &intc GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1083					<0 0 0 4 &intc GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1084
1085			clocks = <&gcc PCIE_A_CLK>,
1086				 <&gcc PCIE_H_CLK>,
1087				 <&gcc PCIE_PHY_CLK>,
1088				 <&gcc PCIE_AUX_CLK>,
1089				 <&gcc PCIE_ALT_REF_CLK>;
1090			clock-names = "core", "iface", "phy", "aux", "ref";
1091
1092			assigned-clocks = <&gcc PCIE_ALT_REF_CLK>;
1093			assigned-clock-rates = <100000000>;
1094
1095			resets = <&gcc PCIE_ACLK_RESET>,
1096				 <&gcc PCIE_HCLK_RESET>,
1097				 <&gcc PCIE_POR_RESET>,
1098				 <&gcc PCIE_PCI_RESET>,
1099				 <&gcc PCIE_PHY_RESET>,
1100				 <&gcc PCIE_EXT_RESET>;
1101			reset-names = "axi", "ahb", "por", "pci", "phy", "ext";
1102
1103			pinctrl-0 = <&pcie0_pins>;
1104			pinctrl-names = "default";
1105
1106			status = "disabled";
1107			perst-gpios = <&qcom_pinmux 3 GPIO_ACTIVE_LOW>;
1108
1109			pcie@0 {
1110				device_type = "pci";
1111				reg = <0x0 0x0 0x0 0x0 0x0>;
1112				bus-range = <0x01 0xff>;
1113
1114				#address-cells = <3>;
1115				#size-cells = <2>;
1116				ranges;
1117			};
1118		};
1119
1120		pcie1: pcie@1b700000 {
1121			compatible = "qcom,pcie-ipq8064";
1122			reg = <0x1b700000 0x1000
1123			       0x1b702000 0x80
1124			       0x1b800000 0x100
1125			       0x31f00000 0x100000>;
1126			reg-names = "dbi", "elbi", "parf", "config";
1127			device_type = "pci";
1128			linux,pci-domain = <1>;
1129			bus-range = <0x00 0xff>;
1130			num-lanes = <1>;
1131			#address-cells = <3>;
1132			#size-cells = <2>;
1133
1134			ranges = <0x81000000 0x0 0x00000000 0x31e00000 0x0 0x00010000   /* I/O */
1135				  0x82000000 0x0 0x2e000000 0x2e000000 0x0 0x03e00000>; /* MEM */
1136
1137			interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
1138			interrupt-names = "msi";
1139			#interrupt-cells = <1>;
1140			interrupt-map-mask = <0 0 0 0x7>;
1141			interrupt-map = <0 0 0 1 &intc GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1142					<0 0 0 2 &intc GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1143					<0 0 0 3 &intc GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1144					<0 0 0 4 &intc GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1145
1146			clocks = <&gcc PCIE_1_A_CLK>,
1147				 <&gcc PCIE_1_H_CLK>,
1148				 <&gcc PCIE_1_PHY_CLK>,
1149				 <&gcc PCIE_1_AUX_CLK>,
1150				 <&gcc PCIE_1_ALT_REF_CLK>;
1151			clock-names = "core", "iface", "phy", "aux", "ref";
1152
1153			assigned-clocks = <&gcc PCIE_1_ALT_REF_CLK>;
1154			assigned-clock-rates = <100000000>;
1155
1156			resets = <&gcc PCIE_1_ACLK_RESET>,
1157				 <&gcc PCIE_1_HCLK_RESET>,
1158				 <&gcc PCIE_1_POR_RESET>,
1159				 <&gcc PCIE_1_PCI_RESET>,
1160				 <&gcc PCIE_1_PHY_RESET>,
1161				 <&gcc PCIE_1_EXT_RESET>;
1162			reset-names = "axi", "ahb", "por", "pci", "phy", "ext";
1163
1164			pinctrl-0 = <&pcie1_pins>;
1165			pinctrl-names = "default";
1166
1167			status = "disabled";
1168			perst-gpios = <&qcom_pinmux 48 GPIO_ACTIVE_LOW>;
1169
1170			pcie@0 {
1171				device_type = "pci";
1172				reg = <0x0 0x0 0x0 0x0 0x0>;
1173				bus-range = <0x01 0xff>;
1174
1175				#address-cells = <3>;
1176				#size-cells = <2>;
1177				ranges;
1178			};
1179		};
1180
1181		pcie2: pcie@1b900000 {
1182			compatible = "qcom,pcie-ipq8064";
1183			reg = <0x1b900000 0x1000
1184			       0x1b902000 0x80
1185			       0x1ba00000 0x100
1186			       0x35f00000 0x100000>;
1187			reg-names = "dbi", "elbi", "parf", "config";
1188			device_type = "pci";
1189			linux,pci-domain = <2>;
1190			bus-range = <0x00 0xff>;
1191			num-lanes = <1>;
1192			#address-cells = <3>;
1193			#size-cells = <2>;
1194
1195			ranges = <0x81000000 0x0 0x00000000 0x35e00000 0x0 0x00010000   /* I/O */
1196				  0x82000000 0x0 0x32000000 0x32000000 0x0 0x03e00000>; /* MEM */
1197
1198			interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
1199			interrupt-names = "msi";
1200			#interrupt-cells = <1>;
1201			interrupt-map-mask = <0 0 0 0x7>;
1202			interrupt-map = <0 0 0 1 &intc GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1203					<0 0 0 2 &intc GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1204					<0 0 0 3 &intc GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1205					<0 0 0 4 &intc GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1206
1207			clocks = <&gcc PCIE_2_A_CLK>,
1208				 <&gcc PCIE_2_H_CLK>,
1209				 <&gcc PCIE_2_PHY_CLK>,
1210				 <&gcc PCIE_2_AUX_CLK>,
1211				 <&gcc PCIE_2_ALT_REF_CLK>;
1212			clock-names = "core", "iface", "phy", "aux", "ref";
1213
1214			assigned-clocks = <&gcc PCIE_2_ALT_REF_CLK>;
1215			assigned-clock-rates = <100000000>;
1216
1217			resets = <&gcc PCIE_2_ACLK_RESET>,
1218				 <&gcc PCIE_2_HCLK_RESET>,
1219				 <&gcc PCIE_2_POR_RESET>,
1220				 <&gcc PCIE_2_PCI_RESET>,
1221				 <&gcc PCIE_2_PHY_RESET>,
1222				 <&gcc PCIE_2_EXT_RESET>;
1223			reset-names = "axi", "ahb", "por", "pci", "phy", "ext";
1224
1225			pinctrl-0 = <&pcie2_pins>;
1226			pinctrl-names = "default";
1227
1228			status = "disabled";
1229			perst-gpios = <&qcom_pinmux 63 GPIO_ACTIVE_LOW>;
1230
1231			pcie@0 {
1232				device_type = "pci";
1233				reg = <0x0 0x0 0x0 0x0 0x0>;
1234				bus-range = <0x01 0xff>;
1235
1236				#address-cells = <3>;
1237				#size-cells = <2>;
1238				ranges;
1239			};
1240		};
1241
1242		qsgmii_csr: syscon@1bb00000 {
1243			compatible = "syscon";
1244			reg = <0x1bb00000 0x000001FF>;
1245		};
1246
1247		lcc: clock-controller@28000000 {
1248			compatible = "qcom,lcc-ipq8064";
1249			reg = <0x28000000 0x1000>;
1250			#clock-cells = <1>;
1251			#reset-cells = <1>;
1252		};
1253
1254		lpass@28100000 {
1255			compatible = "qcom,lpass-cpu";
1256			status = "disabled";
1257			clocks = <&lcc AHBIX_CLK>,
1258					<&lcc MI2S_OSR_CLK>,
1259					<&lcc MI2S_BIT_CLK>;
1260			clock-names = "ahbix-clk",
1261					"mi2s-osr-clk",
1262					"mi2s-bit-clk";
1263			interrupts = <GIC_SPI 85 IRQ_TYPE_EDGE_RISING>;
1264			interrupt-names = "lpass-irq-lpaif";
1265			reg = <0x28100000 0x10000>;
1266			reg-names = "lpass-lpaif";
1267		};
1268
1269		sata: sata@29000000 {
1270			compatible = "qcom,ipq806x-ahci", "generic-ahci";
1271			reg = <0x29000000 0x180>;
1272
1273			interrupts = <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>;
1274
1275			clocks = <&gcc SFAB_SATA_S_H_CLK>,
1276				 <&gcc SATA_H_CLK>,
1277				 <&gcc SATA_A_CLK>,
1278				 <&gcc SATA_RXOOB_CLK>,
1279				 <&gcc SATA_PMALIVE_CLK>;
1280			clock-names = "slave_iface", "iface", "core",
1281					"rxoob", "pmalive";
1282
1283			assigned-clocks = <&gcc SATA_RXOOB_CLK>, <&gcc SATA_PMALIVE_CLK>;
1284			assigned-clock-rates = <100000000>, <100000000>;
1285
1286			phys = <&sata_phy>;
1287			phy-names = "sata-phy";
1288			status = "disabled";
1289		};
1290
1291		gmac0: ethernet@37000000 {
1292			device_type = "network";
1293			compatible = "qcom,ipq806x-gmac", "snps,dwmac";
1294			reg = <0x37000000 0x200000>;
1295			interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>;
1296			interrupt-names = "macirq";
1297
1298			snps,axi-config = <&stmmac_axi_setup>;
1299			snps,pbl = <32>;
1300			snps,aal;
1301
1302			qcom,nss-common = <&nss_common>;
1303			qcom,qsgmii-csr = <&qsgmii_csr>;
1304
1305			clocks = <&gcc GMAC_CORE1_CLK>;
1306			clock-names = "stmmaceth";
1307
1308			resets = <&gcc GMAC_CORE1_RESET>,
1309				 <&gcc GMAC_AHB_RESET>;
1310			reset-names = "stmmaceth", "ahb";
1311
1312			status = "disabled";
1313		};
1314
1315		gmac1: ethernet@37200000 {
1316			device_type = "network";
1317			compatible = "qcom,ipq806x-gmac", "snps,dwmac";
1318			reg = <0x37200000 0x200000>;
1319			interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
1320			interrupt-names = "macirq";
1321
1322			snps,axi-config = <&stmmac_axi_setup>;
1323			snps,pbl = <32>;
1324			snps,aal;
1325
1326			qcom,nss-common = <&nss_common>;
1327			qcom,qsgmii-csr = <&qsgmii_csr>;
1328
1329			clocks = <&gcc GMAC_CORE2_CLK>;
1330			clock-names = "stmmaceth";
1331
1332			resets = <&gcc GMAC_CORE2_RESET>,
1333				 <&gcc GMAC_AHB_RESET>;
1334			reset-names = "stmmaceth", "ahb";
1335
1336			status = "disabled";
1337		};
1338
1339		gmac2: ethernet@37400000 {
1340			device_type = "network";
1341			compatible = "qcom,ipq806x-gmac", "snps,dwmac";
1342			reg = <0x37400000 0x200000>;
1343			interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
1344			interrupt-names = "macirq";
1345
1346			snps,axi-config = <&stmmac_axi_setup>;
1347			snps,pbl = <32>;
1348			snps,aal;
1349
1350			qcom,nss-common = <&nss_common>;
1351			qcom,qsgmii-csr = <&qsgmii_csr>;
1352
1353			clocks = <&gcc GMAC_CORE3_CLK>;
1354			clock-names = "stmmaceth";
1355
1356			resets = <&gcc GMAC_CORE3_RESET>,
1357				 <&gcc GMAC_AHB_RESET>;
1358			reset-names = "stmmaceth", "ahb";
1359
1360			status = "disabled";
1361		};
1362
1363		gmac3: ethernet@37600000 {
1364			device_type = "network";
1365			compatible = "qcom,ipq806x-gmac", "snps,dwmac";
1366			reg = <0x37600000 0x200000>;
1367			interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
1368			interrupt-names = "macirq";
1369
1370			snps,axi-config = <&stmmac_axi_setup>;
1371			snps,pbl = <32>;
1372			snps,aal;
1373
1374			qcom,nss-common = <&nss_common>;
1375			qcom,qsgmii-csr = <&qsgmii_csr>;
1376
1377			clocks = <&gcc GMAC_CORE4_CLK>;
1378			clock-names = "stmmaceth";
1379
1380			resets = <&gcc GMAC_CORE4_RESET>,
1381				 <&gcc GMAC_AHB_RESET>;
1382			reset-names = "stmmaceth", "ahb";
1383
1384			status = "disabled";
1385		};
1386	};
1387};