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qcom-apq8064.dtsi
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linux-6.19.14/arch/arm/boot/dts/qcom/qcom-apq8064.dtsi
1// SPDX-License-Identifier: GPL-2.0 2/dts-v1/; 3 4#include <dt-bindings/clock/qcom,gcc-msm8960.h> 5#include <dt-bindings/clock/qcom,lcc-msm8960.h> 6#include <dt-bindings/reset/qcom,gcc-msm8960.h> 7#include <dt-bindings/clock/qcom,mmcc-msm8960.h> 8#include <dt-bindings/clock/qcom,rpmcc.h> 9#include <dt-bindings/soc/qcom,gsbi.h> 10#include <dt-bindings/interrupt-controller/irq.h> 11#include <dt-bindings/interrupt-controller/arm-gic.h> 12/ { 13 #address-cells = <1>; 14 #size-cells = <1>; 15 model = "Qualcomm APQ8064"; 16 compatible = "qcom,apq8064"; 17 interrupt-parent = <&intc>; 18 19 reserved-memory { 20 #address-cells = <1>; 21 #size-cells = <1>; 22 ranges; 23 24 smem_region: smem@80000000 { 25 reg = <0x80000000 0x200000>; 26 no-map; 27 }; 28 29 wcnss_mem: wcnss@8f000000 { 30 reg = <0x8f000000 0x700000>; 31 no-map; 32 }; 33 }; 34 35 cpus { 36 #address-cells = <1>; 37 #size-cells = <0>; 38 39 cpu0: cpu@0 { 40 compatible = "qcom,krait"; 41 enable-method = "qcom,kpss-acc-v1"; 42 device_type = "cpu"; 43 reg = <0>; 44 next-level-cache = <&l2>; 45 qcom,acc = <&acc0>; 46 qcom,saw = <&saw0>; 47 cpu-idle-states = <&cpu_spc>; 48 }; 49 50 cpu1: cpu@1 { 51 compatible = "qcom,krait"; 52 enable-method = "qcom,kpss-acc-v1"; 53 device_type = "cpu"; 54 reg = <1>; 55 next-level-cache = <&l2>; 56 qcom,acc = <&acc1>; 57 qcom,saw = <&saw1>; 58 cpu-idle-states = <&cpu_spc>; 59 }; 60 61 cpu2: cpu@2 { 62 compatible = "qcom,krait"; 63 enable-method = "qcom,kpss-acc-v1"; 64 device_type = "cpu"; 65 reg = <2>; 66 next-level-cache = <&l2>; 67 qcom,acc = <&acc2>; 68 qcom,saw = <&saw2>; 69 cpu-idle-states = <&cpu_spc>; 70 }; 71 72 cpu3: cpu@3 { 73 compatible = "qcom,krait"; 74 enable-method = "qcom,kpss-acc-v1"; 75 device_type = "cpu"; 76 reg = <3>; 77 next-level-cache = <&l2>; 78 qcom,acc = <&acc3>; 79 qcom,saw = <&saw3>; 80 cpu-idle-states = <&cpu_spc>; 81 }; 82 83 l2: l2-cache { 84 compatible = "cache"; 85 cache-level = <2>; 86 cache-unified; 87 }; 88 89 idle-states { 90 cpu_spc: cpu-spc { 91 compatible = "qcom,idle-state-spc", 92 "arm,idle-state"; 93 entry-latency-us = <400>; 94 exit-latency-us = <900>; 95 min-residency-us = <3000>; 96 }; 97 }; 98 }; 99 100 memory@0 { 101 device_type = "memory"; 102 reg = <0x0 0x0>; 103 }; 104 105 thermal-zones { 106 cpu0-thermal { 107 polling-delay-passive = <250>; 108 polling-delay = <1000>; 109 110 thermal-sensors = <&tsens 7>; 111 coefficients = <1199 0>; 112 113 trips { 114 cpu_alert0: trip0 { 115 temperature = <75000>; 116 hysteresis = <2000>; 117 type = "passive"; 118 }; 119 cpu_crit0: trip1 { 120 temperature = <110000>; 121 hysteresis = <2000>; 122 type = "critical"; 123 }; 124 }; 125 }; 126 127 cpu1-thermal { 128 polling-delay-passive = <250>; 129 polling-delay = <1000>; 130 131 thermal-sensors = <&tsens 8>; 132 coefficients = <1132 0>; 133 134 trips { 135 cpu_alert1: trip0 { 136 temperature = <75000>; 137 hysteresis = <2000>; 138 type = "passive"; 139 }; 140 cpu_crit1: trip1 { 141 temperature = <110000>; 142 hysteresis = <2000>; 143 type = "critical"; 144 }; 145 }; 146 }; 147 148 cpu2-thermal { 149 polling-delay-passive = <250>; 150 polling-delay = <1000>; 151 152 thermal-sensors = <&tsens 9>; 153 coefficients = <1199 0>; 154 155 trips { 156 cpu_alert2: trip0 { 157 temperature = <75000>; 158 hysteresis = <2000>; 159 type = "passive"; 160 }; 161 cpu_crit2: trip1 { 162 temperature = <110000>; 163 hysteresis = <2000>; 164 type = "critical"; 165 }; 166 }; 167 }; 168 169 cpu3-thermal { 170 polling-delay-passive = <250>; 171 polling-delay = <1000>; 172 173 thermal-sensors = <&tsens 10>; 174 coefficients = <1132 0>; 175 176 trips { 177 cpu_alert3: trip0 { 178 temperature = <75000>; 179 hysteresis = <2000>; 180 type = "passive"; 181 }; 182 cpu_crit3: trip1 { 183 temperature = <110000>; 184 hysteresis = <2000>; 185 type = "critical"; 186 }; 187 }; 188 }; 189 }; 190 191 cpu-pmu { 192 compatible = "qcom,krait-pmu"; 193 interrupts = <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>; 194 }; 195 196 clocks { 197 cxo_board: cxo_board { 198 compatible = "fixed-clock"; 199 #clock-cells = <0>; 200 clock-frequency = <19200000>; 201 }; 202 203 pxo_board: pxo_board { 204 compatible = "fixed-clock"; 205 #clock-cells = <0>; 206 clock-frequency = <27000000>; 207 }; 208 209 sleep_clk: sleep_clk { 210 compatible = "fixed-clock"; 211 #clock-cells = <0>; 212 clock-frequency = <32768>; 213 }; 214 }; 215 216 smem { 217 compatible = "qcom,smem"; 218 memory-region = <&smem_region>; 219 220 hwlocks = <&sfpb_mutex 3>; 221 }; 222 223 smsm { 224 compatible = "qcom,smsm"; 225 226 #address-cells = <1>; 227 #size-cells = <0>; 228 229 qcom,ipc-1 = <&l2cc 8 4>; 230 qcom,ipc-2 = <&l2cc 8 14>; 231 qcom,ipc-3 = <&l2cc 8 23>; 232 qcom,ipc-4 = <&sps_sic_non_secure 0x4094 0>; 233 234 apps_smsm: apps@0 { 235 reg = <0>; 236 #qcom,smem-state-cells = <1>; 237 }; 238 239 modem_smsm: modem@1 { 240 reg = <1>; 241 interrupts = <GIC_SPI 38 IRQ_TYPE_EDGE_RISING>; 242 243 interrupt-controller; 244 #interrupt-cells = <2>; 245 }; 246 247 q6_smsm: q6@2 { 248 reg = <2>; 249 interrupts = <GIC_SPI 89 IRQ_TYPE_EDGE_RISING>; 250 251 interrupt-controller; 252 #interrupt-cells = <2>; 253 }; 254 255 wcnss_smsm: wcnss@3 { 256 reg = <3>; 257 interrupts = <GIC_SPI 204 IRQ_TYPE_EDGE_RISING>; 258 259 interrupt-controller; 260 #interrupt-cells = <2>; 261 }; 262 263 dsps_smsm: dsps@4 { 264 reg = <4>; 265 interrupts = <GIC_SPI 137 IRQ_TYPE_EDGE_RISING>; 266 267 interrupt-controller; 268 #interrupt-cells = <2>; 269 }; 270 }; 271 272 firmware { 273 scm { 274 compatible = "qcom,scm-apq8064", "qcom,scm"; 275 276 clocks = <&rpmcc RPM_DAYTONA_FABRIC_CLK>; 277 clock-names = "core"; 278 }; 279 }; 280 281 replicator { 282 compatible = "arm,coresight-static-replicator"; 283 284 clocks = <&rpmcc RPM_QDSS_CLK>; 285 clock-names = "apb_pclk"; 286 287 in-ports { 288 port { 289 replicator_in: endpoint { 290 remote-endpoint = <&funnel_out>; 291 }; 292 }; 293 }; 294 295 out-ports { 296 #address-cells = <1>; 297 #size-cells = <0>; 298 299 port@0 { 300 reg = <0>; 301 replicator_out0: endpoint { 302 remote-endpoint = <&etb_in>; 303 }; 304 }; 305 306 port@1 { 307 reg = <1>; 308 replicator_out1: endpoint { 309 remote-endpoint = <&tpiu_in>; 310 }; 311 }; 312 }; 313 }; 314 315 soc: soc { 316 #address-cells = <1>; 317 #size-cells = <1>; 318 ranges; 319 compatible = "simple-bus"; 320 321 tlmm_pinmux: pinctrl@800000 { 322 compatible = "qcom,apq8064-pinctrl"; 323 reg = <0x800000 0x4000>; 324 325 gpio-controller; 326 gpio-ranges = <&tlmm_pinmux 0 0 90>; 327 #gpio-cells = <2>; 328 interrupt-controller; 329 #interrupt-cells = <2>; 330 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 331 332 pinctrl-names = "default"; 333 pinctrl-0 = <&ps_hold_default_state>; 334 }; 335 336 sfpb_mutex: hwmutex@1200600 { 337 compatible = "qcom,sfpb-mutex"; 338 reg = <0x01200600 0x100>; 339 #hwlock-cells = <1>; 340 }; 341 342 intc: interrupt-controller@2000000 { 343 compatible = "qcom,msm-qgic2"; 344 interrupt-controller; 345 #address-cells = <0>; 346 #interrupt-cells = <3>; 347 reg = <0x02000000 0x1000>, 348 <0x02002000 0x1000>; 349 }; 350 351 timer@200a000 { 352 compatible = "qcom,kpss-wdt-apq8064", "qcom,kpss-timer", 353 "qcom,msm-timer"; 354 interrupts = <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_EDGE_RISING)>, 355 <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_EDGE_RISING)>, 356 <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_EDGE_RISING)>; 357 reg = <0x0200a000 0x100>; 358 clock-frequency = <27000000>; 359 clocks = <&sleep_clk>; 360 clock-names = "sleep"; 361 cpu-offset = <0x80000>; 362 }; 363 364 acc0: clock-controller@2088000 { 365 compatible = "qcom,kpss-acc-v1"; 366 reg = <0x02088000 0x1000>, <0x02008000 0x1000>; 367 clocks = <&gcc PLL8_VOTE>, <&pxo_board>; 368 clock-names = "pll8_vote", "pxo"; 369 clock-output-names = "acpu0_aux"; 370 #clock-cells = <0>; 371 }; 372 373 acc1: clock-controller@2098000 { 374 compatible = "qcom,kpss-acc-v1"; 375 reg = <0x02098000 0x1000>, <0x02008000 0x1000>; 376 clocks = <&gcc PLL8_VOTE>, <&pxo_board>; 377 clock-names = "pll8_vote", "pxo"; 378 clock-output-names = "acpu1_aux"; 379 #clock-cells = <0>; 380 }; 381 382 acc2: clock-controller@20a8000 { 383 compatible = "qcom,kpss-acc-v1"; 384 reg = <0x020a8000 0x1000>, <0x02008000 0x1000>; 385 clocks = <&gcc PLL8_VOTE>, <&pxo_board>; 386 clock-names = "pll8_vote", "pxo"; 387 clock-output-names = "acpu2_aux"; 388 #clock-cells = <0>; 389 }; 390 391 acc3: clock-controller@20b8000 { 392 compatible = "qcom,kpss-acc-v1"; 393 reg = <0x020b8000 0x1000>, <0x02008000 0x1000>; 394 clocks = <&gcc PLL8_VOTE>, <&pxo_board>; 395 clock-names = "pll8_vote", "pxo"; 396 clock-output-names = "acpu3_aux"; 397 #clock-cells = <0>; 398 }; 399 400 saw0: power-manager@2089000 { 401 compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2"; 402 reg = <0x02089000 0x1000>, <0x02009000 0x1000>; 403 404 saw0_vreg: regulator { 405 regulator-min-microvolt = <850000>; 406 regulator-max-microvolt = <1300000>; 407 }; 408 }; 409 410 saw1: power-manager@2099000 { 411 compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2"; 412 reg = <0x02099000 0x1000>, <0x02009000 0x1000>; 413 414 saw1_vreg: regulator { 415 regulator-min-microvolt = <850000>; 416 regulator-max-microvolt = <1300000>; 417 }; 418 }; 419 420 saw2: power-manager@20a9000 { 421 compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2"; 422 reg = <0x020a9000 0x1000>, <0x02009000 0x1000>; 423 424 saw2_vreg: regulator { 425 regulator-min-microvolt = <850000>; 426 regulator-max-microvolt = <1300000>; 427 }; 428 }; 429 430 saw3: power-manager@20b9000 { 431 compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2"; 432 reg = <0x020b9000 0x1000>, <0x02009000 0x1000>; 433 434 saw3_vreg: regulator { 435 regulator-min-microvolt = <850000>; 436 regulator-max-microvolt = <1300000>; 437 }; 438 }; 439 440 sps_sic_non_secure: interrupt-controller@12100000 { 441 compatible = "qcom,apq8064-sps-sic", "syscon"; 442 reg = <0x12100000 0x10000>; 443 }; 444 445 gsbi1: gsbi@12440000 { 446 status = "disabled"; 447 compatible = "qcom,gsbi-v1.0.0"; 448 cell-index = <1>; 449 reg = <0x12440000 0x100>; 450 clocks = <&gcc GSBI1_H_CLK>; 451 clock-names = "iface"; 452 #address-cells = <1>; 453 #size-cells = <1>; 454 ranges; 455 456 syscon-tcsr = <&tcsr>; 457 458 gsbi1_serial: serial@12450000 { 459 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; 460 reg = <0x12450000 0x100>, 461 <0x12400000 0x03>; 462 interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>; 463 clocks = <&gcc GSBI1_UART_CLK>, <&gcc GSBI1_H_CLK>; 464 clock-names = "core", "iface"; 465 status = "disabled"; 466 }; 467 468 gsbi1_i2c: i2c@12460000 { 469 compatible = "qcom,i2c-qup-v1.1.1"; 470 pinctrl-0 = <&i2c1_default_state>; 471 pinctrl-1 = <&i2c1_sleep_state>; 472 pinctrl-names = "default", "sleep"; 473 reg = <0x12460000 0x1000>; 474 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>; 475 clocks = <&gcc GSBI1_QUP_CLK>, <&gcc GSBI1_H_CLK>; 476 clock-names = "core", "iface"; 477 #address-cells = <1>; 478 #size-cells = <0>; 479 status = "disabled"; 480 }; 481 482 }; 483 484 gsbi2: gsbi@12480000 { 485 status = "disabled"; 486 compatible = "qcom,gsbi-v1.0.0"; 487 cell-index = <2>; 488 reg = <0x12480000 0x100>; 489 clocks = <&gcc GSBI2_H_CLK>; 490 clock-names = "iface"; 491 #address-cells = <1>; 492 #size-cells = <1>; 493 ranges; 494 495 syscon-tcsr = <&tcsr>; 496 497 gsbi2_i2c: i2c@124a0000 { 498 compatible = "qcom,i2c-qup-v1.1.1"; 499 reg = <0x124a0000 0x1000>; 500 pinctrl-0 = <&i2c2_default_state>; 501 pinctrl-1 = <&i2c2_sleep_state>; 502 pinctrl-names = "default", "sleep"; 503 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>; 504 clocks = <&gcc GSBI2_QUP_CLK>, <&gcc GSBI2_H_CLK>; 505 clock-names = "core", "iface"; 506 #address-cells = <1>; 507 #size-cells = <0>; 508 status = "disabled"; 509 }; 510 }; 511 512 gsbi3: gsbi@16200000 { 513 status = "disabled"; 514 compatible = "qcom,gsbi-v1.0.0"; 515 cell-index = <3>; 516 reg = <0x16200000 0x100>; 517 clocks = <&gcc GSBI3_H_CLK>; 518 clock-names = "iface"; 519 #address-cells = <1>; 520 #size-cells = <1>; 521 ranges; 522 gsbi3_i2c: i2c@16280000 { 523 compatible = "qcom,i2c-qup-v1.1.1"; 524 pinctrl-0 = <&i2c3_default_state>; 525 pinctrl-1 = <&i2c3_sleep_state>; 526 pinctrl-names = "default", "sleep"; 527 reg = <0x16280000 0x1000>; 528 interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>; 529 clocks = <&gcc GSBI3_QUP_CLK>, 530 <&gcc GSBI3_H_CLK>; 531 clock-names = "core", "iface"; 532 #address-cells = <1>; 533 #size-cells = <0>; 534 status = "disabled"; 535 }; 536 }; 537 538 gsbi4: gsbi@16300000 { 539 status = "disabled"; 540 compatible = "qcom,gsbi-v1.0.0"; 541 cell-index = <4>; 542 reg = <0x16300000 0x03>; 543 clocks = <&gcc GSBI4_H_CLK>; 544 clock-names = "iface"; 545 #address-cells = <1>; 546 #size-cells = <1>; 547 ranges; 548 549 gsbi4_serial: serial@16340000 { 550 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; 551 reg = <0x16340000 0x100>, 552 <0x16300000 0x3>; 553 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; 554 pinctrl-0 = <&gsbi4_uart_pin_a>; 555 pinctrl-names = "default"; 556 clocks = <&gcc GSBI4_UART_CLK>, <&gcc GSBI4_H_CLK>; 557 clock-names = "core", "iface"; 558 status = "disabled"; 559 }; 560 561 gsbi4_i2c: i2c@16380000 { 562 compatible = "qcom,i2c-qup-v1.1.1"; 563 pinctrl-0 = <&i2c4_default_state>; 564 pinctrl-1 = <&i2c4_sleep_state>; 565 pinctrl-names = "default", "sleep"; 566 reg = <0x16380000 0x1000>; 567 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; 568 clocks = <&gcc GSBI4_QUP_CLK>, 569 <&gcc GSBI4_H_CLK>; 570 clock-names = "core", "iface"; 571 status = "disabled"; 572 }; 573 }; 574 575 gsbi5: gsbi@1a200000 { 576 status = "disabled"; 577 compatible = "qcom,gsbi-v1.0.0"; 578 cell-index = <5>; 579 reg = <0x1a200000 0x03>; 580 clocks = <&gcc GSBI5_H_CLK>; 581 clock-names = "iface"; 582 #address-cells = <1>; 583 #size-cells = <1>; 584 ranges; 585 586 gsbi5_serial: serial@1a240000 { 587 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; 588 reg = <0x1a240000 0x100>, 589 <0x1a200000 0x03>; 590 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; 591 clocks = <&gcc GSBI5_UART_CLK>, <&gcc GSBI5_H_CLK>; 592 clock-names = "core", "iface"; 593 status = "disabled"; 594 }; 595 596 gsbi5_spi: spi@1a280000 { 597 compatible = "qcom,spi-qup-v1.1.1"; 598 reg = <0x1a280000 0x1000>; 599 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 600 pinctrl-0 = <&spi5_default_state>; 601 pinctrl-1 = <&spi5_sleep_state>; 602 pinctrl-names = "default", "sleep"; 603 clocks = <&gcc GSBI5_QUP_CLK>, <&gcc GSBI5_H_CLK>; 604 clock-names = "core", "iface"; 605 status = "disabled"; 606 #address-cells = <1>; 607 #size-cells = <0>; 608 }; 609 }; 610 611 gsbi6: gsbi@16500000 { 612 status = "disabled"; 613 compatible = "qcom,gsbi-v1.0.0"; 614 cell-index = <6>; 615 reg = <0x16500000 0x03>; 616 clocks = <&gcc GSBI6_H_CLK>; 617 clock-names = "iface"; 618 #address-cells = <1>; 619 #size-cells = <1>; 620 ranges; 621 622 gsbi6_serial: serial@16540000 { 623 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; 624 reg = <0x16540000 0x100>, 625 <0x16500000 0x03>; 626 interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>; 627 clocks = <&gcc GSBI6_UART_CLK>, <&gcc GSBI6_H_CLK>; 628 clock-names = "core", "iface"; 629 status = "disabled"; 630 }; 631 632 gsbi6_i2c: i2c@16580000 { 633 compatible = "qcom,i2c-qup-v1.1.1"; 634 pinctrl-0 = <&i2c6_default_state>; 635 pinctrl-1 = <&i2c6_sleep_state>; 636 pinctrl-names = "default", "sleep"; 637 reg = <0x16580000 0x1000>; 638 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>; 639 clocks = <&gcc GSBI6_QUP_CLK>, 640 <&gcc GSBI6_H_CLK>; 641 clock-names = "core", "iface"; 642 status = "disabled"; 643 }; 644 }; 645 646 gsbi7: gsbi@16600000 { 647 status = "disabled"; 648 compatible = "qcom,gsbi-v1.0.0"; 649 cell-index = <7>; 650 reg = <0x16600000 0x100>; 651 clocks = <&gcc GSBI7_H_CLK>; 652 clock-names = "iface"; 653 #address-cells = <1>; 654 #size-cells = <1>; 655 ranges; 656 syscon-tcsr = <&tcsr>; 657 658 gsbi7_serial: serial@16640000 { 659 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; 660 reg = <0x16640000 0x1000>, 661 <0x16600000 0x1000>; 662 interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>; 663 clocks = <&gcc GSBI7_UART_CLK>, <&gcc GSBI7_H_CLK>; 664 clock-names = "core", "iface"; 665 status = "disabled"; 666 }; 667 668 gsbi7_i2c: i2c@16680000 { 669 compatible = "qcom,i2c-qup-v1.1.1"; 670 pinctrl-0 = <&i2c7_default_state>; 671 pinctrl-1 = <&i2c7_sleep_state>; 672 pinctrl-names = "default", "sleep"; 673 reg = <0x16680000 0x1000>; 674 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>; 675 clocks = <&gcc GSBI7_QUP_CLK>, 676 <&gcc GSBI7_H_CLK>; 677 clock-names = "core", "iface"; 678 status = "disabled"; 679 }; 680 }; 681 682 rng@1a500000 { 683 compatible = "qcom,prng"; 684 reg = <0x1a500000 0x200>; 685 clocks = <&gcc PRNG_CLK>; 686 clock-names = "core"; 687 }; 688 689 ssbi2: ssbi@c00000 { 690 compatible = "qcom,ssbi"; 691 reg = <0x00c00000 0x1000>; 692 qcom,controller-type = "pmic-arbiter"; 693 }; 694 695 ssbi: ssbi@500000 { 696 compatible = "qcom,ssbi"; 697 reg = <0x00500000 0x1000>; 698 qcom,controller-type = "pmic-arbiter"; 699 }; 700 701 qfprom: efuse@700000 { 702 compatible = "qcom,apq8064-qfprom", "qcom,qfprom"; 703 reg = <0x00700000 0x1000>; 704 #address-cells = <1>; 705 #size-cells = <1>; 706 707 tsens_calib: calib@404 { 708 reg = <0x404 0x10>; 709 }; 710 tsens_backup: backup-calib@414 { 711 reg = <0x414 0x10>; 712 }; 713 }; 714 715 gcc: clock-controller@900000 { 716 compatible = "qcom,gcc-apq8064", "syscon"; 717 reg = <0x00900000 0x4000>; 718 #clock-cells = <1>; 719 #reset-cells = <1>; 720 clocks = <&cxo_board>, 721 <&pxo_board>, 722 <&lcc PLL4>; 723 clock-names = "cxo", "pxo", "pll4"; 724 725 tsens: thermal-sensor { 726 compatible = "qcom,msm8960-tsens"; 727 728 nvmem-cells = <&tsens_calib>, <&tsens_backup>; 729 nvmem-cell-names = "calib", "calib_backup"; 730 interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>; 731 interrupt-names = "uplow"; 732 733 #qcom,sensors = <11>; 734 #thermal-sensor-cells = <1>; 735 }; 736 }; 737 738 lcc: clock-controller@28000000 { 739 compatible = "qcom,lcc-apq8064"; 740 reg = <0x28000000 0x1000>; 741 #clock-cells = <1>; 742 #reset-cells = <1>; 743 clocks = <&pxo_board>, 744 <&gcc PLL4_VOTE>, 745 <0>, 746 <0>, <0>, 747 <0>, <0>, 748 <0>; 749 clock-names = "pxo", 750 "pll4_vote", 751 "mi2s_codec_clk", 752 "codec_i2s_mic_codec_clk", 753 "spare_i2s_mic_codec_clk", 754 "codec_i2s_spkr_codec_clk", 755 "spare_i2s_spkr_codec_clk", 756 "pcm_codec_clk"; 757 }; 758 759 mmcc: clock-controller@4000000 { 760 compatible = "qcom,mmcc-apq8064"; 761 reg = <0x4000000 0x1000>; 762 #clock-cells = <1>; 763 #power-domain-cells = <1>; 764 #reset-cells = <1>; 765 clocks = <&pxo_board>, 766 <&gcc PLL3>, 767 <&gcc PLL8_VOTE>, 768 <&dsi0_phy 1>, 769 <&dsi0_phy 0>, 770 <&dsi1_phy 1>, 771 <&dsi1_phy 0>, 772 <&hdmi_phy>, 773 <&mdp>; 774 clock-names = "pxo", 775 "pll3", 776 "pll8_vote", 777 "dsi1pll", 778 "dsi1pllbyte", 779 "dsi2pll", 780 "dsi2pllbyte", 781 "hdmipll", 782 "lvdspll"; 783 }; 784 785 l2cc: clock-controller@2011000 { 786 compatible = "qcom,kpss-gcc-apq8064", "qcom,kpss-gcc", "syscon"; 787 reg = <0x2011000 0x1000>; 788 clocks = <&gcc PLL8_VOTE>, <&pxo_board>; 789 clock-names = "pll8_vote", "pxo"; 790 #clock-cells = <0>; 791 }; 792 793 rpm: rpm@108000 { 794 compatible = "qcom,rpm-apq8064"; 795 reg = <0x108000 0x1000>; 796 qcom,ipc = <&l2cc 0x8 2>; 797 798 interrupts = <GIC_SPI 19 IRQ_TYPE_EDGE_RISING>, 799 <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>, 800 <GIC_SPI 22 IRQ_TYPE_EDGE_RISING>; 801 interrupt-names = "ack", "err", "wakeup"; 802 803 rpmcc: clock-controller { 804 compatible = "qcom,rpmcc-apq8064", "qcom,rpmcc"; 805 #clock-cells = <1>; 806 clocks = <&pxo_board>, <&cxo_board>; 807 clock-names = "pxo", "cxo"; 808 }; 809 }; 810 811 usb1: usb@12500000 { 812 compatible = "qcom,ci-hdrc"; 813 reg = <0x12500000 0x200>, 814 <0x12500200 0x200>; 815 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; 816 clocks = <&gcc USB_HS1_XCVR_CLK>, <&gcc USB_HS1_H_CLK>; 817 clock-names = "core", "iface"; 818 assigned-clocks = <&gcc USB_HS1_XCVR_CLK>; 819 assigned-clock-rates = <60000000>; 820 resets = <&gcc USB_HS1_RESET>; 821 reset-names = "core"; 822 phy_type = "ulpi"; 823 ahb-burst-config = <0>; 824 phys = <&usb_hs1_phy>; 825 phy-names = "usb-phy"; 826 status = "disabled"; 827 #reset-cells = <1>; 828 829 ulpi { 830 usb_hs1_phy: phy { 831 compatible = "qcom,usb-hs-phy-apq8064", 832 "qcom,usb-hs-phy"; 833 clocks = <&sleep_clk>, <&cxo_board>; 834 clock-names = "sleep", "ref"; 835 resets = <&usb1 0>; 836 reset-names = "por"; 837 #phy-cells = <0>; 838 }; 839 }; 840 }; 841 842 usb3: usb@12520000 { 843 compatible = "qcom,ci-hdrc"; 844 reg = <0x12520000 0x200>, 845 <0x12520200 0x200>; 846 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>; 847 clocks = <&gcc USB_HS3_XCVR_CLK>, <&gcc USB_HS3_H_CLK>; 848 clock-names = "core", "iface"; 849 assigned-clocks = <&gcc USB_HS3_XCVR_CLK>; 850 assigned-clock-rates = <60000000>; 851 resets = <&gcc USB_HS3_RESET>; 852 reset-names = "core"; 853 phy_type = "ulpi"; 854 ahb-burst-config = <0>; 855 phys = <&usb_hs3_phy>; 856 phy-names = "usb-phy"; 857 status = "disabled"; 858 #reset-cells = <1>; 859 860 ulpi { 861 usb_hs3_phy: phy { 862 compatible = "qcom,usb-hs-phy-apq8064", 863 "qcom,usb-hs-phy"; 864 #phy-cells = <0>; 865 clocks = <&sleep_clk>, <&cxo_board>; 866 clock-names = "sleep", "ref"; 867 resets = <&usb3 0>; 868 reset-names = "por"; 869 }; 870 }; 871 }; 872 873 usb4: usb@12530000 { 874 compatible = "qcom,ci-hdrc"; 875 reg = <0x12530000 0x200>, 876 <0x12530200 0x200>; 877 interrupts = <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>; 878 clocks = <&gcc USB_HS4_XCVR_CLK>, <&gcc USB_HS4_H_CLK>; 879 clock-names = "core", "iface"; 880 assigned-clocks = <&gcc USB_HS4_XCVR_CLK>; 881 assigned-clock-rates = <60000000>; 882 resets = <&gcc USB_HS4_RESET>; 883 reset-names = "core"; 884 phy_type = "ulpi"; 885 ahb-burst-config = <0>; 886 phys = <&usb_hs4_phy>; 887 phy-names = "usb-phy"; 888 status = "disabled"; 889 #reset-cells = <1>; 890 891 ulpi { 892 usb_hs4_phy: phy { 893 compatible = "qcom,usb-hs-phy-apq8064", 894 "qcom,usb-hs-phy"; 895 #phy-cells = <0>; 896 clocks = <&sleep_clk>, <&cxo_board>; 897 clock-names = "sleep", "ref"; 898 resets = <&usb4 0>; 899 reset-names = "por"; 900 }; 901 }; 902 }; 903 904 sata_phy0: phy@1b400000 { 905 compatible = "qcom,apq8064-sata-phy"; 906 status = "disabled"; 907 reg = <0x1b400000 0x200>; 908 clocks = <&gcc SATA_PHY_CFG_CLK>; 909 clock-names = "cfg"; 910 #phy-cells = <0>; 911 }; 912 913 sata0: sata@29000000 { 914 compatible = "qcom,apq8064-ahci", "generic-ahci"; 915 status = "disabled"; 916 reg = <0x29000000 0x180>; 917 interrupts = <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>; 918 919 clocks = <&gcc SFAB_SATA_S_H_CLK>, 920 <&gcc SATA_H_CLK>, 921 <&gcc SATA_A_CLK>, 922 <&gcc SATA_RXOOB_CLK>, 923 <&gcc SATA_PMALIVE_CLK>; 924 clock-names = "slave_iface", 925 "iface", 926 "core", 927 "rxoob", 928 "pmalive"; 929 930 assigned-clocks = <&gcc SATA_RXOOB_CLK>, 931 <&gcc SATA_PMALIVE_CLK>; 932 assigned-clock-rates = <100000000>, <100000000>; 933 934 phys = <&sata_phy0>; 935 phy-names = "sata-phy"; 936 ports-implemented = <0x1>; 937 }; 938 939 sdcc3: mmc@12180000 { 940 compatible = "arm,pl18x", "arm,primecell"; 941 arm,primecell-periphid = <0x00051180>; 942 status = "disabled"; 943 reg = <0x12180000 0x2000>; 944 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; 945 clocks = <&gcc SDC3_CLK>, <&gcc SDC3_H_CLK>; 946 clock-names = "mclk", "apb_pclk"; 947 bus-width = <4>; 948 cap-sd-highspeed; 949 cap-mmc-highspeed; 950 max-frequency = <192000000>; 951 no-1-8-v; 952 dmas = <&sdcc3bam 2>, <&sdcc3bam 1>; 953 dma-names = "tx", "rx"; 954 }; 955 956 sdcc3bam: dma-controller@12182000 { 957 compatible = "qcom,bam-v1.3.0"; 958 reg = <0x12182000 0x8000>; 959 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 960 clocks = <&gcc SDC3_H_CLK>; 961 clock-names = "bam_clk"; 962 #dma-cells = <1>; 963 qcom,ee = <0>; 964 }; 965 966 sdcc4: mmc@121c0000 { 967 compatible = "arm,pl18x", "arm,primecell"; 968 arm,primecell-periphid = <0x00051180>; 969 status = "disabled"; 970 reg = <0x121c0000 0x2000>; 971 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; 972 clocks = <&gcc SDC4_CLK>, <&gcc SDC4_H_CLK>; 973 clock-names = "mclk", "apb_pclk"; 974 bus-width = <4>; 975 cap-sd-highspeed; 976 cap-mmc-highspeed; 977 max-frequency = <48000000>; 978 dmas = <&sdcc4bam 2>, <&sdcc4bam 1>; 979 dma-names = "tx", "rx"; 980 pinctrl-names = "default"; 981 pinctrl-0 = <&sdc4_default_state>; 982 }; 983 984 sdcc4bam: dma-controller@121c2000 { 985 compatible = "qcom,bam-v1.3.0"; 986 reg = <0x121c2000 0x8000>; 987 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 988 clocks = <&gcc SDC4_H_CLK>; 989 clock-names = "bam_clk"; 990 #dma-cells = <1>; 991 qcom,ee = <0>; 992 }; 993 994 sdcc1: mmc@12400000 { 995 status = "disabled"; 996 compatible = "arm,pl18x", "arm,primecell"; 997 pinctrl-names = "default"; 998 pinctrl-0 = <&sdcc1_default_state>; 999 arm,primecell-periphid = <0x00051180>; 1000 reg = <0x12400000 0x2000>; 1001 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>; 1002 clocks = <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>; 1003 clock-names = "mclk", "apb_pclk"; 1004 bus-width = <8>; 1005 max-frequency = <96000000>; 1006 non-removable; 1007 cap-sd-highspeed; 1008 cap-mmc-highspeed; 1009 dmas = <&sdcc1bam 2>, <&sdcc1bam 1>; 1010 dma-names = "tx", "rx"; 1011 }; 1012 1013 sdcc1bam: dma-controller@12402000 { 1014 compatible = "qcom,bam-v1.3.0"; 1015 reg = <0x12402000 0x8000>; 1016 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 1017 clocks = <&gcc SDC1_H_CLK>; 1018 clock-names = "bam_clk"; 1019 #dma-cells = <1>; 1020 qcom,ee = <0>; 1021 }; 1022 1023 tcsr: syscon@1a400000 { 1024 compatible = "qcom,tcsr-apq8064", "syscon"; 1025 reg = <0x1a400000 0x100>; 1026 }; 1027 1028 gpu: gpu@4300000 { 1029 compatible = "qcom,adreno-320.2", "qcom,adreno"; 1030 reg = <0x04300000 0x20000>; 1031 reg-names = "kgsl_3d0_reg_memory"; 1032 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; 1033 interrupt-names = "kgsl_3d0_irq"; 1034 clock-names = 1035 "core", 1036 "iface", 1037 "mem", 1038 "mem_iface"; 1039 clocks = 1040 <&mmcc GFX3D_CLK>, 1041 <&mmcc GFX3D_AHB_CLK>, 1042 <&mmcc GFX3D_AXI_CLK>, 1043 <&mmcc MMSS_IMEM_AHB_CLK>; 1044 1045 iommus = <&gfx3d 0 1046 &gfx3d 1 1047 &gfx3d 2 1048 &gfx3d 3 1049 &gfx3d 4 1050 &gfx3d 5 1051 &gfx3d 6 1052 &gfx3d 7 1053 &gfx3d 8 1054 &gfx3d 9 1055 &gfx3d 10 1056 &gfx3d 11 1057 &gfx3d 12 1058 &gfx3d 13 1059 &gfx3d 14 1060 &gfx3d 15 1061 &gfx3d 16 1062 &gfx3d 17 1063 &gfx3d 18 1064 &gfx3d 19 1065 &gfx3d 20 1066 &gfx3d 21 1067 &gfx3d 22 1068 &gfx3d 23 1069 &gfx3d 24 1070 &gfx3d 25 1071 &gfx3d 26 1072 &gfx3d 27 1073 &gfx3d 28 1074 &gfx3d 29 1075 &gfx3d 30 1076 &gfx3d 31 1077 &gfx3d1 0 1078 &gfx3d1 1 1079 &gfx3d1 2 1080 &gfx3d1 3 1081 &gfx3d1 4 1082 &gfx3d1 5 1083 &gfx3d1 6 1084 &gfx3d1 7 1085 &gfx3d1 8 1086 &gfx3d1 9 1087 &gfx3d1 10 1088 &gfx3d1 11 1089 &gfx3d1 12 1090 &gfx3d1 13 1091 &gfx3d1 14 1092 &gfx3d1 15 1093 &gfx3d1 16 1094 &gfx3d1 17 1095 &gfx3d1 18 1096 &gfx3d1 19 1097 &gfx3d1 20 1098 &gfx3d1 21 1099 &gfx3d1 22 1100 &gfx3d1 23 1101 &gfx3d1 24 1102 &gfx3d1 25 1103 &gfx3d1 26 1104 &gfx3d1 27 1105 &gfx3d1 28 1106 &gfx3d1 29 1107 &gfx3d1 30 1108 &gfx3d1 31>; 1109 1110 operating-points-v2 = <&gpu_opp_table>; 1111 1112 gpu_opp_table: opp-table { 1113 compatible = "operating-points-v2"; 1114 1115 opp-450000000 { 1116 opp-hz = /bits/ 64 <450000000>; 1117 }; 1118 1119 opp-27000000 { 1120 opp-hz = /bits/ 64 <27000000>; 1121 }; 1122 }; 1123 }; 1124 1125 mmss_sfpb: syscon@5700000 { 1126 compatible = "qcom,apq8064-mmss-sfpb", "syscon"; 1127 reg = <0x5700000 0x70>; 1128 }; 1129 1130 dsi0: dsi@4700000 { 1131 compatible = "qcom,apq8064-dsi-ctrl", 1132 "qcom,mdss-dsi-ctrl"; 1133 #address-cells = <1>; 1134 #size-cells = <0>; 1135 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 1136 reg = <0x04700000 0x200>; 1137 reg-names = "dsi_ctrl"; 1138 1139 clocks = <&mmcc DSI_M_AHB_CLK>, 1140 <&mmcc DSI_S_AHB_CLK>, 1141 <&mmcc AMP_AHB_CLK>, 1142 <&mmcc DSI_CLK>, 1143 <&mmcc DSI1_BYTE_CLK>, 1144 <&mmcc DSI_PIXEL_CLK>, 1145 <&mmcc DSI1_ESC_CLK>; 1146 clock-names = "iface", "bus", "core_mmss", 1147 "src", "byte", "pixel", 1148 "core"; 1149 1150 assigned-clocks = <&mmcc DSI1_BYTE_SRC>, 1151 <&mmcc DSI1_ESC_SRC>, 1152 <&mmcc DSI_SRC>, 1153 <&mmcc DSI_PIXEL_SRC>; 1154 assigned-clock-parents = <&dsi0_phy 0>, 1155 <&dsi0_phy 0>, 1156 <&dsi0_phy 1>, 1157 <&dsi0_phy 1>; 1158 syscon-sfpb = <&mmss_sfpb>; 1159 phys = <&dsi0_phy>; 1160 status = "disabled"; 1161 1162 ports { 1163 #address-cells = <1>; 1164 #size-cells = <0>; 1165 1166 port@0 { 1167 reg = <0>; 1168 dsi0_in: endpoint { 1169 }; 1170 }; 1171 1172 port@1 { 1173 reg = <1>; 1174 dsi0_out: endpoint { 1175 }; 1176 }; 1177 }; 1178 }; 1179 1180 1181 dsi0_phy: phy@4700200 { 1182 compatible = "qcom,dsi-phy-28nm-8960"; 1183 #clock-cells = <1>; 1184 #phy-cells = <0>; 1185 1186 reg = <0x04700200 0x100>, 1187 <0x04700300 0x200>, 1188 <0x04700500 0x5c>; 1189 reg-names = "dsi_pll", "dsi_phy", "dsi_phy_regulator"; 1190 clock-names = "iface", "ref"; 1191 clocks = <&mmcc DSI_M_AHB_CLK>, 1192 <&pxo_board>; 1193 status = "disabled"; 1194 }; 1195 1196 dsi1: dsi@5800000 { 1197 compatible = "qcom,mdss-dsi-ctrl"; 1198 interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>; 1199 reg = <0x05800000 0x200>; 1200 reg-names = "dsi_ctrl"; 1201 1202 clocks = <&mmcc DSI2_M_AHB_CLK>, 1203 <&mmcc DSI2_S_AHB_CLK>, 1204 <&mmcc AMP_AHB_CLK>, 1205 <&mmcc DSI2_CLK>, 1206 <&mmcc DSI2_BYTE_CLK>, 1207 <&mmcc DSI2_PIXEL_CLK>, 1208 <&mmcc DSI2_ESC_CLK>; 1209 clock-names = "iface", 1210 "bus", 1211 "core_mmss", 1212 "src", 1213 "byte", 1214 "pixel", 1215 "core"; 1216 1217 assigned-clocks = <&mmcc DSI2_BYTE_SRC>, 1218 <&mmcc DSI2_ESC_SRC>, 1219 <&mmcc DSI2_SRC>, 1220 <&mmcc DSI2_PIXEL_SRC>; 1221 assigned-clock-parents = <&dsi1_phy 0>, 1222 <&dsi1_phy 0>, 1223 <&dsi1_phy 1>, 1224 <&dsi1_phy 1>; 1225 1226 syscon-sfpb = <&mmss_sfpb>; 1227 phys = <&dsi1_phy>; 1228 1229 #address-cells = <1>; 1230 #size-cells = <0>; 1231 1232 status = "disabled"; 1233 1234 ports { 1235 #address-cells = <1>; 1236 #size-cells = <0>; 1237 1238 port@0 { 1239 reg = <0>; 1240 dsi1_in: endpoint { 1241 }; 1242 }; 1243 1244 port@1 { 1245 reg = <1>; 1246 dsi1_out: endpoint { 1247 }; 1248 }; 1249 }; 1250 }; 1251 1252 1253 dsi1_phy: dsi-phy@5800200 { 1254 compatible = "qcom,dsi-phy-28nm-8960"; 1255 reg = <0x05800200 0x100>, 1256 <0x05800300 0x200>, 1257 <0x05800500 0x5c>; 1258 reg-names = "dsi_pll", 1259 "dsi_phy", 1260 "dsi_phy_regulator"; 1261 clock-names = "iface", 1262 "ref"; 1263 clocks = <&mmcc DSI2_M_AHB_CLK>, 1264 <&pxo_board>; 1265 #clock-cells = <1>; 1266 #phy-cells = <0>; 1267 1268 status = "disabled"; 1269 }; 1270 1271 mdp_port0: iommu@7500000 { 1272 compatible = "qcom,apq8064-iommu"; 1273 #iommu-cells = <1>; 1274 clock-names = 1275 "smmu_pclk", 1276 "iommu_clk"; 1277 clocks = 1278 <&mmcc SMMU_AHB_CLK>, 1279 <&mmcc MDP_AXI_CLK>; 1280 reg = <0x07500000 0x100000>; 1281 interrupts = 1282 <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>, 1283 <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 1284 qcom,ncb = <2>; 1285 }; 1286 1287 mdp_port1: iommu@7600000 { 1288 compatible = "qcom,apq8064-iommu"; 1289 #iommu-cells = <1>; 1290 clock-names = 1291 "smmu_pclk", 1292 "iommu_clk"; 1293 clocks = 1294 <&mmcc SMMU_AHB_CLK>, 1295 <&mmcc MDP_AXI_CLK>; 1296 reg = <0x07600000 0x100000>; 1297 interrupts = 1298 <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>, 1299 <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 1300 qcom,ncb = <2>; 1301 }; 1302 1303 gfx3d: iommu@7c00000 { 1304 compatible = "qcom,apq8064-iommu"; 1305 #iommu-cells = <1>; 1306 clock-names = 1307 "smmu_pclk", 1308 "iommu_clk"; 1309 clocks = 1310 <&mmcc SMMU_AHB_CLK>, 1311 <&mmcc GFX3D_AXI_CLK>; 1312 reg = <0x07c00000 0x100000>; 1313 interrupts = 1314 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>, 1315 <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; 1316 qcom,ncb = <3>; 1317 }; 1318 1319 gfx3d1: iommu@7d00000 { 1320 compatible = "qcom,apq8064-iommu"; 1321 #iommu-cells = <1>; 1322 clock-names = 1323 "smmu_pclk", 1324 "iommu_clk"; 1325 clocks = 1326 <&mmcc SMMU_AHB_CLK>, 1327 <&mmcc GFX3D_AXI_CLK>; 1328 reg = <0x07d00000 0x100000>; 1329 interrupts = 1330 <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>, 1331 <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>; 1332 qcom,ncb = <3>; 1333 }; 1334 1335 pcie: pcie@1b500000 { 1336 compatible = "qcom,pcie-apq8064"; 1337 reg = <0x1b500000 0x1000>, 1338 <0x1b502000 0x80>, 1339 <0x1b600000 0x100>, 1340 <0x0ff00000 0x100000>; 1341 reg-names = "dbi", "elbi", "parf", "config"; 1342 device_type = "pci"; 1343 linux,pci-domain = <0>; 1344 bus-range = <0x00 0xff>; 1345 num-lanes = <1>; 1346 #address-cells = <3>; 1347 #size-cells = <2>; 1348 ranges = <0x81000000 0x0 0x00000000 0x0fe00000 0x0 0x00100000>, /* I/O */ 1349 <0x82000000 0x0 0x08000000 0x08000000 0x0 0x07e00000>; /* mem */ 1350 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>; 1351 interrupt-names = "msi"; 1352 #interrupt-cells = <1>; 1353 interrupt-map-mask = <0 0 0 0x7>; 1354 interrupt-map = <0 0 0 1 &intc GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 1355 <0 0 0 2 &intc GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 1356 <0 0 0 3 &intc GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 1357 <0 0 0 4 &intc GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 1358 clocks = <&gcc PCIE_A_CLK>, 1359 <&gcc PCIE_H_CLK>, 1360 <&gcc PCIE_PHY_REF_CLK>; 1361 clock-names = "core", "iface", "phy"; 1362 resets = <&gcc PCIE_ACLK_RESET>, 1363 <&gcc PCIE_HCLK_RESET>, 1364 <&gcc PCIE_POR_RESET>, 1365 <&gcc PCIE_PCI_RESET>, 1366 <&gcc PCIE_PHY_RESET>; 1367 reset-names = "axi", "ahb", "por", "pci", "phy"; 1368 status = "disabled"; 1369 1370 pcie@0 { 1371 device_type = "pci"; 1372 reg = <0x0 0x0 0x0 0x0 0x0>; 1373 bus-range = <0x01 0xff>; 1374 1375 #address-cells = <3>; 1376 #size-cells = <2>; 1377 ranges; 1378 }; 1379 }; 1380 1381 hdmi: hdmi-tx@4a00000 { 1382 compatible = "qcom,hdmi-tx-8960"; 1383 pinctrl-names = "default"; 1384 pinctrl-0 = <&hdmi_pinctrl>; 1385 reg = <0x04a00000 0x2f0>; 1386 reg-names = "core_physical"; 1387 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; 1388 clocks = <&mmcc HDMI_APP_CLK>, 1389 <&mmcc HDMI_M_AHB_CLK>, 1390 <&mmcc HDMI_S_AHB_CLK>; 1391 clock-names = "core", 1392 "master_iface", 1393 "slave_iface"; 1394 1395 phys = <&hdmi_phy>; 1396 1397 status = "disabled"; 1398 1399 ports { 1400 #address-cells = <1>; 1401 #size-cells = <0>; 1402 1403 port@0 { 1404 reg = <0>; 1405 hdmi_in: endpoint { 1406 }; 1407 }; 1408 1409 port@1 { 1410 reg = <1>; 1411 hdmi_out: endpoint { 1412 }; 1413 }; 1414 }; 1415 }; 1416 1417 hdmi_phy: phy@4a00400 { 1418 compatible = "qcom,hdmi-phy-8960"; 1419 reg = <0x4a00400 0x60>, 1420 <0x4a00500 0x100>; 1421 reg-names = "hdmi_phy", 1422 "hdmi_pll"; 1423 1424 clocks = <&mmcc HDMI_S_AHB_CLK>; 1425 clock-names = "slave_iface"; 1426 #phy-cells = <0>; 1427 #clock-cells = <0>; 1428 1429 status = "disabled"; 1430 }; 1431 1432 mdp: display-controller@5100000 { 1433 compatible = "qcom,mdp4"; 1434 reg = <0x05100000 0xf0000>; 1435 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 1436 clocks = <&mmcc MDP_CLK>, 1437 <&mmcc MDP_AHB_CLK>, 1438 <&mmcc MDP_AXI_CLK>, 1439 <&mmcc MDP_LUT_CLK>, 1440 <&mmcc HDMI_TV_CLK>, 1441 <&mmcc MDP_TV_CLK>, 1442 <&mmcc LVDS_CLK>, 1443 <&rpmcc RPM_PXO_CLK>; 1444 clock-names = "core_clk", 1445 "iface_clk", 1446 "bus_clk", 1447 "lut_clk", 1448 "hdmi_clk", 1449 "tv_clk", 1450 "lcdc_clk", 1451 "pxo"; 1452 1453 #clock-cells = <0>; 1454 1455 iommus = <&mdp_port0 0 1456 &mdp_port0 2 1457 &mdp_port1 0 1458 &mdp_port1 2>; 1459 1460 ports { 1461 #address-cells = <1>; 1462 #size-cells = <0>; 1463 1464 port@0 { 1465 reg = <0>; 1466 mdp_lvds_out: endpoint { 1467 }; 1468 }; 1469 1470 port@1 { 1471 reg = <1>; 1472 mdp_dsi1_out: endpoint { 1473 }; 1474 }; 1475 1476 port@2 { 1477 reg = <2>; 1478 mdp_dsi2_out: endpoint { 1479 }; 1480 }; 1481 1482 port@3 { 1483 reg = <3>; 1484 mdp_dtv_out: endpoint { 1485 }; 1486 }; 1487 }; 1488 }; 1489 1490 riva: riva-pil@3200800 { 1491 compatible = "qcom,riva-pil"; 1492 1493 reg = <0x03200800 0x1000>, <0x03202000 0x2000>, <0x03204000 0x100>; 1494 reg-names = "ccu", "dxe", "pmu"; 1495 1496 interrupts-extended = <&intc GIC_SPI 199 IRQ_TYPE_EDGE_RISING>, 1497 <&wcnss_smsm 6 IRQ_TYPE_EDGE_RISING>; 1498 interrupt-names = "wdog", "fatal"; 1499 1500 memory-region = <&wcnss_mem>; 1501 1502 status = "disabled"; 1503 1504 iris { 1505 compatible = "qcom,wcn3660"; 1506 1507 clocks = <&cxo_board>; 1508 clock-names = "xo"; 1509 }; 1510 1511 smd-edge { 1512 interrupts = <GIC_SPI 198 IRQ_TYPE_EDGE_RISING>; 1513 1514 qcom,ipc = <&l2cc 8 25>; 1515 qcom,smd-edge = <6>; 1516 1517 label = "riva"; 1518 1519 wcnss { 1520 compatible = "qcom,wcnss"; 1521 qcom,smd-channels = "WCNSS_CTRL"; 1522 1523 qcom,mmio = <&riva>; 1524 1525 bluetooth { 1526 compatible = "qcom,wcnss-bt"; 1527 }; 1528 1529 wifi { 1530 compatible = "qcom,wcnss-wlan"; 1531 1532 interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>, 1533 <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>; 1534 interrupt-names = "tx", "rx"; 1535 1536 qcom,smem-states = <&apps_smsm 10>, <&apps_smsm 9>; 1537 qcom,smem-state-names = "tx-enable", "tx-rings-empty"; 1538 }; 1539 }; 1540 }; 1541 }; 1542 1543 etb@1a01000 { 1544 compatible = "arm,coresight-etb10", "arm,primecell"; 1545 reg = <0x1a01000 0x1000>; 1546 1547 clocks = <&rpmcc RPM_QDSS_CLK>; 1548 clock-names = "apb_pclk"; 1549 1550 in-ports { 1551 port { 1552 etb_in: endpoint { 1553 remote-endpoint = <&replicator_out0>; 1554 }; 1555 }; 1556 }; 1557 }; 1558 1559 tpiu@1a03000 { 1560 compatible = "arm,coresight-tpiu", "arm,primecell"; 1561 reg = <0x1a03000 0x1000>; 1562 1563 clocks = <&rpmcc RPM_QDSS_CLK>; 1564 clock-names = "apb_pclk"; 1565 1566 in-ports { 1567 port { 1568 tpiu_in: endpoint { 1569 remote-endpoint = <&replicator_out1>; 1570 }; 1571 }; 1572 }; 1573 }; 1574 1575 funnel@1a04000 { 1576 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 1577 reg = <0x1a04000 0x1000>; 1578 1579 clocks = <&rpmcc RPM_QDSS_CLK>; 1580 clock-names = "apb_pclk"; 1581 1582 in-ports { 1583 #address-cells = <1>; 1584 #size-cells = <0>; 1585 1586 /* 1587 * Not described input ports: 1588 * 2 - connected to STM component 1589 * 3 - not-connected 1590 * 6 - not-connected 1591 * 7 - not-connected 1592 */ 1593 port@0 { 1594 reg = <0>; 1595 funnel_in0: endpoint { 1596 remote-endpoint = <&etm0_out>; 1597 }; 1598 }; 1599 port@1 { 1600 reg = <1>; 1601 funnel_in1: endpoint { 1602 remote-endpoint = <&etm1_out>; 1603 }; 1604 }; 1605 port@4 { 1606 reg = <4>; 1607 funnel_in4: endpoint { 1608 remote-endpoint = <&etm2_out>; 1609 }; 1610 }; 1611 port@5 { 1612 reg = <5>; 1613 funnel_in5: endpoint { 1614 remote-endpoint = <&etm3_out>; 1615 }; 1616 }; 1617 }; 1618 1619 out-ports { 1620 port { 1621 funnel_out: endpoint { 1622 remote-endpoint = <&replicator_in>; 1623 }; 1624 }; 1625 }; 1626 }; 1627 1628 etm@1a1c000 { 1629 compatible = "arm,coresight-etm3x", "arm,primecell"; 1630 reg = <0x1a1c000 0x1000>; 1631 1632 clocks = <&rpmcc RPM_QDSS_CLK>; 1633 clock-names = "apb_pclk"; 1634 1635 cpu = <&cpu0>; 1636 1637 out-ports { 1638 port { 1639 etm0_out: endpoint { 1640 remote-endpoint = <&funnel_in0>; 1641 }; 1642 }; 1643 }; 1644 }; 1645 1646 etm@1a1d000 { 1647 compatible = "arm,coresight-etm3x", "arm,primecell"; 1648 reg = <0x1a1d000 0x1000>; 1649 1650 clocks = <&rpmcc RPM_QDSS_CLK>; 1651 clock-names = "apb_pclk"; 1652 1653 cpu = <&cpu1>; 1654 1655 out-ports { 1656 port { 1657 etm1_out: endpoint { 1658 remote-endpoint = <&funnel_in1>; 1659 }; 1660 }; 1661 }; 1662 }; 1663 1664 etm@1a1e000 { 1665 compatible = "arm,coresight-etm3x", "arm,primecell"; 1666 reg = <0x1a1e000 0x1000>; 1667 1668 clocks = <&rpmcc RPM_QDSS_CLK>; 1669 clock-names = "apb_pclk"; 1670 1671 cpu = <&cpu2>; 1672 1673 out-ports { 1674 port { 1675 etm2_out: endpoint { 1676 remote-endpoint = <&funnel_in4>; 1677 }; 1678 }; 1679 }; 1680 }; 1681 1682 etm@1a1f000 { 1683 compatible = "arm,coresight-etm3x", "arm,primecell"; 1684 reg = <0x1a1f000 0x1000>; 1685 1686 clocks = <&rpmcc RPM_QDSS_CLK>; 1687 clock-names = "apb_pclk"; 1688 1689 cpu = <&cpu3>; 1690 1691 out-ports { 1692 port { 1693 etm3_out: endpoint { 1694 remote-endpoint = <&funnel_in5>; 1695 }; 1696 }; 1697 }; 1698 }; 1699 }; 1700}; 1701#include "qcom-apq8064-pins.dtsi"
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