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imx7s.dtsi
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linux-6.19.14/arch/arm/boot/dts/nxp/imx/imx7s.dtsi
1// SPDX-License-Identifier: GPL-2.0+ OR MIT 2// 3// Copyright 2015 Freescale Semiconductor, Inc. 4// Copyright 2016 Toradex AG 5 6#include <dt-bindings/clock/imx7d-clock.h> 7#include <dt-bindings/power/imx7-power.h> 8#include <dt-bindings/gpio/gpio.h> 9#include <dt-bindings/input/input.h> 10#include <dt-bindings/interrupt-controller/arm-gic.h> 11#include <dt-bindings/reset/imx7-reset.h> 12#include "imx7d-pinfunc.h" 13 14/ { 15 #address-cells = <1>; 16 #size-cells = <1>; 17 /* 18 * The decompressor and also some bootloaders rely on a 19 * pre-existing /chosen node to be available to insert the 20 * command line and merge other ATAGS info. 21 */ 22 chosen {}; 23 24 aliases { 25 gpio0 = &gpio1; 26 gpio1 = &gpio2; 27 gpio2 = &gpio3; 28 gpio3 = &gpio4; 29 gpio4 = &gpio5; 30 gpio5 = &gpio6; 31 gpio6 = &gpio7; 32 i2c0 = &i2c1; 33 i2c1 = &i2c2; 34 i2c2 = &i2c3; 35 i2c3 = &i2c4; 36 mmc0 = &usdhc1; 37 mmc1 = &usdhc2; 38 mmc2 = &usdhc3; 39 serial0 = &uart1; 40 serial1 = &uart2; 41 serial2 = &uart3; 42 serial3 = &uart4; 43 serial4 = &uart5; 44 serial5 = &uart6; 45 serial6 = &uart7; 46 spi0 = &ecspi1; 47 spi1 = &ecspi2; 48 spi2 = &ecspi3; 49 spi3 = &ecspi4; 50 usb0 = &usbotg1; 51 usb1 = &usbh; 52 }; 53 54 cpus { 55 #address-cells = <1>; 56 #size-cells = <0>; 57 58 idle-states { 59 entry-method = "psci"; 60 61 cpu_sleep_wait: cpu-sleep-wait { 62 compatible = "arm,idle-state"; 63 arm,psci-suspend-param = <0x0010000>; 64 local-timer-stop; 65 entry-latency-us = <100>; 66 exit-latency-us = <50>; 67 min-residency-us = <1000>; 68 }; 69 }; 70 71 cpu0: cpu@0 { 72 compatible = "arm,cortex-a7"; 73 device_type = "cpu"; 74 reg = <0>; 75 clock-frequency = <792000000>; 76 clocks = <&clks IMX7D_CLK_ARM>; 77 cpu-idle-states = <&cpu_sleep_wait>; 78 operating-points-v2 = <&cpu0_opp_table>; 79 #cooling-cells = <2>; 80 nvmem-cells = <&fuse_grade>; 81 nvmem-cell-names = "speed_grade"; 82 }; 83 }; 84 85 cpu0_opp_table: opp-table { 86 compatible = "operating-points-v2"; 87 opp-shared; 88 89 opp-792000000 { 90 opp-hz = /bits/ 64 <792000000>; 91 opp-microvolt = <1000000>; 92 clock-latency-ns = <150000>; 93 opp-supported-hw = <0xf>, <0xf>; 94 }; 95 }; 96 97 ckil: clock-cki { 98 compatible = "fixed-clock"; 99 #clock-cells = <0>; 100 clock-frequency = <32768>; 101 clock-output-names = "ckil"; 102 }; 103 104 osc: clock-osc { 105 compatible = "fixed-clock"; 106 #clock-cells = <0>; 107 clock-frequency = <24000000>; 108 clock-output-names = "osc"; 109 }; 110 111 usbphynop1: usbphynop1 { 112 compatible = "usb-nop-xceiv"; 113 clocks = <&clks IMX7D_USB_PHY1_CLK>; 114 clock-names = "main_clk"; 115 #phy-cells = <0>; 116 }; 117 118 usbphynop3: usbphynop3 { 119 compatible = "usb-nop-xceiv"; 120 clocks = <&clks IMX7D_USB_HSIC_ROOT_CLK>; 121 clock-names = "main_clk"; 122 power-domains = <&pgc_hsic_phy>; 123 #phy-cells = <0>; 124 }; 125 126 pmu { 127 compatible = "arm,cortex-a7-pmu"; 128 interrupt-parent = <&gpc>; 129 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; 130 interrupt-affinity = <&cpu0>; 131 }; 132 133 replicator { 134 /* 135 * non-configurable replicators don't show up on the 136 * AMBA bus. As such no need to add "arm,primecell" 137 */ 138 compatible = "arm,coresight-static-replicator"; 139 140 out-ports { 141 #address-cells = <1>; 142 #size-cells = <0>; 143 /* replicator output ports */ 144 port@0 { 145 reg = <0>; 146 replicator_out_port0: endpoint { 147 remote-endpoint = <&tpiu_in_port>; 148 }; 149 }; 150 151 port@1 { 152 reg = <1>; 153 replicator_out_port1: endpoint { 154 remote-endpoint = <&etr_in_port>; 155 }; 156 }; 157 }; 158 159 in-ports { 160 port { 161 replicator_in_port0: endpoint { 162 remote-endpoint = <&etf_out_port>; 163 }; 164 }; 165 }; 166 }; 167 168 timer { 169 compatible = "arm,armv7-timer"; 170 arm,cpu-registers-not-fw-configured; 171 interrupt-parent = <&intc>; 172 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, 173 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, 174 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, 175 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>; 176 }; 177 178 video_mux: csi-mux { 179 compatible = "video-mux"; 180 mux-controls = <&mux 0>; 181 #address-cells = <1>; 182 #size-cells = <0>; 183 status = "disabled"; 184 185 port@0 { 186 reg = <0>; 187 }; 188 189 port@1 { 190 reg = <1>; 191 192 csi_mux_from_mipi_vc0: endpoint { 193 remote-endpoint = <&mipi_vc0_to_csi_mux>; 194 }; 195 }; 196 197 port@2 { 198 reg = <2>; 199 200 csi_mux_to_csi: endpoint { 201 remote-endpoint = <&csi_from_csi_mux>; 202 }; 203 }; 204 }; 205 206 soc: soc { 207 #address-cells = <1>; 208 #size-cells = <1>; 209 compatible = "simple-bus"; 210 interrupt-parent = <&gpc>; 211 ranges; 212 213 ocram: sram@900000 { 214 compatible = "mmio-sram"; 215 reg = <0x00900000 0x20000>; 216 ranges = <0 0x00900000 0x20000>; 217 #address-cells = <1>; 218 #size-cells = <1>; 219 clocks = <&clks IMX7D_OCRAM_CLK>; 220 }; 221 222 funnel@30041000 { 223 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 224 reg = <0x30041000 0x1000>; 225 clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>; 226 clock-names = "apb_pclk"; 227 228 ca_funnel_in_ports: in-ports { 229 #address-cells = <1>; 230 #size-cells = <0>; 231 232 port@0 { 233 reg = <0>; 234 ca_funnel_in_port0: endpoint { 235 remote-endpoint = <&etm0_out_port>; 236 }; 237 }; 238 239 /* the other input ports are not connect to anything */ 240 }; 241 242 out-ports { 243 port { 244 ca_funnel_out_port0: endpoint { 245 remote-endpoint = <&hugo_funnel_in_port0>; 246 }; 247 }; 248 249 }; 250 }; 251 252 etm@3007c000 { 253 compatible = "arm,coresight-etm3x", "arm,primecell"; 254 reg = <0x3007c000 0x1000>; 255 cpu = <&cpu0>; 256 clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>; 257 clock-names = "apb_pclk"; 258 259 out-ports { 260 port { 261 etm0_out_port: endpoint { 262 remote-endpoint = <&ca_funnel_in_port0>; 263 }; 264 }; 265 }; 266 }; 267 268 funnel@30083000 { 269 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 270 reg = <0x30083000 0x1000>; 271 clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>; 272 clock-names = "apb_pclk"; 273 274 in-ports { 275 #address-cells = <1>; 276 #size-cells = <0>; 277 278 port@0 { 279 reg = <0>; 280 hugo_funnel_in_port0: endpoint { 281 remote-endpoint = <&ca_funnel_out_port0>; 282 }; 283 }; 284 285 port@1 { 286 reg = <1>; 287 hugo_funnel_in_port1: endpoint { 288 /* M4 input */ 289 }; 290 }; 291 /* the other input ports are not connect to anything */ 292 }; 293 294 out-ports { 295 port { 296 hugo_funnel_out_port0: endpoint { 297 remote-endpoint = <&etf_in_port>; 298 }; 299 }; 300 }; 301 }; 302 303 etf@30084000 { 304 compatible = "arm,coresight-tmc", "arm,primecell"; 305 reg = <0x30084000 0x1000>; 306 clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>; 307 clock-names = "apb_pclk"; 308 309 in-ports { 310 port { 311 etf_in_port: endpoint { 312 remote-endpoint = <&hugo_funnel_out_port0>; 313 }; 314 }; 315 }; 316 317 out-ports { 318 port { 319 etf_out_port: endpoint { 320 remote-endpoint = <&replicator_in_port0>; 321 }; 322 }; 323 }; 324 }; 325 326 etr@30086000 { 327 compatible = "arm,coresight-tmc", "arm,primecell"; 328 reg = <0x30086000 0x1000>; 329 clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>; 330 clock-names = "apb_pclk"; 331 332 in-ports { 333 port { 334 etr_in_port: endpoint { 335 remote-endpoint = <&replicator_out_port1>; 336 }; 337 }; 338 }; 339 }; 340 341 tpiu@30087000 { 342 compatible = "arm,coresight-tpiu", "arm,primecell"; 343 reg = <0x30087000 0x1000>; 344 clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>; 345 clock-names = "apb_pclk"; 346 347 in-ports { 348 port { 349 tpiu_in_port: endpoint { 350 remote-endpoint = <&replicator_out_port0>; 351 }; 352 }; 353 }; 354 }; 355 356 intc: interrupt-controller@31001000 { 357 compatible = "arm,cortex-a7-gic"; 358 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>; 359 #interrupt-cells = <3>; 360 interrupt-controller; 361 interrupt-parent = <&intc>; 362 reg = <0x31001000 0x1000>, 363 <0x31002000 0x2000>, 364 <0x31004000 0x2000>, 365 <0x31006000 0x2000>; 366 }; 367 368 aips1: bus@30000000 { 369 compatible = "fsl,aips-bus", "simple-bus"; 370 #address-cells = <1>; 371 #size-cells = <1>; 372 reg = <0x30000000 0x400000>; 373 ranges; 374 375 gpio1: gpio@30200000 { 376 compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio"; 377 reg = <0x30200000 0x10000>; 378 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>, /* GPIO1_INT15_0 */ 379 <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; /* GPIO1_INT31_16 */ 380 gpio-controller; 381 #gpio-cells = <2>; 382 interrupt-controller; 383 #interrupt-cells = <2>; 384 gpio-ranges = <&iomuxc_lpsr 0 0 8>, <&iomuxc 8 5 8>; 385 }; 386 387 gpio2: gpio@30210000 { 388 compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio"; 389 reg = <0x30210000 0x10000>; 390 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>, 391 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; 392 gpio-controller; 393 #gpio-cells = <2>; 394 interrupt-controller; 395 #interrupt-cells = <2>; 396 gpio-ranges = <&iomuxc 0 13 32>; 397 }; 398 399 gpio3: gpio@30220000 { 400 compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio"; 401 reg = <0x30220000 0x10000>; 402 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, 403 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; 404 gpio-controller; 405 #gpio-cells = <2>; 406 interrupt-controller; 407 #interrupt-cells = <2>; 408 gpio-ranges = <&iomuxc 0 45 29>; 409 }; 410 411 gpio4: gpio@30230000 { 412 compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio"; 413 reg = <0x30230000 0x10000>; 414 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, 415 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 416 gpio-controller; 417 #gpio-cells = <2>; 418 interrupt-controller; 419 #interrupt-cells = <2>; 420 gpio-ranges = <&iomuxc 0 74 24>; 421 }; 422 423 gpio5: gpio@30240000 { 424 compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio"; 425 reg = <0x30240000 0x10000>; 426 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, 427 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 428 gpio-controller; 429 #gpio-cells = <2>; 430 interrupt-controller; 431 #interrupt-cells = <2>; 432 gpio-ranges = <&iomuxc 0 98 18>; 433 }; 434 435 gpio6: gpio@30250000 { 436 compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio"; 437 reg = <0x30250000 0x10000>; 438 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>, 439 <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 440 gpio-controller; 441 #gpio-cells = <2>; 442 interrupt-controller; 443 #interrupt-cells = <2>; 444 gpio-ranges = <&iomuxc 0 116 23>; 445 }; 446 447 gpio7: gpio@30260000 { 448 compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio"; 449 reg = <0x30260000 0x10000>; 450 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>, 451 <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 452 gpio-controller; 453 #gpio-cells = <2>; 454 interrupt-controller; 455 #interrupt-cells = <2>; 456 gpio-ranges = <&iomuxc 0 139 16>; 457 }; 458 459 wdog1: watchdog@30280000 { 460 compatible = "fsl,imx7d-wdt", "fsl,imx21-wdt"; 461 reg = <0x30280000 0x10000>; 462 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; 463 clocks = <&clks IMX7D_WDOG1_ROOT_CLK>; 464 }; 465 466 wdog2: watchdog@30290000 { 467 compatible = "fsl,imx7d-wdt", "fsl,imx21-wdt"; 468 reg = <0x30290000 0x10000>; 469 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; 470 clocks = <&clks IMX7D_WDOG2_ROOT_CLK>; 471 status = "disabled"; 472 }; 473 474 wdog3: watchdog@302a0000 { 475 compatible = "fsl,imx7d-wdt", "fsl,imx21-wdt"; 476 reg = <0x302a0000 0x10000>; 477 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 478 clocks = <&clks IMX7D_WDOG3_ROOT_CLK>; 479 status = "disabled"; 480 }; 481 482 wdog4: watchdog@302b0000 { 483 compatible = "fsl,imx7d-wdt", "fsl,imx21-wdt"; 484 reg = <0x302b0000 0x10000>; 485 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; 486 clocks = <&clks IMX7D_WDOG4_ROOT_CLK>; 487 status = "disabled"; 488 }; 489 490 iomuxc_lpsr: pinctrl@302c0000 { 491 compatible = "fsl,imx7d-iomuxc-lpsr"; 492 reg = <0x302c0000 0x10000>; 493 fsl,input-sel = <&iomuxc>; 494 }; 495 496 gpt1: timer@302d0000 { 497 compatible = "fsl,imx7d-gpt", "fsl,imx6dl-gpt"; 498 reg = <0x302d0000 0x10000>; 499 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; 500 clocks = <&clks IMX7D_GPT1_ROOT_CLK>, 501 <&clks IMX7D_GPT1_ROOT_CLK>; 502 clock-names = "ipg", "per"; 503 }; 504 505 gpt2: timer@302e0000 { 506 compatible = "fsl,imx7d-gpt", "fsl,imx6dl-gpt"; 507 reg = <0x302e0000 0x10000>; 508 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; 509 clocks = <&clks IMX7D_GPT2_ROOT_CLK>, 510 <&clks IMX7D_GPT2_ROOT_CLK>; 511 clock-names = "ipg", "per"; 512 status = "disabled"; 513 }; 514 515 gpt3: timer@302f0000 { 516 compatible = "fsl,imx7d-gpt", "fsl,imx6dl-gpt"; 517 reg = <0x302f0000 0x10000>; 518 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 519 clocks = <&clks IMX7D_GPT3_ROOT_CLK>, 520 <&clks IMX7D_GPT3_ROOT_CLK>; 521 clock-names = "ipg", "per"; 522 status = "disabled"; 523 }; 524 525 gpt4: timer@30300000 { 526 compatible = "fsl,imx7d-gpt", "fsl,imx6dl-gpt"; 527 reg = <0x30300000 0x10000>; 528 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; 529 clocks = <&clks IMX7D_GPT4_ROOT_CLK>, 530 <&clks IMX7D_GPT4_ROOT_CLK>; 531 clock-names = "ipg", "per"; 532 status = "disabled"; 533 }; 534 535 kpp: keypad@30320000 { 536 compatible = "fsl,imx7d-kpp", "fsl,imx21-kpp"; 537 reg = <0x30320000 0x10000>; 538 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; 539 clocks = <&clks IMX7D_KPP_ROOT_CLK>; 540 status = "disabled"; 541 }; 542 543 iomuxc: pinctrl@30330000 { 544 compatible = "fsl,imx7d-iomuxc"; 545 reg = <0x30330000 0x10000>; 546 }; 547 548 gpr: iomuxc-gpr@30340000 { 549 compatible = "fsl,imx7d-iomuxc-gpr", 550 "fsl,imx6q-iomuxc-gpr", "syscon", 551 "simple-mfd"; 552 reg = <0x30340000 0x10000>; 553 554 mux: mux-controller { 555 compatible = "mmio-mux"; 556 #mux-control-cells = <1>; 557 mux-reg-masks = <0x14 0x00000010>; 558 }; 559 }; 560 561 ocotp: efuse@30350000 { 562 #address-cells = <1>; 563 #size-cells = <1>; 564 compatible = "fsl,imx7d-ocotp", "syscon"; 565 reg = <0x30350000 0x10000>; 566 clocks = <&clks IMX7D_OCOTP_CLK>; 567 568 tempmon_calib: calib@3c { 569 reg = <0x3c 0x4>; 570 }; 571 572 fuse_grade: fuse-grade@10 { 573 reg = <0x10 0x4>; 574 }; 575 }; 576 577 anatop: anatop@30360000 { 578 compatible = "fsl,imx7d-anatop", "fsl,imx6q-anatop", 579 "syscon", "simple-mfd"; 580 reg = <0x30360000 0x10000>; 581 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, 582 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; 583 584 reg_1p0d: regulator-vdd1p0d { 585 compatible = "fsl,anatop-regulator"; 586 regulator-name = "vdd1p0d"; 587 regulator-min-microvolt = <800000>; 588 regulator-max-microvolt = <1200000>; 589 anatop-reg-offset = <0x210>; 590 anatop-vol-bit-shift = <8>; 591 anatop-vol-bit-width = <5>; 592 anatop-min-bit-val = <8>; 593 anatop-min-voltage = <800000>; 594 anatop-max-voltage = <1200000>; 595 anatop-enable-bit = <0>; 596 }; 597 598 reg_1p2: regulator-vdd1p2 { 599 compatible = "fsl,anatop-regulator"; 600 regulator-name = "vdd1p2"; 601 regulator-min-microvolt = <1100000>; 602 regulator-max-microvolt = <1300000>; 603 anatop-reg-offset = <0x220>; 604 anatop-vol-bit-shift = <8>; 605 anatop-vol-bit-width = <5>; 606 anatop-min-bit-val = <0x14>; 607 anatop-min-voltage = <1100000>; 608 anatop-max-voltage = <1300000>; 609 anatop-enable-bit = <0>; 610 }; 611 612 tempmon: tempmon { 613 compatible = "fsl,imx7d-tempmon"; 614 interrupt-parent = <&gpc>; 615 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; 616 fsl,tempmon = <&anatop>; 617 nvmem-cells = <&tempmon_calib>, <&fuse_grade>; 618 nvmem-cell-names = "calib", "temp_grade"; 619 clocks = <&clks IMX7D_PLL_SYS_MAIN_CLK>; 620 #thermal-sensor-cells = <0>; 621 }; 622 }; 623 624 snvs: snvs@30370000 { 625 compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd"; 626 reg = <0x30370000 0x10000>; 627 628 snvs_rtc: snvs-rtc-lp { 629 compatible = "fsl,sec-v4.0-mon-rtc-lp"; 630 regmap = <&snvs>; 631 offset = <0x34>; 632 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, 633 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 634 clocks = <&clks IMX7D_SNVS_CLK>; 635 clock-names = "snvs-rtc"; 636 }; 637 638 snvs_poweroff: snvs-poweroff { 639 compatible = "syscon-poweroff"; 640 regmap = <&snvs>; 641 offset = <0x38>; 642 value = <0x60>; 643 mask = <0x60>; 644 status = "disabled"; 645 }; 646 647 snvs_pwrkey: snvs-powerkey { 648 compatible = "fsl,sec-v4.0-pwrkey"; 649 regmap = <&snvs>; 650 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 651 clocks = <&clks IMX7D_SNVS_CLK>; 652 clock-names = "snvs-pwrkey"; 653 linux,keycode = <KEY_POWER>; 654 wakeup-source; 655 status = "disabled"; 656 }; 657 }; 658 659 clks: clock-controller@30380000 { 660 compatible = "fsl,imx7d-ccm"; 661 reg = <0x30380000 0x10000>; 662 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>, 663 <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 664 #clock-cells = <1>; 665 clocks = <&ckil>, <&osc>; 666 clock-names = "ckil", "osc"; 667 }; 668 669 src: reset-controller@30390000 { 670 compatible = "fsl,imx7d-src", "syscon"; 671 reg = <0x30390000 0x10000>; 672 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; 673 #reset-cells = <1>; 674 }; 675 676 gpc: gpc@303a0000 { 677 compatible = "fsl,imx7d-gpc"; 678 reg = <0x303a0000 0x10000>; 679 interrupt-controller; 680 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; 681 #interrupt-cells = <3>; 682 interrupt-parent = <&intc>; 683 684 pgc { 685 #address-cells = <1>; 686 #size-cells = <0>; 687 688 pgc_mipi_phy: power-domain@0 { 689 #power-domain-cells = <0>; 690 reg = <0>; 691 power-supply = <®_1p0d>; 692 }; 693 694 pgc_pcie_phy: power-domain@1 { 695 #power-domain-cells = <0>; 696 reg = <1>; 697 power-supply = <®_1p0d>; 698 }; 699 700 pgc_hsic_phy: power-domain@2 { 701 #power-domain-cells = <0>; 702 reg = <2>; 703 power-supply = <®_1p2>; 704 }; 705 }; 706 }; 707 }; 708 709 aips2: bus@30400000 { 710 compatible = "fsl,aips-bus", "simple-bus"; 711 #address-cells = <1>; 712 #size-cells = <1>; 713 reg = <0x30400000 0x400000>; 714 ranges; 715 716 adc1: adc@30610000 { 717 compatible = "fsl,imx7d-adc"; 718 reg = <0x30610000 0x10000>; 719 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 720 clocks = <&clks IMX7D_ADC_ROOT_CLK>; 721 clock-names = "adc"; 722 #io-channel-cells = <1>; 723 status = "disabled"; 724 }; 725 726 adc2: adc@30620000 { 727 compatible = "fsl,imx7d-adc"; 728 reg = <0x30620000 0x10000>; 729 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; 730 clocks = <&clks IMX7D_ADC_ROOT_CLK>; 731 clock-names = "adc"; 732 #io-channel-cells = <1>; 733 status = "disabled"; 734 }; 735 736 ecspi4: spi@30630000 { 737 #address-cells = <1>; 738 #size-cells = <0>; 739 compatible = "fsl,imx7d-ecspi", "fsl,imx51-ecspi"; 740 reg = <0x30630000 0x10000>; 741 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 742 clocks = <&clks IMX7D_ECSPI4_ROOT_CLK>, 743 <&clks IMX7D_ECSPI4_ROOT_CLK>; 744 clock-names = "ipg", "per"; 745 dma-names = "rx", "tx"; 746 dmas = <&sdma 6 7 1>, <&sdma 7 7 2>; 747 status = "disabled"; 748 }; 749 750 ftm1: pwm@30640000 { 751 compatible = "fsl,vf610-ftm-pwm"; 752 reg = <0x30640000 0x10000>; 753 #pwm-cells = <3>; 754 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 755 clock-names = "ftm_sys", "ftm_ext", 756 "ftm_fix", "ftm_cnt_clk_en"; 757 clocks = <&clks IMX7D_FLEXTIMER1_ROOT_CLK>, 758 <&clks IMX7D_FLEXTIMER1_ROOT_CLK>, 759 <&clks IMX7D_FLEXTIMER1_ROOT_CLK>, 760 <&clks IMX7D_FLEXTIMER1_ROOT_CLK>; 761 status = "disabled"; 762 }; 763 764 ftm2: pwm@30650000 { 765 compatible = "fsl,vf610-ftm-pwm"; 766 reg = <0x30650000 0x10000>; 767 #pwm-cells = <3>; 768 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>; 769 clock-names = "ftm_sys", "ftm_ext", 770 "ftm_fix", "ftm_cnt_clk_en"; 771 clocks = <&clks IMX7D_FLEXTIMER2_ROOT_CLK>, 772 <&clks IMX7D_FLEXTIMER2_ROOT_CLK>, 773 <&clks IMX7D_FLEXTIMER2_ROOT_CLK>, 774 <&clks IMX7D_FLEXTIMER2_ROOT_CLK>; 775 status = "disabled"; 776 }; 777 778 pwm1: pwm@30660000 { 779 compatible = "fsl,imx7d-pwm", "fsl,imx27-pwm"; 780 reg = <0x30660000 0x10000>; 781 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 782 clocks = <&clks IMX7D_PWM1_ROOT_CLK>, 783 <&clks IMX7D_PWM1_ROOT_CLK>; 784 clock-names = "ipg", "per"; 785 #pwm-cells = <3>; 786 status = "disabled"; 787 }; 788 789 pwm2: pwm@30670000 { 790 compatible = "fsl,imx7d-pwm", "fsl,imx27-pwm"; 791 reg = <0x30670000 0x10000>; 792 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 793 clocks = <&clks IMX7D_PWM2_ROOT_CLK>, 794 <&clks IMX7D_PWM2_ROOT_CLK>; 795 clock-names = "ipg", "per"; 796 #pwm-cells = <3>; 797 status = "disabled"; 798 }; 799 800 pwm3: pwm@30680000 { 801 compatible = "fsl,imx7d-pwm", "fsl,imx27-pwm"; 802 reg = <0x30680000 0x10000>; 803 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 804 clocks = <&clks IMX7D_PWM3_ROOT_CLK>, 805 <&clks IMX7D_PWM3_ROOT_CLK>; 806 clock-names = "ipg", "per"; 807 #pwm-cells = <3>; 808 status = "disabled"; 809 }; 810 811 pwm4: pwm@30690000 { 812 compatible = "fsl,imx7d-pwm", "fsl,imx27-pwm"; 813 reg = <0x30690000 0x10000>; 814 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 815 clocks = <&clks IMX7D_PWM4_ROOT_CLK>, 816 <&clks IMX7D_PWM4_ROOT_CLK>; 817 clock-names = "ipg", "per"; 818 #pwm-cells = <3>; 819 status = "disabled"; 820 }; 821 822 csi: csi@30710000 { 823 compatible = "fsl,imx7-csi"; 824 reg = <0x30710000 0x10000>; 825 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 826 clocks = <&clks IMX7D_CSI_MCLK_ROOT_CLK>; 827 clock-names = "mclk"; 828 status = "disabled"; 829 830 port { 831 csi_from_csi_mux: endpoint { 832 remote-endpoint = <&csi_mux_to_csi>; 833 }; 834 }; 835 }; 836 837 lcdif: lcdif@30730000 { 838 compatible = "fsl,imx7d-lcdif", "fsl,imx6sx-lcdif"; 839 reg = <0x30730000 0x10000>; 840 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 841 clocks = <&clks IMX7D_LCDIF_PIXEL_ROOT_CLK>, 842 <&clks IMX7D_LCDIF_PIXEL_ROOT_CLK>; 843 clock-names = "pix", "axi"; 844 status = "disabled"; 845 }; 846 847 mipi_csi: mipi-csi@30750000 { 848 compatible = "fsl,imx7-mipi-csi2"; 849 reg = <0x30750000 0x10000>; 850 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 851 clocks = <&clks IMX7D_IPG_ROOT_CLK>, 852 <&clks IMX7D_MIPI_CSI_ROOT_CLK>, 853 <&clks IMX7D_MIPI_DPHY_ROOT_CLK>; 854 clock-names = "pclk", "wrap", "phy"; 855 power-domains = <&pgc_mipi_phy>; 856 phy-supply = <®_1p0d>; 857 resets = <&src IMX7_RESET_MIPI_PHY_MRST>; 858 status = "disabled"; 859 860 ports { 861 #address-cells = <1>; 862 #size-cells = <0>; 863 864 port@0 { 865 reg = <0>; 866 }; 867 868 port@1 { 869 reg = <1>; 870 871 mipi_vc0_to_csi_mux: endpoint { 872 remote-endpoint = <&csi_mux_from_mipi_vc0>; 873 }; 874 }; 875 }; 876 }; 877 878 mipi_dsi: dsi@30760000 { 879 compatible = "fsl,imx7d-mipi-dsim", "fsl,imx8mm-mipi-dsim"; 880 #address-cells = <1>; 881 #size-cells = <0>; 882 reg = <0x30760000 0x400>; 883 clocks = <&clks IMX7D_MIPI_DSI_ROOT_CLK>, 884 <&clks IMX7D_MIPI_DPHY_ROOT_CLK>; 885 clock-names = "bus_clk", "sclk_mipi"; 886 assigned-clocks = <&clks IMX7D_MIPI_DSI_ROOT_SRC>, 887 <&clks IMX7D_PLL_SYS_PFD5_CLK>; 888 assigned-clock-parents = <&clks IMX7D_PLL_SYS_PFD5_CLK>; 889 assigned-clock-rates = <0>, <333000000>; 890 power-domains = <&pgc_mipi_phy>; 891 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; 892 samsung,burst-clock-frequency = <891000000>; 893 samsung,esc-clock-frequency = <20000000>; 894 samsung,pll-clock-frequency = <24000000>; 895 status = "disabled"; 896 }; 897 }; 898 899 aips3: bus@30800000 { 900 compatible = "fsl,aips-bus", "simple-bus"; 901 #address-cells = <1>; 902 #size-cells = <1>; 903 reg = <0x30800000 0x400000>; 904 ranges; 905 906 spba-bus@30800000 { 907 compatible = "fsl,spba-bus", "simple-bus"; 908 #address-cells = <1>; 909 #size-cells = <1>; 910 reg = <0x30800000 0x100000>; 911 ranges; 912 913 ecspi1: spi@30820000 { 914 #address-cells = <1>; 915 #size-cells = <0>; 916 compatible = "fsl,imx7d-ecspi", "fsl,imx51-ecspi"; 917 reg = <0x30820000 0x10000>; 918 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 919 clocks = <&clks IMX7D_ECSPI1_ROOT_CLK>, 920 <&clks IMX7D_ECSPI1_ROOT_CLK>; 921 clock-names = "ipg", "per"; 922 dma-names = "rx", "tx"; 923 dmas = <&sdma 0 7 1>, <&sdma 1 7 2>; 924 status = "disabled"; 925 }; 926 927 ecspi2: spi@30830000 { 928 #address-cells = <1>; 929 #size-cells = <0>; 930 compatible = "fsl,imx7d-ecspi", "fsl,imx51-ecspi"; 931 reg = <0x30830000 0x10000>; 932 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 933 clocks = <&clks IMX7D_ECSPI2_ROOT_CLK>, 934 <&clks IMX7D_ECSPI2_ROOT_CLK>; 935 clock-names = "ipg", "per"; 936 dma-names = "rx", "tx"; 937 dmas = <&sdma 2 7 1>, <&sdma 3 7 2>; 938 status = "disabled"; 939 }; 940 941 ecspi3: spi@30840000 { 942 #address-cells = <1>; 943 #size-cells = <0>; 944 compatible = "fsl,imx7d-ecspi", "fsl,imx51-ecspi"; 945 reg = <0x30840000 0x10000>; 946 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 947 clocks = <&clks IMX7D_ECSPI3_ROOT_CLK>, 948 <&clks IMX7D_ECSPI3_ROOT_CLK>; 949 clock-names = "ipg", "per"; 950 dma-names = "rx", "tx"; 951 dmas = <&sdma 4 7 1>, <&sdma 5 7 2>; 952 status = "disabled"; 953 }; 954 955 uart1: serial@30860000 { 956 compatible = "fsl,imx7d-uart", 957 "fsl,imx6q-uart"; 958 reg = <0x30860000 0x10000>; 959 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 960 clocks = <&clks IMX7D_UART1_ROOT_CLK>, 961 <&clks IMX7D_UART1_ROOT_CLK>; 962 clock-names = "ipg", "per"; 963 status = "disabled"; 964 }; 965 966 uart2: serial@30890000 { 967 compatible = "fsl,imx7d-uart", 968 "fsl,imx6q-uart"; 969 reg = <0x30890000 0x10000>; 970 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 971 clocks = <&clks IMX7D_UART2_ROOT_CLK>, 972 <&clks IMX7D_UART2_ROOT_CLK>; 973 clock-names = "ipg", "per"; 974 status = "disabled"; 975 }; 976 977 uart3: serial@30880000 { 978 compatible = "fsl,imx7d-uart", 979 "fsl,imx6q-uart"; 980 reg = <0x30880000 0x10000>; 981 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 982 clocks = <&clks IMX7D_UART3_ROOT_CLK>, 983 <&clks IMX7D_UART3_ROOT_CLK>; 984 clock-names = "ipg", "per"; 985 status = "disabled"; 986 }; 987 988 sai1: sai@308a0000 { 989 #sound-dai-cells = <0>; 990 compatible = "fsl,imx7d-sai", "fsl,imx6sx-sai"; 991 reg = <0x308a0000 0x10000>; 992 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 993 clocks = <&clks IMX7D_SAI1_IPG_CLK>, 994 <&clks IMX7D_SAI1_ROOT_CLK>, 995 <&clks IMX7D_CLK_DUMMY>, 996 <&clks IMX7D_CLK_DUMMY>; 997 clock-names = "bus", "mclk1", "mclk2", "mclk3"; 998 dma-names = "rx", "tx"; 999 dmas = <&sdma 8 24 0>, <&sdma 9 24 0>; 1000 status = "disabled"; 1001 }; 1002 1003 sai2: sai@308b0000 { 1004 #sound-dai-cells = <0>; 1005 compatible = "fsl,imx7d-sai", "fsl,imx6sx-sai"; 1006 reg = <0x308b0000 0x10000>; 1007 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 1008 clocks = <&clks IMX7D_SAI2_IPG_CLK>, 1009 <&clks IMX7D_SAI2_ROOT_CLK>, 1010 <&clks IMX7D_CLK_DUMMY>, 1011 <&clks IMX7D_CLK_DUMMY>; 1012 clock-names = "bus", "mclk1", "mclk2", "mclk3"; 1013 dma-names = "rx", "tx"; 1014 dmas = <&sdma 10 24 0>, <&sdma 11 24 0>; 1015 status = "disabled"; 1016 }; 1017 1018 sai3: sai@308c0000 { 1019 #sound-dai-cells = <0>; 1020 compatible = "fsl,imx7d-sai", "fsl,imx6sx-sai"; 1021 reg = <0x308c0000 0x10000>; 1022 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; 1023 clocks = <&clks IMX7D_SAI3_IPG_CLK>, 1024 <&clks IMX7D_SAI3_ROOT_CLK>, 1025 <&clks IMX7D_CLK_DUMMY>, 1026 <&clks IMX7D_CLK_DUMMY>; 1027 clock-names = "bus", "mclk1", "mclk2", "mclk3"; 1028 dma-names = "rx", "tx"; 1029 dmas = <&sdma 12 24 0>, <&sdma 13 24 0>; 1030 status = "disabled"; 1031 }; 1032 }; 1033 1034 crypto: crypto@30900000 { 1035 compatible = "fsl,sec-v4.0"; 1036 #address-cells = <1>; 1037 #size-cells = <1>; 1038 reg = <0x30900000 0x40000>; 1039 ranges = <0 0x30900000 0x40000>; 1040 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; 1041 clocks = <&clks IMX7D_CAAM_CLK>, 1042 <&clks IMX7D_AHB_CHANNEL_ROOT_CLK>; 1043 clock-names = "ipg", "aclk"; 1044 1045 sec_jr0: jr@1000 { 1046 compatible = "fsl,sec-v4.0-job-ring"; 1047 reg = <0x1000 0x1000>; 1048 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; 1049 }; 1050 1051 sec_jr1: jr@2000 { 1052 compatible = "fsl,sec-v4.0-job-ring"; 1053 reg = <0x2000 0x1000>; 1054 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; 1055 }; 1056 1057 sec_jr2: jr@3000 { 1058 compatible = "fsl,sec-v4.0-job-ring"; 1059 reg = <0x3000 0x1000>; 1060 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 1061 }; 1062 }; 1063 1064 flexcan1: can@30a00000 { 1065 compatible = "fsl,imx7d-flexcan", "fsl,imx6q-flexcan"; 1066 reg = <0x30a00000 0x10000>; 1067 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; 1068 clocks = <&clks IMX7D_CLK_DUMMY>, 1069 <&clks IMX7D_CAN1_ROOT_CLK>; 1070 clock-names = "ipg", "per"; 1071 fsl,stop-mode = <&gpr 0x10 1>; 1072 status = "disabled"; 1073 }; 1074 1075 flexcan2: can@30a10000 { 1076 compatible = "fsl,imx7d-flexcan", "fsl,imx6q-flexcan"; 1077 reg = <0x30a10000 0x10000>; 1078 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>; 1079 clocks = <&clks IMX7D_CLK_DUMMY>, 1080 <&clks IMX7D_CAN2_ROOT_CLK>; 1081 clock-names = "ipg", "per"; 1082 fsl,stop-mode = <&gpr 0x10 2>; 1083 status = "disabled"; 1084 }; 1085 1086 i2c1: i2c@30a20000 { 1087 #address-cells = <1>; 1088 #size-cells = <0>; 1089 compatible = "fsl,imx7d-i2c", "fsl,imx21-i2c"; 1090 reg = <0x30a20000 0x10000>; 1091 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 1092 clocks = <&clks IMX7D_I2C1_ROOT_CLK>; 1093 status = "disabled"; 1094 }; 1095 1096 i2c2: i2c@30a30000 { 1097 #address-cells = <1>; 1098 #size-cells = <0>; 1099 compatible = "fsl,imx7d-i2c", "fsl,imx21-i2c"; 1100 reg = <0x30a30000 0x10000>; 1101 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 1102 clocks = <&clks IMX7D_I2C2_ROOT_CLK>; 1103 status = "disabled"; 1104 }; 1105 1106 i2c3: i2c@30a40000 { 1107 #address-cells = <1>; 1108 #size-cells = <0>; 1109 compatible = "fsl,imx7d-i2c", "fsl,imx21-i2c"; 1110 reg = <0x30a40000 0x10000>; 1111 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 1112 clocks = <&clks IMX7D_I2C3_ROOT_CLK>; 1113 status = "disabled"; 1114 }; 1115 1116 i2c4: i2c@30a50000 { 1117 #address-cells = <1>; 1118 #size-cells = <0>; 1119 compatible = "fsl,imx7d-i2c", "fsl,imx21-i2c"; 1120 reg = <0x30a50000 0x10000>; 1121 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 1122 clocks = <&clks IMX7D_I2C4_ROOT_CLK>; 1123 status = "disabled"; 1124 }; 1125 1126 uart4: serial@30a60000 { 1127 compatible = "fsl,imx7d-uart", 1128 "fsl,imx6q-uart"; 1129 reg = <0x30a60000 0x10000>; 1130 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 1131 clocks = <&clks IMX7D_UART4_ROOT_CLK>, 1132 <&clks IMX7D_UART4_ROOT_CLK>; 1133 clock-names = "ipg", "per"; 1134 status = "disabled"; 1135 }; 1136 1137 uart5: serial@30a70000 { 1138 compatible = "fsl,imx7d-uart", 1139 "fsl,imx6q-uart"; 1140 reg = <0x30a70000 0x10000>; 1141 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 1142 clocks = <&clks IMX7D_UART5_ROOT_CLK>, 1143 <&clks IMX7D_UART5_ROOT_CLK>; 1144 clock-names = "ipg", "per"; 1145 status = "disabled"; 1146 }; 1147 1148 uart6: serial@30a80000 { 1149 compatible = "fsl,imx7d-uart", 1150 "fsl,imx6q-uart"; 1151 reg = <0x30a80000 0x10000>; 1152 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 1153 clocks = <&clks IMX7D_UART6_ROOT_CLK>, 1154 <&clks IMX7D_UART6_ROOT_CLK>; 1155 clock-names = "ipg", "per"; 1156 status = "disabled"; 1157 }; 1158 1159 uart7: serial@30a90000 { 1160 compatible = "fsl,imx7d-uart", 1161 "fsl,imx6q-uart"; 1162 reg = <0x30a90000 0x10000>; 1163 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>; 1164 clocks = <&clks IMX7D_UART7_ROOT_CLK>, 1165 <&clks IMX7D_UART7_ROOT_CLK>; 1166 clock-names = "ipg", "per"; 1167 status = "disabled"; 1168 }; 1169 1170 mu0a: mailbox@30aa0000 { 1171 compatible = "fsl,imx7s-mu", "fsl,imx6sx-mu"; 1172 reg = <0x30aa0000 0x10000>; 1173 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>; 1174 clocks = <&clks IMX7D_MU_ROOT_CLK>; 1175 #mbox-cells = <2>; 1176 status = "disabled"; 1177 }; 1178 1179 mu0b: mailbox@30ab0000 { 1180 compatible = "fsl,imx7s-mu", "fsl,imx6sx-mu"; 1181 reg = <0x30ab0000 0x10000>; 1182 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 1183 clocks = <&clks IMX7D_MU_ROOT_CLK>; 1184 #mbox-cells = <2>; 1185 fsl,mu-side-b; 1186 status = "disabled"; 1187 }; 1188 1189 usbotg1: usb@30b10000 { 1190 compatible = "fsl,imx7d-usb", "fsl,imx27-usb"; 1191 reg = <0x30b10000 0x200>; 1192 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; 1193 clocks = <&clks IMX7D_USB_CTRL_CLK>; 1194 fsl,usbphy = <&usbphynop1>; 1195 fsl,usbmisc = <&usbmisc1 0>; 1196 phy-clkgate-delay-us = <400>; 1197 status = "disabled"; 1198 }; 1199 1200 usbh: usb@30b30000 { 1201 compatible = "fsl,imx7d-usb", "fsl,imx27-usb"; 1202 reg = <0x30b30000 0x200>; 1203 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; 1204 clocks = <&clks IMX7D_USB_CTRL_CLK>; 1205 fsl,usbphy = <&usbphynop3>; 1206 fsl,usbmisc = <&usbmisc3 0>; 1207 phy_type = "hsic"; 1208 dr_mode = "host"; 1209 phy-clkgate-delay-us = <400>; 1210 status = "disabled"; 1211 }; 1212 1213 usbmisc1: usbmisc@30b10200 { 1214 #index-cells = <1>; 1215 compatible = "fsl,imx7d-usbmisc", "fsl,imx6q-usbmisc"; 1216 reg = <0x30b10200 0x200>; 1217 }; 1218 1219 usbmisc3: usbmisc@30b30200 { 1220 #index-cells = <1>; 1221 compatible = "fsl,imx7d-usbmisc", "fsl,imx6q-usbmisc"; 1222 reg = <0x30b30200 0x200>; 1223 }; 1224 1225 usdhc1: mmc@30b40000 { 1226 compatible = "fsl,imx7d-usdhc", "fsl,imx6sl-usdhc"; 1227 reg = <0x30b40000 0x10000>; 1228 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; 1229 clocks = <&clks IMX7D_IPG_ROOT_CLK>, 1230 <&clks IMX7D_NAND_USDHC_BUS_ROOT_CLK>, 1231 <&clks IMX7D_USDHC1_ROOT_CLK>; 1232 clock-names = "ipg", "ahb", "per"; 1233 bus-width = <4>; 1234 fsl,tuning-step = <2>; 1235 fsl,tuning-start-tap = <20>; 1236 status = "disabled"; 1237 }; 1238 1239 usdhc2: mmc@30b50000 { 1240 compatible = "fsl,imx7d-usdhc", "fsl,imx6sl-usdhc"; 1241 reg = <0x30b50000 0x10000>; 1242 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 1243 clocks = <&clks IMX7D_IPG_ROOT_CLK>, 1244 <&clks IMX7D_NAND_USDHC_BUS_ROOT_CLK>, 1245 <&clks IMX7D_USDHC2_ROOT_CLK>; 1246 clock-names = "ipg", "ahb", "per"; 1247 bus-width = <4>; 1248 fsl,tuning-step = <2>; 1249 fsl,tuning-start-tap = <20>; 1250 status = "disabled"; 1251 }; 1252 1253 usdhc3: mmc@30b60000 { 1254 compatible = "fsl,imx7d-usdhc", "fsl,imx6sl-usdhc"; 1255 reg = <0x30b60000 0x10000>; 1256 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; 1257 clocks = <&clks IMX7D_IPG_ROOT_CLK>, 1258 <&clks IMX7D_NAND_USDHC_BUS_ROOT_CLK>, 1259 <&clks IMX7D_USDHC3_ROOT_CLK>; 1260 clock-names = "ipg", "ahb", "per"; 1261 bus-width = <4>; 1262 fsl,tuning-step = <2>; 1263 fsl,tuning-start-tap = <20>; 1264 status = "disabled"; 1265 }; 1266 1267 qspi: spi@30bb0000 { 1268 compatible = "fsl,imx7d-qspi"; 1269 reg = <0x30bb0000 0x10000>, <0x60000000 0x10000000>; 1270 reg-names = "QuadSPI", "QuadSPI-memory"; 1271 #address-cells = <1>; 1272 #size-cells = <0>; 1273 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; 1274 clocks = <&clks IMX7D_QSPI_ROOT_CLK>, 1275 <&clks IMX7D_QSPI_ROOT_CLK>; 1276 clock-names = "qspi_en", "qspi"; 1277 status = "disabled"; 1278 }; 1279 1280 sdma: dma-controller@30bd0000 { 1281 compatible = "fsl,imx7d-sdma", "fsl,imx35-sdma"; 1282 reg = <0x30bd0000 0x10000>; 1283 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 1284 clocks = <&clks IMX7D_IPG_ROOT_CLK>, 1285 <&clks IMX7D_SDMA_CORE_CLK>; 1286 clock-names = "ipg", "ahb"; 1287 #dma-cells = <3>; 1288 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin"; 1289 }; 1290 1291 fec1: ethernet@30be0000 { 1292 compatible = "fsl,imx7d-fec", "fsl,imx6sx-fec"; 1293 reg = <0x30be0000 0x10000>; 1294 interrupt-names = "int0", "int1", "int2", "pps"; 1295 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 1296 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 1297 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, 1298 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; 1299 clocks = <&clks IMX7D_ENET1_IPG_ROOT_CLK>, 1300 <&clks IMX7D_ENET_AXI_ROOT_CLK>, 1301 <&clks IMX7D_ENET1_TIME_ROOT_CLK>, 1302 <&clks IMX7D_PLL_ENET_MAIN_125M_CLK>, 1303 <&clks IMX7D_ENET_PHY_REF_ROOT_CLK>; 1304 clock-names = "ipg", "ahb", "ptp", 1305 "enet_clk_ref", "enet_out"; 1306 fsl,num-tx-queues = <3>; 1307 fsl,num-rx-queues = <3>; 1308 fsl,stop-mode = <&gpr 0x10 3>; 1309 status = "disabled"; 1310 }; 1311 }; 1312 1313 dma_apbh: dma-controller@33000000 { 1314 compatible = "fsl,imx7d-dma-apbh", "fsl,imx28-dma-apbh"; 1315 reg = <0x33000000 0x2000>; 1316 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 1317 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 1318 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 1319 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 1320 #dma-cells = <1>; 1321 dma-channels = <4>; 1322 clocks = <&clks IMX7D_NAND_USDHC_BUS_RAWNAND_CLK>; 1323 }; 1324 1325 gpmi: nand-controller@33002000 { 1326 compatible = "fsl,imx7d-gpmi-nand"; 1327 #address-cells = <1>; 1328 #size-cells = <0>; 1329 reg = <0x33002000 0x2000>, <0x33004000 0x4000>; 1330 reg-names = "gpmi-nand", "bch"; 1331 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 1332 interrupt-names = "bch"; 1333 clocks = <&clks IMX7D_NAND_RAWNAND_CLK>, 1334 <&clks IMX7D_NAND_USDHC_BUS_RAWNAND_CLK>; 1335 clock-names = "gpmi_io", "gpmi_bch_apb"; 1336 dmas = <&dma_apbh 0>; 1337 dma-names = "rx-tx"; 1338 status = "disabled"; 1339 assigned-clocks = <&clks IMX7D_NAND_ROOT_SRC>; 1340 assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_500M_CLK>; 1341 }; 1342 }; 1343};
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