imx7d.dtsi

  1// SPDX-License-Identifier: GPL-2.0+ OR MIT
  2//
  3// Copyright 2015 Freescale Semiconductor, Inc.
  4// Copyright 2016 Toradex AG
  5
  6#include "imx7s.dtsi"
  7#include <dt-bindings/reset/imx7-reset.h>
  8
  9/ {
 10	aliases {
 11		usb0 = &usbotg1;
 12		usb1 = &usbotg2;
 13		usb2 = &usbh;
 14	};
 15
 16	cpus {
 17		cpu0: cpu@0 {
 18			clock-frequency = <996000000>;
 19			operating-points-v2 = <&cpu0_opp_table>;
 20			#cooling-cells = <2>;
 21			nvmem-cells = <&fuse_grade>;
 22			nvmem-cell-names = "speed_grade";
 23		};
 24
 25		cpu1: cpu@1 {
 26			compatible = "arm,cortex-a7";
 27			device_type = "cpu";
 28			reg = <1>;
 29			clock-frequency = <996000000>;
 30			operating-points-v2 = <&cpu0_opp_table>;
 31			#cooling-cells = <2>;
 32			cpu-idle-states = <&cpu_sleep_wait>;
 33		};
 34	};
 35
 36	timer {
 37		compatible = "arm,armv7-timer";
 38		interrupt-parent = <&intc>;
 39		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
 40			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
 41			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
 42			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
 43	};
 44
 45	cpu0_opp_table: opp-table {
 46		compatible = "operating-points-v2";
 47		opp-shared;
 48
 49		opp-792000000 {
 50			opp-hz = /bits/ 64 <792000000>;
 51			opp-microvolt = <1000000 950000 1250000>;
 52			clock-latency-ns = <150000>;
 53			opp-supported-hw = <0xd>, <0x7>;
 54			opp-suspend;
 55		};
 56
 57		opp-996000000 {
 58			opp-hz = /bits/ 64 <996000000>;
 59			opp-microvolt = <1100000 1045000 1250000>;
 60			clock-latency-ns = <150000>;
 61			opp-supported-hw = <0xc>, <0x7>;
 62			opp-suspend;
 63		};
 64
 65		opp-1200000000 {
 66			opp-hz = /bits/ 64 <1200000000>;
 67			opp-microvolt = <1225000 1200000 1250000>;
 68			clock-latency-ns = <150000>;
 69			opp-supported-hw = <0x8>, <0x3>;
 70			opp-suspend;
 71		};
 72	};
 73
 74	usbphynop2: usbphynop2 {
 75		compatible = "usb-nop-xceiv";
 76		clocks = <&clks IMX7D_USB_PHY2_CLK>;
 77		clock-names = "main_clk";
 78		#phy-cells = <0>;
 79	};
 80
 81	soc: soc {
 82		etm@3007d000 {
 83			compatible = "arm,coresight-etm3x", "arm,primecell";
 84			reg = <0x3007d000 0x1000>;
 85
 86			/*
 87			 * System will hang if added nosmp in kernel command line
 88			 * without arm,primecell-periphid because amba bus try to
 89			 * read id and core1 power off at this time.
 90			 */
 91			arm,primecell-periphid = <0xbb956>;
 92			cpu = <&cpu1>;
 93			clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
 94			clock-names = "apb_pclk";
 95
 96			out-ports {
 97				port {
 98					etm1_out_port: endpoint {
 99						remote-endpoint = <&ca_funnel_in_port1>;
100					};
101				};
102			};
103		};
104
105		intc: interrupt-controller@31001000 {
106			compatible = "arm,cortex-a7-gic";
107			interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
108			#interrupt-cells = <3>;
109			interrupt-controller;
110			interrupt-parent = <&intc>;
111			reg = <0x31001000 0x1000>,
112			      <0x31002000 0x2000>,
113			      <0x31004000 0x2000>,
114			      <0x31006000 0x2000>;
115		};
116
117		pcie: pcie@33800000 {
118			compatible = "fsl,imx7d-pcie";
119			reg = <0x33800000 0x4000>,
120			      <0x4ff00000 0x80000>;
121			reg-names = "dbi", "config";
122			#address-cells = <3>;
123			#size-cells = <2>;
124			device_type = "pci";
125			bus-range = <0x00 0xff>;
126			ranges = <0x81000000 0 0          0x4ff80000 0 0x00010000>, /* downstream I/O */
127				 <0x82000000 0 0x40000000 0x40000000 0 0x0ff00000>; /* non-prefetchable memory */
128			num-lanes = <1>;
129			interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
130			interrupt-names = "msi";
131			#interrupt-cells = <1>;
132			interrupt-map-mask = <0 0 0 0x7>;
133			/*
134			 * Reference manual lists pci irqs incorrectly
135			 * Real hardware ordering is same as imx6: D+MSI, C, B, A
136			 */
137			interrupt-map = <0 0 0 1 &intc GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
138					<0 0 0 2 &intc GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
139					<0 0 0 3 &intc GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
140					<0 0 0 4 &intc GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
141			clocks = <&clks IMX7D_PCIE_CTRL_ROOT_CLK>,
142				 <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>,
143				 <&clks IMX7D_PCIE_PHY_ROOT_CLK>;
144			clock-names = "pcie", "pcie_bus", "pcie_phy";
145			assigned-clocks = <&clks IMX7D_PCIE_CTRL_ROOT_SRC>,
146					  <&clks IMX7D_PCIE_PHY_ROOT_SRC>;
147			assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_250M_CLK>,
148						 <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;
149
150			fsl,max-link-speed = <2>;
151			power-domains = <&pgc_pcie_phy>;
152			resets = <&src IMX7_RESET_PCIEPHY>,
153				 <&src IMX7_RESET_PCIE_CTRL_APPS_EN>,
154				 <&src IMX7_RESET_PCIE_CTRL_APPS_TURNOFF>;
155			reset-names = "pciephy", "apps", "turnoff";
156			fsl,imx7d-pcie-phy = <&pcie_phy>;
157			status = "disabled";
158		};
159	};
160};
161
162&aips2 {
163	pcie_phy: pcie-phy@306d0000 {
164		  compatible = "fsl,imx7d-pcie-phy";
165		  reg = <0x306d0000 0x10000>;
166		  status = "disabled";
167	};
168
169	pxp: pxp@30700000 {
170		compatible = "fsl,imx7d-pxp";
171		reg = <0x30700000 0x10000>;
172		interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
173			     <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
174		clocks = <&clks IMX7D_PXP_CLK>;
175		clock-names = "axi";
176	};
177};
178
179&aips3 {
180	usbotg2: usb@30b20000 {
181		compatible = "fsl,imx7d-usb", "fsl,imx27-usb";
182		reg = <0x30b20000 0x200>;
183		interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
184		clocks = <&clks IMX7D_USB_CTRL_CLK>;
185		fsl,usbphy = <&usbphynop2>;
186		fsl,usbmisc = <&usbmisc2 0>;
187		phy-clkgate-delay-us = <400>;
188		status = "disabled";
189	};
190
191	usbmisc2: usbmisc@30b20200 {
192		#index-cells = <1>;
193		compatible = "fsl,imx7d-usbmisc", "fsl,imx6q-usbmisc";
194		reg = <0x30b20200 0x200>;
195	};
196
197	fec2: ethernet@30bf0000 {
198		compatible = "fsl,imx7d-fec", "fsl,imx6sx-fec";
199		reg = <0x30bf0000 0x10000>;
200		interrupt-names = "int0", "int1", "int2", "pps";
201		interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
202			<GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
203			<GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
204			<GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
205		clocks = <&clks IMX7D_ENET2_IPG_ROOT_CLK>,
206			<&clks IMX7D_ENET_AXI_ROOT_CLK>,
207			<&clks IMX7D_ENET2_TIME_ROOT_CLK>,
208			<&clks IMX7D_PLL_ENET_MAIN_125M_CLK>,
209			<&clks IMX7D_ENET_PHY_REF_ROOT_CLK>;
210		clock-names = "ipg", "ahb", "ptp",
211			"enet_clk_ref", "enet_out";
212		fsl,num-tx-queues = <3>;
213		fsl,num-rx-queues = <3>;
214		fsl,stop-mode = <&gpr 0x10 4>;
215		status = "disabled";
216	};
217};
218
219&ca_funnel_in_ports {
220	port@1 {
221		reg = <1>;
222		ca_funnel_in_port1: endpoint {
223			remote-endpoint = <&etm1_out_port>;
224		};
225	};
226};