imx6ul-var-som.dtsi

  1// SPDX-License-Identifier: GPL-2.0+
  2/*
  3 * Support for Variscite VAR-SOM-MX6UL Module
  4 *
  5 * Copyright 2019 Variscite Ltd.
  6 * Copyright 2025 Bootlin
  7 */
  8
  9/dts-v1/;
 10
 11#include "imx6ul.dtsi"
 12#include <dt-bindings/clock/imx6ul-clock.h>
 13#include <dt-bindings/gpio/gpio.h>
 14
 15/ {
 16	model = "Variscite VAR-SOM-MX6UL module";
 17	compatible = "variscite,var-som-imx6ul", "fsl,imx6ul";
 18
 19	memory@80000000 {
 20		device_type = "memory";
 21		reg = <0x80000000 0x20000000>;
 22	};
 23
 24	reg_gpio_dvfs: reg-gpio-dvfs {
 25		compatible = "regulator-gpio";
 26		regulator-min-microvolt = <1300000>;
 27		regulator-max-microvolt = <1400000>;
 28		regulator-name = "gpio_dvfs";
 29		regulator-type = "voltage";
 30		gpios = <&gpio4 13 GPIO_ACTIVE_HIGH>;
 31		states = <1300000 0x1
 32			  1400000 0x0>;
 33	};
 34
 35	rmii_ref_clk: rmii-ref-clk {
 36		compatible = "fixed-clock";
 37		#clock-cells = <0>;
 38		clock-frequency = <25000000>;
 39		clock-output-names = "rmii-ref";
 40	};
 41};
 42
 43&clks {
 44	assigned-clocks = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>;
 45	assigned-clock-rates = <786432000>;
 46};
 47
 48&cpu0 {
 49	dc-supply = <&reg_gpio_dvfs>;
 50};
 51
 52&fec1 {
 53	pinctrl-names = "default";
 54	pinctrl-0 = <&pinctrl_enet1>, <&pinctrl_enet1_gpio>, <&pinctrl_enet1_mdio>;
 55	phy-mode = "rmii";
 56	phy-handle = <&ethphy0>;
 57	status = "okay";
 58
 59	mdio {
 60		#address-cells = <1>;
 61		#size-cells = <0>;
 62
 63		ethphy0: ethernet-phy@1 {
 64			compatible = "ethernet-phy-ieee802.3-c22";
 65			reg = <1>;
 66			clocks = <&rmii_ref_clk>;
 67			clock-names = "rmii-ref";
 68			reset-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>;
 69			reset-assert-us = <100000>;
 70			micrel,led-mode = <1>;
 71			micrel,rmii-reference-clock-select-25-mhz = <1>;
 72		};
 73	};
 74};
 75
 76&iomuxc {
 77	pinctrl-names = "default";
 78	pinctrl-0 = <&pinctrl_hog>;
 79
 80	pinctrl_enet1: enet1grp {
 81		fsl,pins = <
 82			MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN	0x1b0b0
 83			MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER	0x1b0b0
 84			MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00	0x1b0b0
 85			MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01	0x1b0b0
 86			MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN	0x1b0b0
 87			MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00	0x1b0b0
 88			MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01	0x1b0b0
 89			MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1	0x4001b031
 90		>;
 91	};
 92
 93	pinctrl_enet1_gpio: enet1-gpiogrp {
 94		fsl,pins = <
 95			MX6UL_PAD_SNVS_TAMPER0__GPIO5_IO00	0x1b0b0 /* fec1 reset */
 96		>;
 97	};
 98
 99	pinctrl_enet1_mdio: enet1-mdiogrp {
100		fsl,pins = <
101			MX6UL_PAD_GPIO1_IO06__ENET1_MDIO	0x1b0b0
102			MX6UL_PAD_GPIO1_IO07__ENET1_MDC		0x1b0b0
103		>;
104	};
105
106	pinctrl_hog: hoggrp {
107		fsl,pins = <
108			MX6UL_PAD_SNVS_TAMPER4__GPIO5_IO04	0x1b0b0	/* BT Enable */
109			MX6UL_PAD_SNVS_TAMPER6__GPIO5_IO06	0x03029	/* WLAN Enable */
110		>;
111	};
112
113	pinctrl_sai2: sai2grp {
114		fsl,pins = <
115			MX6UL_PAD_JTAG_TDI__SAI2_TX_BCLK	0x17088
116			MX6UL_PAD_JTAG_TDO__SAI2_TX_SYNC	0x17088
117			MX6UL_PAD_JTAG_TRST_B__SAI2_TX_DATA	0x11088
118			MX6UL_PAD_JTAG_TCK__SAI2_RX_DATA	0x11088
119			MX6UL_PAD_JTAG_TMS__SAI2_MCLK		0x17088
120		>;
121	};
122
123	pinctrl_tsc: tscgrp {
124		fsl,pins = <
125			MX6UL_PAD_GPIO1_IO01__GPIO1_IO01	0xb0
126			MX6UL_PAD_GPIO1_IO02__GPIO1_IO02	0xb0
127			MX6UL_PAD_GPIO1_IO03__GPIO1_IO03	0xb0
128			MX6UL_PAD_GPIO1_IO04__GPIO1_IO04	0xb0
129		>;
130	};
131
132	pinctrl_uart2: uart2grp {
133		fsl,pins = <
134			MX6UL_PAD_UART2_TX_DATA__UART2_DCE_TX	0x1b0b1
135			MX6UL_PAD_UART2_RX_DATA__UART2_DCE_RX	0x1b0b1
136			MX6UL_PAD_UART2_CTS_B__UART2_DCE_CTS	0x1b0b1
137			MX6UL_PAD_UART2_RTS_B__UART2_DCE_RTS	0x1b0b1
138		>;
139	};
140
141	pinctrl_usdhc2: usdhc2grp {
142		fsl,pins = <
143			MX6UL_PAD_NAND_RE_B__USDHC2_CLK		0x10069
144			MX6UL_PAD_NAND_WE_B__USDHC2_CMD		0x17059
145			MX6UL_PAD_NAND_DATA00__USDHC2_DATA0	0x17059
146			MX6UL_PAD_NAND_DATA01__USDHC2_DATA1	0x17059
147			MX6UL_PAD_NAND_DATA02__USDHC2_DATA2	0x17059
148			MX6UL_PAD_NAND_DATA03__USDHC2_DATA3	0x17059
149			MX6UL_PAD_NAND_DATA04__USDHC2_DATA4	0x17059
150			MX6UL_PAD_NAND_DATA05__USDHC2_DATA5	0x17059
151			MX6UL_PAD_NAND_DATA06__USDHC2_DATA6	0x17059
152			MX6UL_PAD_NAND_DATA07__USDHC2_DATA7	0x17059
153		>;
154	};
155
156	pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
157		fsl,pins = <
158			MX6UL_PAD_NAND_RE_B__USDHC2_CLK		0x100b9
159			MX6UL_PAD_NAND_WE_B__USDHC2_CMD		0x170b9
160			MX6UL_PAD_NAND_DATA00__USDHC2_DATA0	0x170b9
161			MX6UL_PAD_NAND_DATA01__USDHC2_DATA1	0x170b9
162			MX6UL_PAD_NAND_DATA02__USDHC2_DATA2	0x170b9
163			MX6UL_PAD_NAND_DATA03__USDHC2_DATA3	0x170b9
164			MX6UL_PAD_NAND_DATA04__USDHC2_DATA4	0x170b9
165			MX6UL_PAD_NAND_DATA05__USDHC2_DATA5	0x170b9
166			MX6UL_PAD_NAND_DATA06__USDHC2_DATA6	0x170b9
167			MX6UL_PAD_NAND_DATA07__USDHC2_DATA7	0x170b9
168		>;
169	};
170
171	pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
172		fsl,pins = <
173			MX6UL_PAD_NAND_RE_B__USDHC2_CLK		0x100f9
174			MX6UL_PAD_NAND_WE_B__USDHC2_CMD		0x170f9
175			MX6UL_PAD_NAND_DATA00__USDHC2_DATA0	0x170f9
176			MX6UL_PAD_NAND_DATA01__USDHC2_DATA1	0x170f9
177			MX6UL_PAD_NAND_DATA02__USDHC2_DATA2	0x170f9
178			MX6UL_PAD_NAND_DATA03__USDHC2_DATA3	0x170f9
179			MX6UL_PAD_NAND_DATA04__USDHC2_DATA4	0x170f9
180			MX6UL_PAD_NAND_DATA05__USDHC2_DATA5	0x170f9
181			MX6UL_PAD_NAND_DATA06__USDHC2_DATA6	0x170f9
182			MX6UL_PAD_NAND_DATA07__USDHC2_DATA7	0x170f9
183		>;
184	};
185};
186
187&pxp {
188	status = "okay";
189};
190
191&sai2 {
192	pinctrl-names = "default";
193	pinctrl-0 = <&pinctrl_sai2>;
194	assigned-clocks = <&clks IMX6UL_CLK_SAI2_SEL>,
195			  <&clks IMX6UL_CLK_SAI2>;
196	assigned-clock-parents = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>;
197	assigned-clock-rates = <0>, <12288000>;
198	fsl,sai-mclk-direction-output;
199	status = "okay";
200};
201
202&snvs_poweroff {
203	status = "okay";
204};
205
206&tsc {
207	pinctrl-names = "default";
208	pinctrl-0 = <&pinctrl_tsc>;
209	xnur-gpios = <&gpio1 3 GPIO_ACTIVE_LOW>;
210	measure-delay-time = <0xffff>;
211	pre-charge-time = <0xfff>;
212	status = "okay";
213};
214
215&uart2 {
216	pinctrl-names = "default";
217	pinctrl-0 = <&pinctrl_uart2>;
218	uart-has-rtscts;
219	status = "okay";
220};
221
222&usdhc2 {
223	pinctrl-names = "default", "state_100mhz", "state_200mhz";
224	pinctrl-0 = <&pinctrl_usdhc2>;
225	pinctrl-1 = <&pinctrl_usdhc2_100mhz>;
226	pinctrl-2 = <&pinctrl_usdhc2_200mhz>;
227	bus-width = <8>;
228	no-1-8-v;
229	non-removable;
230	keep-power-in-suspend;
231	wakeup-source;
232	status = "okay";
233};