imx6ul-isiot.dtsi

  1// SPDX-License-Identifier: GPL-2.0 OR X11
  2/*
  3 * Copyright (C) 2016 Amarula Solutions B.V.
  4 * Copyright (C) 2016 Engicam S.r.l.
  5 */
  6
  7#include <dt-bindings/gpio/gpio.h>
  8#include <dt-bindings/input/input.h>
  9#include "imx6ul.dtsi"
 10
 11/ {
 12	memory@80000000 {
 13		device_type = "memory";
 14		reg = <0x80000000 0x20000000>;
 15	};
 16
 17	chosen {
 18		stdout-path = &uart1;
 19	};
 20
 21	backlight {
 22		compatible = "pwm-backlight";
 23		pwms = <&pwm8 0 100000 0>;
 24		brightness-levels = < 0  1  2  3  4  5  6  7  8  9
 25				     10 11 12 13 14 15 16 17 18 19
 26				     20 21 22 23 24 25 26 27 28 29
 27				     30 31 32 33 34 35 36 37 38 39
 28				     40 41 42 43 44 45 46 47 48 49
 29				     50 51 52 53 54 55 56 57 58 59
 30				     60 61 62 63 64 65 66 67 68 69
 31				     70 71 72 73 74 75 76 77 78 79
 32				     80 81 82 83 84 85 86 87 88 89
 33				     90 91 92 93 94 95 96 97 98 99
 34				    100>;
 35		default-brightness-level = <100>;
 36	};
 37
 38	reg_1p8v: regulator-1p8v {
 39		compatible = "regulator-fixed";
 40		regulator-name = "1P8V";
 41		regulator-min-microvolt = <1800000>;
 42		regulator-max-microvolt = <1800000>;
 43		regulator-always-on;
 44		regulator-boot-on;
 45	};
 46
 47	reg_3p3v: regulator-3p3v {
 48		compatible = "regulator-fixed";
 49		regulator-name = "3P3V";
 50		regulator-min-microvolt = <3300000>;
 51		regulator-max-microvolt = <3300000>;
 52		regulator-always-on;
 53		regulator-boot-on;
 54	};
 55
 56	sound {
 57		compatible = "simple-audio-card";
 58		simple-audio-card,name = "imx6ul-isiot-sgtl5000";
 59		simple-audio-card,format = "i2s";
 60		simple-audio-card,bitclock-master = <&dailink_master>;
 61		simple-audio-card,frame-master = <&dailink_master>;
 62		simple-audio-card,widgets =
 63			"Microphone", "Mic Jack",
 64			"Line", "Line In",
 65			"Line", "Line Out",
 66			"Headphone", "Headphone Jack";
 67		simple-audio-card,routing =
 68			"MIC_IN", "Mic Jack",
 69			"Mic Jack", "Mic Bias",
 70			"Headphone Jack", "HP_OUT";
 71
 72		simple-audio-card,cpu {
 73			sound-dai = <&sai2>;
 74		};
 75
 76		dailink_master: simple-audio-card,codec {
 77			sound-dai = <&sgtl5000>;
 78			clocks = <&clks IMX6UL_CLK_SAI2>;
 79		};
 80	};
 81};
 82
 83&fec1 {
 84	pinctrl-names = "default";
 85	pinctrl-0 = <&pinctrl_enet1>;
 86	phy-mode = "rmii";
 87	phy-handle = <&ethphy0>;
 88	status = "okay";
 89
 90	mdio {
 91		#address-cells = <1>;
 92		#size-cells = <0>;
 93
 94		ethphy0: ethernet-phy@0 {
 95			compatible = "ethernet-phy-ieee802.3-c22";
 96			reg = <0>;
 97		};
 98	};
 99};
100
101&gpmi {
102	pinctrl-names = "default";
103	pinctrl-0 = <&pinctrl_gpmi_nand>;
104	nand-on-flash-bbt;
105	status = "disabled";
106};
107
108&i2c1 {
109	clock-frequency = <100000>;
110	pinctrl-names = "default";
111	pinctrl-0 = <&pinctrl_i2c1>;
112	status = "okay";
113
114	sgtl5000: codec@a {
115		compatible = "fsl,sgtl5000";
116		reg = <0x0a>;
117		#sound-dai-cells = <0>;
118		clocks = <&clks IMX6UL_CLK_OSC>;
119		clock-names = "mclk";
120		VDDA-supply = <&reg_3p3v>;
121		VDDIO-supply = <&reg_3p3v>;
122		VDDD-supply = <&reg_1p8v>;
123	};
124
125	gpio-expander@44 {
126		compatible = "st,stmpe811";
127		reg = <0x44>;
128		pinctrl-names = "default";
129		pinctrl-0 = <&pinctrl_stmpe>;
130		interrupt-parent = <&gpio1>;
131		interrupts = <18 IRQ_TYPE_EDGE_FALLING>;
132
133		gpio {
134			compatible = "st,stmpe-gpio";
135			gpio-controller;
136			#gpio-cells = <2>;
137			interrupt-controller;
138			#interrupt-cells = <2>;
139		};
140
141		stmpe: touchscreen {
142			compatible = "st,stmpe-ts";
143			st,sample-time = <4>;
144			st,mod-12b = <1>;
145			st,ref-sel = <0>;
146			st,adc-freq = <1>;
147			st,ave-ctrl = <1>;
148			st,touch-det-delay = <2>;
149			st,settling = <2>;
150			st,fraction-z = <7>;
151			st,i-drive = <1>;
152		};
153	};
154};
155
156&i2c2 {
157	clock-frequency = <100000>;
158	pinctrl-names = "default";
159	pinctrl-0 = <&pinctrl_i2c2>;
160	status = "okay";
161};
162
163&lcdif {
164	pinctrl-names = "default";
165	pinctrl-0 = <&pinctrl_lcdif_dat
166		     &pinctrl_lcdif_ctrl>;
167	display = <&display0>;
168	status = "okay";
169
170	display0: display0 {
171		bits-per-pixel = <16>;
172		bus-width = <18>;
173
174		display-timings {
175			native-mode = <&timing0>;
176			timing0: timing0 {
177				clock-frequency = <28000000>;
178				hactive = <800>;
179				vactive = <480>;
180				hfront-porch = <30>;
181				hback-porch = <30>;
182				hsync-len = <64>;
183				vback-porch = <5>;
184				vfront-porch = <5>;
185				vsync-len = <20>;
186				hsync-active = <0>;
187				vsync-active = <0>;
188				de-active = <1>;
189				pixelclk-active = <0>;
190			};
191		};
192	};
193};
194
195&pwm8 {
196	pinctrl-names = "default";
197	pinctrl-0 = <&pinctrl_pwm8>;
198	status = "okay";
199};
200
201&sai2 {
202	pinctrl-names = "default";
203	pinctrl-0 = <&pinctrl_sai2>;
204	status = "okay";
205};
206
207&uart1 {
208	pinctrl-names = "default";
209	pinctrl-0 = <&pinctrl_uart1>;
210	status = "okay";
211};
212
213&usdhc1 {
214	pinctrl-names = "default", "state_100mhz", "state_200mhz";
215	pinctrl-0 = <&pinctrl_usdhc1>;
216	pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
217	pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
218	cd-gpios = <&gpio1 19 GPIO_ACTIVE_LOW>;
219	bus-width = <4>;
220	no-1-8-v;
221	status = "okay";
222};
223
224&usdhc2 {
225	pinctrl-names = "default";
226	pinctrl-0 = <&pinctrl_usdhc2>;
227	cd-gpios = <&gpio4 5 GPIO_ACTIVE_LOW>;
228	bus-width = <8>;
229	no-1-8-v;
230	status = "disabled";
231};
232
233&iomuxc {
234	pinctrl_enet1: enet1grp {
235		fsl,pins = <
236			MX6UL_PAD_ENET2_RX_DATA0__ENET1_MDIO	0x1b0b0
237			MX6UL_PAD_ENET2_RX_DATA1__ENET1_MDC	0x1b0b0
238			MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN	0x1b0b0
239			MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00	0x1b0b0
240			MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01	0x1b0b0
241			MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN	0x1b0b0
242			MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00	0x1b0b0
243			MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01	0x1b0b0
244			MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1	0x4001b031
245			MX6UL_PAD_ENET2_RX_EN__GPIO2_IO10	0x1b0b0
246		>;
247	};
248
249	pinctrl_gpmi_nand: gpminandgrp {
250		fsl,pins = <
251			MX6UL_PAD_NAND_CLE__RAWNAND_CLE         0xb0b1
252			MX6UL_PAD_NAND_ALE__RAWNAND_ALE         0xb0b1
253			MX6UL_PAD_NAND_WP_B__RAWNAND_WP_B       0xb0b1
254			MX6UL_PAD_NAND_READY_B__RAWNAND_READY_B 0xb000
255			MX6UL_PAD_NAND_CE0_B__RAWNAND_CE0_B     0xb0b1
256			MX6UL_PAD_NAND_RE_B__RAWNAND_RE_B       0xb0b1
257			MX6UL_PAD_NAND_WE_B__RAWNAND_WE_B       0xb0b1
258			MX6UL_PAD_NAND_DATA00__RAWNAND_DATA00   0xb0b1
259			MX6UL_PAD_NAND_DATA01__RAWNAND_DATA01   0xb0b1
260			MX6UL_PAD_NAND_DATA02__RAWNAND_DATA02   0xb0b1
261			MX6UL_PAD_NAND_DATA03__RAWNAND_DATA03   0xb0b1
262			MX6UL_PAD_NAND_DATA04__RAWNAND_DATA04   0xb0b1
263			MX6UL_PAD_NAND_DATA05__RAWNAND_DATA05   0xb0b1
264			MX6UL_PAD_NAND_DATA06__RAWNAND_DATA06   0xb0b1
265			MX6UL_PAD_NAND_DATA07__RAWNAND_DATA07   0xb0b1
266		>;
267	};
268
269	pinctrl_i2c1: i2c1grp {
270		fsl,pins = <
271			MX6UL_PAD_UART4_TX_DATA__I2C1_SCL 0x4001b8b0
272			MX6UL_PAD_UART4_RX_DATA__I2C1_SDA 0x4001b8b0
273		>;
274	};
275
276	pinctrl_i2c2: i2c2grp {
277		fsl,pins = <
278			MX6UL_PAD_GPIO1_IO00__I2C2_SCL 0x4001b8b0
279			MX6UL_PAD_GPIO1_IO01__I2C2_SDA 0x4001b8b0
280		>;
281	};
282
283	pinctrl_lcdif_ctrl: lcdifctrlgrp {
284		fsl,pins = <
285			MX6UL_PAD_LCD_CLK__LCDIF_CLK	    0x79
286			MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE  0x79
287			MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC    0x79
288			MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC    0x79
289		>;
290	};
291
292	pinctrl_lcdif_dat: lcdifdatgrp {
293		fsl,pins = <
294			MX6UL_PAD_LCD_DATA00__LCDIF_DATA00  0x79
295			MX6UL_PAD_LCD_DATA01__LCDIF_DATA01  0x79
296			MX6UL_PAD_LCD_DATA02__LCDIF_DATA02  0x79
297			MX6UL_PAD_LCD_DATA03__LCDIF_DATA03  0x79
298			MX6UL_PAD_LCD_DATA04__LCDIF_DATA04  0x79
299			MX6UL_PAD_LCD_DATA05__LCDIF_DATA05  0x79
300			MX6UL_PAD_LCD_DATA06__LCDIF_DATA06  0x79
301			MX6UL_PAD_LCD_DATA07__LCDIF_DATA07  0x79
302			MX6UL_PAD_LCD_DATA08__LCDIF_DATA08  0x79
303			MX6UL_PAD_LCD_DATA09__LCDIF_DATA09  0x79
304			MX6UL_PAD_LCD_DATA10__LCDIF_DATA10  0x79
305			MX6UL_PAD_LCD_DATA11__LCDIF_DATA11  0x79
306			MX6UL_PAD_LCD_DATA12__LCDIF_DATA12  0x79
307			MX6UL_PAD_LCD_DATA13__LCDIF_DATA13  0x79
308			MX6UL_PAD_LCD_DATA14__LCDIF_DATA14  0x79
309			MX6UL_PAD_LCD_DATA15__LCDIF_DATA15  0x79
310			MX6UL_PAD_LCD_DATA16__LCDIF_DATA16  0x79
311			MX6UL_PAD_LCD_DATA17__LCDIF_DATA17  0x79
312		>;
313	};
314
315	pinctrl_pwm8: pwm8grp {
316		fsl,pins = <
317			MX6UL_PAD_ENET1_RX_ER__PWM8_OUT   0x110b0
318		>;
319	};
320
321	pinctrl_sai2: sai2grp {
322		fsl,pins = <
323			MX6UL_PAD_JTAG_TCK__SAI2_RX_DATA	0x130b0
324			MX6UL_PAD_JTAG_TMS__CCM_CLKO1		0x4001b031
325			MX6UL_PAD_JTAG_TDI__SAI2_TX_BCLK	0x17088
326			MX6UL_PAD_JTAG_TDO__SAI2_TX_SYNC	0x17088
327			MX6UL_PAD_JTAG_TRST_B__SAI2_TX_DATA	0x120b0
328		>;
329	};
330
331	pinctrl_stmpe: stmpegrp {
332		fsl,pins = <
333			MX6UL_PAD_UART1_CTS_B__GPIO1_IO18 0x1b0b0
334		>;
335	};
336
337	pinctrl_uart1: uart1grp {
338		fsl,pins = <
339			MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1
340			MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1
341		>;
342	};
343
344	pinctrl_usdhc1: usdhc1grp {
345		fsl,pins = <
346			MX6UL_PAD_SD1_CMD__USDHC1_CMD     0x17059
347			MX6UL_PAD_SD1_CLK__USDHC1_CLK     0x10059
348			MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059
349			MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059
350			MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059
351			MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059
352		>;
353	};
354
355	pinctrl_usdhc1_100mhz: usdhc1-100mhz-grp {
356		fsl,pins = <
357			MX6UL_PAD_SD1_CMD__USDHC1_CMD     0x170b9
358			MX6UL_PAD_SD1_CLK__USDHC1_CLK     0x100b9
359			MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170b9
360			MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170b9
361			MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170b9
362			MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170b9
363		>;
364	};
365
366	pinctrl_usdhc1_200mhz: usdhc1-200mhz-grp {
367		fsl,pins = <
368			MX6UL_PAD_SD1_CMD__USDHC1_CMD     0x170f9
369			MX6UL_PAD_SD1_CLK__USDHC1_CLK     0x100f9
370			MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170f9
371			MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170f9
372			MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170f9
373			MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170f9
374		>;
375	};
376
377	pinctrl_usdhc2: usdhc2grp {
378		fsl,pins = <
379			MX6UL_PAD_NAND_RE_B__USDHC2_CLK      0x17070
380			MX6UL_PAD_NAND_WE_B__USDHC2_CMD      0x10070
381			MX6UL_PAD_NAND_DATA00__USDHC2_DATA0  0x17070
382			MX6UL_PAD_NAND_DATA01__USDHC2_DATA1  0x17070
383			MX6UL_PAD_NAND_DATA02__USDHC2_DATA2  0x17070
384			MX6UL_PAD_NAND_DATA03__USDHC2_DATA3  0x17070
385			MX6UL_PAD_NAND_DATA04__USDHC2_DATA4  0x17070
386			MX6UL_PAD_NAND_DATA05__USDHC2_DATA5  0x17070
387			MX6UL_PAD_NAND_DATA06__USDHC2_DATA6  0x17070
388			MX6UL_PAD_NAND_DATA07__USDHC2_DATA7  0x17070
389			MX6UL_PAD_NAND_ALE__USDHC2_RESET_B   0x17070
390		>;
391	};
392};