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imx6qdl-sabresd.dtsi
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linux-6.19.14/arch/arm/boot/dts/nxp/imx/imx6qdl-sabresd.dtsi
1// SPDX-License-Identifier: GPL-2.0+ 2// 3// Copyright 2012 Freescale Semiconductor, Inc. 4// Copyright 2011 Linaro Ltd. 5 6#include <dt-bindings/clock/imx6qdl-clock.h> 7#include <dt-bindings/gpio/gpio.h> 8#include <dt-bindings/input/input.h> 9#include <dt-bindings/media/video-interfaces.h> 10 11/ { 12 chosen { 13 stdout-path = &uart1; 14 }; 15 16 memory@10000000 { 17 device_type = "memory"; 18 reg = <0x10000000 0x40000000>; 19 }; 20 21 reg_3v3: regulator-3v3 { 22 compatible = "regulator-fixed"; 23 regulator-name = "reg-3v3"; 24 regulator-min-microvolt = <3300000>; 25 regulator-max-microvolt = <3300000>; 26 }; 27 28 reg_usb_otg_vbus: regulator-usb-otg-vbus { 29 compatible = "regulator-fixed"; 30 regulator-name = "usb_otg_vbus"; 31 regulator-min-microvolt = <5000000>; 32 regulator-max-microvolt = <5000000>; 33 gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>; 34 enable-active-high; 35 vin-supply = <&swbst_reg>; 36 }; 37 38 reg_usb_h1_vbus: regulator-usb-h1-vbus { 39 compatible = "regulator-fixed"; 40 regulator-name = "usb_h1_vbus"; 41 regulator-min-microvolt = <5000000>; 42 regulator-max-microvolt = <5000000>; 43 gpio = <&gpio1 29 GPIO_ACTIVE_HIGH>; 44 enable-active-high; 45 vin-supply = <&swbst_reg>; 46 }; 47 48 reg_audio: regulator-audio { 49 compatible = "regulator-fixed"; 50 regulator-name = "wm8962-supply"; 51 gpio = <&gpio4 10 GPIO_ACTIVE_HIGH>; 52 enable-active-high; 53 }; 54 55 reg_pcie: regulator-pcie { 56 compatible = "regulator-fixed"; 57 pinctrl-names = "default"; 58 pinctrl-0 = <&pinctrl_pcie_reg>; 59 regulator-name = "MPCIE_3V3"; 60 regulator-min-microvolt = <3300000>; 61 regulator-max-microvolt = <3300000>; 62 gpio = <&gpio3 19 GPIO_ACTIVE_HIGH>; 63 enable-active-high; 64 }; 65 66 reg_sensors: regulator-sensors { 67 compatible = "regulator-fixed"; 68 pinctrl-names = "default"; 69 pinctrl-0 = <&pinctrl_sensors_reg>; 70 regulator-name = "sensors-supply"; 71 regulator-min-microvolt = <3300000>; 72 regulator-max-microvolt = <3300000>; 73 gpio = <&gpio2 31 GPIO_ACTIVE_HIGH>; 74 enable-active-high; 75 }; 76 77 gpio-keys { 78 compatible = "gpio-keys"; 79 pinctrl-names = "default"; 80 pinctrl-0 = <&pinctrl_gpio_keys>; 81 82 key-power { 83 label = "Power Button"; 84 gpios = <&gpio3 29 GPIO_ACTIVE_LOW>; 85 wakeup-source; 86 linux,code = <KEY_POWER>; 87 }; 88 89 key-volume-up { 90 label = "Volume Up"; 91 gpios = <&gpio1 4 GPIO_ACTIVE_LOW>; 92 wakeup-source; 93 linux,code = <KEY_VOLUMEUP>; 94 }; 95 96 key-volume-down { 97 label = "Volume Down"; 98 gpios = <&gpio1 5 GPIO_ACTIVE_LOW>; 99 wakeup-source; 100 linux,code = <KEY_VOLUMEDOWN>; 101 }; 102 }; 103 104 sound { 105 compatible = "fsl,imx6q-sabresd-wm8962", 106 "fsl,imx-audio-wm8962"; 107 model = "wm8962-audio"; 108 pinctrl-names = "default"; 109 pinctrl-0 = <&pinctrl_hp>; 110 ssi-controller = <&ssi2>; 111 audio-codec = <&codec>; 112 audio-asrc = <&asrc>; 113 audio-routing = 114 "Headphone Jack", "HPOUTL", 115 "Headphone Jack", "HPOUTR", 116 "Ext Spk", "SPKOUTL", 117 "Ext Spk", "SPKOUTR", 118 "AMIC", "MICBIAS", 119 "IN3R", "AMIC", 120 "DMIC", "MICBIAS", 121 "DMICDAT", "DMIC"; 122 mux-int-port = <2>; 123 mux-ext-port = <3>; 124 hp-det-gpios = <&gpio7 8 GPIO_ACTIVE_LOW>; 125 mic-det-gpios = <&gpio1 9 GPIO_ACTIVE_LOW>; 126 }; 127 128 backlight_lvds: backlight-lvds { 129 compatible = "pwm-backlight"; 130 pwms = <&pwm1 0 5000000 0>; 131 brightness-levels = <0 4 8 16 32 64 128 255>; 132 default-brightness-level = <7>; 133 status = "okay"; 134 }; 135 136 leds { 137 compatible = "gpio-leds"; 138 pinctrl-names = "default"; 139 pinctrl-0 = <&pinctrl_gpio_leds>; 140 141 led-red { 142 gpios = <&gpio1 2 0>; 143 default-state = "on"; 144 }; 145 }; 146 147 panel { 148 compatible = "hannstar,hsd100pxn1"; 149 backlight = <&backlight_lvds>; 150 power-supply = <®_3v3>; 151 152 port { 153 panel_in: endpoint { 154 remote-endpoint = <&lvds0_out>; 155 }; 156 }; 157 }; 158}; 159 160&ipu1_csi0_from_ipu1_csi0_mux { 161 bus-width = <8>; 162 data-shift = <12>; /* Lines 19:12 used */ 163 hsync-active = <1>; 164 vsync-active = <1>; 165}; 166 167&ipu1_csi0_mux_from_parallel_sensor { 168 remote-endpoint = <&ov5642_to_ipu1_csi0_mux>; 169}; 170 171&ipu1_csi0 { 172 pinctrl-names = "default"; 173 pinctrl-0 = <&pinctrl_ipu1_csi0>; 174}; 175 176&mipi_csi { 177 status = "okay"; 178 179 port@0 { 180 reg = <0>; 181 182 mipi_csi2_in: endpoint { 183 remote-endpoint = <&ov5640_to_mipi_csi2>; 184 clock-lanes = <0>; 185 data-lanes = <1 2>; 186 }; 187 }; 188}; 189 190&audmux { 191 pinctrl-names = "default"; 192 pinctrl-0 = <&pinctrl_audmux>; 193 status = "okay"; 194}; 195 196&clks { 197 assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, 198 <&clks IMX6QDL_CLK_LDB_DI1_SEL>; 199 assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>, 200 <&clks IMX6QDL_CLK_PLL3_USB_OTG>; 201}; 202 203&ecspi1 { 204 cs-gpios = <&gpio4 9 GPIO_ACTIVE_LOW>; 205 pinctrl-names = "default"; 206 pinctrl-0 = <&pinctrl_ecspi1>; 207 status = "okay"; 208 209 flash: flash@0 { 210 #address-cells = <1>; 211 #size-cells = <1>; 212 compatible = "st,m25p32", "jedec,spi-nor"; 213 spi-max-frequency = <20000000>; 214 reg = <0>; 215 }; 216}; 217 218&fec { 219 pinctrl-names = "default"; 220 pinctrl-0 = <&pinctrl_enet>; 221 phy-mode = "rgmii-id"; 222 phy-handle = <&phy>; 223 fsl,magic-packet; 224 status = "okay"; 225 226 mdio { 227 #address-cells = <1>; 228 #size-cells = <0>; 229 230 phy: ethernet-phy@1 { 231 reg = <1>; 232 qca,clk-out-frequency = <125000000>; 233 reset-gpios = <&gpio1 25 GPIO_ACTIVE_LOW>; 234 reset-assert-us = <10000>; 235 }; 236 }; 237}; 238 239&hdmi { 240 pinctrl-names = "default"; 241 pinctrl-0 = <&pinctrl_hdmi_cec>; 242 ddc-i2c-bus = <&i2c2>; 243 status = "okay"; 244}; 245 246&i2c1 { 247 clock-frequency = <100000>; 248 pinctrl-names = "default"; 249 pinctrl-0 = <&pinctrl_i2c1>; 250 status = "okay"; 251 252 codec: wm8962@1a { 253 compatible = "wlf,wm8962"; 254 reg = <0x1a>; 255 clocks = <&clks IMX6QDL_CLK_CKO>; 256 DCVDD-supply = <®_audio>; 257 DBVDD-supply = <®_audio>; 258 AVDD-supply = <®_audio>; 259 CPVDD-supply = <®_audio>; 260 MICVDD-supply = <®_audio>; 261 PLLVDD-supply = <®_audio>; 262 SPKVDD1-supply = <®_audio>; 263 SPKVDD2-supply = <®_audio>; 264 gpio-cfg = < 265 0x0000 /* 0:Default */ 266 0x0000 /* 1:Default */ 267 0x0013 /* 2:FN_DMICCLK */ 268 0x0000 /* 3:Default */ 269 0x8014 /* 4:FN_DMICCDAT */ 270 0x0000 /* 5:Default */ 271 >; 272 }; 273 274 accelerometer@1c { 275 compatible = "fsl,mma8451"; 276 reg = <0x1c>; 277 pinctrl-names = "default"; 278 pinctrl-0 = <&pinctrl_i2c1_mma8451_int>; 279 interrupt-parent = <&gpio1>; 280 interrupts = <18 IRQ_TYPE_LEVEL_LOW>; 281 vdd-supply = <®_sensors>; 282 vddio-supply = <®_sensors>; 283 }; 284 285 ov5642: camera@3c { 286 compatible = "ovti,ov5642"; 287 pinctrl-names = "default"; 288 pinctrl-0 = <&pinctrl_ov5642>; 289 clocks = <&clks IMX6QDL_CLK_CKO>; 290 reg = <0x3c>; 291 DOVDD-supply = <&vgen4_reg>; /* 1.8v */ 292 AVDD-supply = <&vgen3_reg>; /* 2.8v, rev C board is VGEN3 293 rev B board is VGEN5 */ 294 DVDD-supply = <&vgen2_reg>; /* 1.5v*/ 295 powerdown-gpios = <&gpio1 16 GPIO_ACTIVE_HIGH>; 296 reset-gpios = <&gpio1 17 GPIO_ACTIVE_LOW>; 297 status = "disabled"; 298 299 port { 300 ov5642_to_ipu1_csi0_mux: endpoint { 301 remote-endpoint = <&ipu1_csi0_mux_from_parallel_sensor>; 302 bus-type = <MEDIA_BUS_TYPE_PARALLEL>; 303 bus-width = <8>; 304 hsync-active = <1>; 305 vsync-active = <1>; 306 }; 307 }; 308 }; 309}; 310 311&i2c2 { 312 clock-frequency = <100000>; 313 pinctrl-names = "default"; 314 pinctrl-0 = <&pinctrl_i2c2>; 315 status = "okay"; 316 317 touchscreen@4 { 318 compatible = "eeti,egalax_ts"; 319 reg = <0x04>; 320 pinctrl-names = "default"; 321 pinctrl-0 = <&pinctrl_i2c2_egalax_int>; 322 interrupt-parent = <&gpio6>; 323 interrupts = <8 IRQ_TYPE_LEVEL_LOW>; 324 wakeup-gpios = <&gpio6 8 GPIO_ACTIVE_LOW>; 325 }; 326 327 ov5640: camera@3c { 328 compatible = "ovti,ov5640"; 329 pinctrl-names = "default"; 330 pinctrl-0 = <&pinctrl_ov5640>; 331 reg = <0x3c>; 332 clocks = <&clks IMX6QDL_CLK_CKO>; 333 clock-names = "xclk"; 334 DOVDD-supply = <&vgen4_reg>; /* 1.8v */ 335 AVDD-supply = <&vgen3_reg>; /* 2.8v, rev C board is VGEN3 336 rev B board is VGEN5 */ 337 DVDD-supply = <&vgen2_reg>; /* 1.5v*/ 338 powerdown-gpios = <&gpio1 19 GPIO_ACTIVE_HIGH>; 339 reset-gpios = <&gpio1 20 GPIO_ACTIVE_LOW>; 340 341 port { 342 ov5640_to_mipi_csi2: endpoint { 343 remote-endpoint = <&mipi_csi2_in>; 344 clock-lanes = <0>; 345 data-lanes = <1 2>; 346 }; 347 }; 348 }; 349 350 pmic: pmic@8 { 351 compatible = "fsl,pfuze100"; 352 reg = <0x08>; 353 354 regulators { 355 sw1a_reg: sw1ab { 356 regulator-min-microvolt = <300000>; 357 regulator-max-microvolt = <1875000>; 358 regulator-boot-on; 359 regulator-always-on; 360 regulator-ramp-delay = <6250>; 361 }; 362 363 sw1c_reg: sw1c { 364 regulator-min-microvolt = <300000>; 365 regulator-max-microvolt = <1875000>; 366 regulator-boot-on; 367 regulator-always-on; 368 regulator-ramp-delay = <6250>; 369 }; 370 371 sw2_reg: sw2 { 372 regulator-min-microvolt = <800000>; 373 regulator-max-microvolt = <3300000>; 374 regulator-boot-on; 375 regulator-always-on; 376 regulator-ramp-delay = <6250>; 377 }; 378 379 sw3a_reg: sw3a { 380 regulator-min-microvolt = <400000>; 381 regulator-max-microvolt = <1975000>; 382 regulator-boot-on; 383 regulator-always-on; 384 }; 385 386 sw3b_reg: sw3b { 387 regulator-min-microvolt = <400000>; 388 regulator-max-microvolt = <1975000>; 389 regulator-boot-on; 390 regulator-always-on; 391 }; 392 393 sw4_reg: sw4 { 394 regulator-min-microvolt = <800000>; 395 regulator-max-microvolt = <3300000>; 396 regulator-always-on; 397 }; 398 399 swbst_reg: swbst { 400 regulator-min-microvolt = <5000000>; 401 regulator-max-microvolt = <5150000>; 402 }; 403 404 snvs_reg: vsnvs { 405 regulator-min-microvolt = <1000000>; 406 regulator-max-microvolt = <3000000>; 407 regulator-boot-on; 408 regulator-always-on; 409 }; 410 411 vref_reg: vrefddr { 412 regulator-boot-on; 413 regulator-always-on; 414 }; 415 416 vgen1_reg: vgen1 { 417 regulator-min-microvolt = <800000>; 418 regulator-max-microvolt = <1550000>; 419 }; 420 421 vgen2_reg: vgen2 { 422 regulator-min-microvolt = <800000>; 423 regulator-max-microvolt = <1550000>; 424 }; 425 426 vgen3_reg: vgen3 { 427 regulator-min-microvolt = <1800000>; 428 regulator-max-microvolt = <3300000>; 429 }; 430 431 vgen4_reg: vgen4 { 432 regulator-min-microvolt = <1800000>; 433 regulator-max-microvolt = <3300000>; 434 regulator-always-on; 435 }; 436 437 vgen5_reg: vgen5 { 438 regulator-min-microvolt = <1800000>; 439 regulator-max-microvolt = <3300000>; 440 regulator-always-on; 441 }; 442 443 vgen6_reg: vgen6 { 444 regulator-min-microvolt = <1800000>; 445 regulator-max-microvolt = <3300000>; 446 regulator-always-on; 447 }; 448 }; 449 }; 450}; 451 452&i2c3 { 453 clock-frequency = <100000>; 454 pinctrl-names = "default"; 455 pinctrl-0 = <&pinctrl_i2c3>; 456 status = "okay"; 457 458 egalax_ts@4 { 459 compatible = "eeti,egalax_ts"; 460 reg = <0x04>; 461 interrupt-parent = <&gpio6>; 462 interrupts = <7 IRQ_TYPE_LEVEL_LOW>; 463 wakeup-gpios = <&gpio6 7 GPIO_ACTIVE_LOW>; 464 }; 465 466 magnetometer@e { 467 compatible = "fsl,mag3110"; 468 reg = <0x0e>; 469 pinctrl-names = "default"; 470 pinctrl-0 = <&pinctrl_i2c3_mag3110_int>; 471 interrupt-parent = <&gpio3>; 472 interrupts = <16 IRQ_TYPE_EDGE_RISING>; 473 vdd-supply = <®_sensors>; 474 vddio-supply = <®_sensors>; 475 }; 476 477 light-sensor@44 { 478 compatible = "isil,isl29023"; 479 reg = <0x44>; 480 pinctrl-names = "default"; 481 pinctrl-0 = <&pinctrl_i2c3_isl29023_int>; 482 interrupt-parent = <&gpio3>; 483 interrupts = <9 IRQ_TYPE_EDGE_FALLING>; 484 vcc-supply = <®_sensors>; 485 }; 486}; 487 488&iomuxc { 489 pinctrl-names = "default"; 490 pinctrl-0 = <&pinctrl_hog>; 491 492 pinctrl_hog: hoggrp { 493 fsl,pins = < 494 MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x1b0b0 495 MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x1b0b0 496 MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x1b0b0 497 MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x1b0b0 498 MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0 499 MX6QDL_PAD_NANDF_CLE__GPIO6_IO07 0x1b0b0 500 MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x1b0b0 501 MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0 502 MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x1b0b0 503 >; 504 }; 505 506 pinctrl_audmux: audmuxgrp { 507 fsl,pins = < 508 MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x130b0 509 MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x130b0 510 MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x110b0 511 MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x130b0 512 >; 513 }; 514 515 pinctrl_ecspi1: ecspi1grp { 516 fsl,pins = < 517 MX6QDL_PAD_KEY_COL1__ECSPI1_MISO 0x100b1 518 MX6QDL_PAD_KEY_ROW0__ECSPI1_MOSI 0x100b1 519 MX6QDL_PAD_KEY_COL0__ECSPI1_SCLK 0x100b1 520 MX6QDL_PAD_KEY_ROW1__GPIO4_IO09 0x1b0b0 521 >; 522 }; 523 524 pinctrl_enet: enetgrp { 525 fsl,pins = < 526 MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 527 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 528 MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030 529 MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030 530 MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030 531 MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030 532 MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030 533 MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030 534 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 535 MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 536 MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 537 MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 538 MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 539 MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 540 MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 541 MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 542 >; 543 }; 544 545 pinctrl_gpio_keys: gpio_keysgrp { 546 fsl,pins = < 547 MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x1b0b0 548 MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1b0b0 549 MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x1b0b0 550 >; 551 }; 552 553 pinctrl_hdmi_cec: hdmicecgrp { 554 fsl,pins = < 555 MX6QDL_PAD_KEY_ROW2__HDMI_TX_CEC_LINE 0x1f8b0 556 >; 557 }; 558 559 pinctrl_hp: hpgrp { 560 fsl,pins = < 561 MX6QDL_PAD_SD3_RST__GPIO7_IO08 0x1b0b0 562 MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x1b0b0 563 >; 564 }; 565 566 pinctrl_i2c1: i2c1grp { 567 fsl,pins = < 568 MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1 569 MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1 570 >; 571 }; 572 573 pinctrl_i2c1_mma8451_int: i2c1mma8451intgrp { 574 fsl,pins = < 575 MX6QDL_PAD_SD1_CMD__GPIO1_IO18 0xb0b1 576 >; 577 }; 578 579 pinctrl_i2c2: i2c2grp { 580 fsl,pins = < 581 MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 582 MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 583 >; 584 }; 585 586 pinctrl_i2c2_egalax_int: i2c2egalaxintgrp { 587 fsl,pins = < 588 MX6QDL_PAD_NANDF_ALE__GPIO6_IO08 0x1b0b0 589 >; 590 }; 591 592 pinctrl_i2c3: i2c3grp { 593 fsl,pins = < 594 MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1 595 MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 596 >; 597 }; 598 599 pinctrl_i2c3_isl29023_int: i2c3isl29023intgrp { 600 fsl,pins = < 601 MX6QDL_PAD_EIM_DA9__GPIO3_IO09 0xb0b1 602 >; 603 }; 604 605 pinctrl_i2c3_mag3110_int: i2c3mag3110intgrp { 606 fsl,pins = < 607 MX6QDL_PAD_EIM_D16__GPIO3_IO16 0xb0b1 608 >; 609 }; 610 611 pinctrl_ipu1_csi0: ipu1csi0grp { 612 fsl,pins = < 613 MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 0x1b0b0 614 MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13 0x1b0b0 615 MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14 0x1b0b0 616 MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15 0x1b0b0 617 MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16 0x1b0b0 618 MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17 0x1b0b0 619 MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18 0x1b0b0 620 MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19 0x1b0b0 621 MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0x1b0b0 622 MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC 0x1b0b0 623 MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC 0x1b0b0 624 >; 625 }; 626 627 pinctrl_ov5640: ov5640grp { 628 fsl,pins = < 629 MX6QDL_PAD_SD1_DAT2__GPIO1_IO19 0x1b0b0 630 MX6QDL_PAD_SD1_CLK__GPIO1_IO20 0x1b0b0 631 >; 632 }; 633 634 pinctrl_ov5642: ov5642grp { 635 fsl,pins = < 636 MX6QDL_PAD_SD1_DAT0__GPIO1_IO16 0x1b0b0 637 MX6QDL_PAD_SD1_DAT1__GPIO1_IO17 0x1b0b0 638 >; 639 }; 640 641 pinctrl_pcie: pciegrp { 642 fsl,pins = < 643 MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x1b0b0 644 >; 645 }; 646 647 pinctrl_pcie_reg: pciereggrp { 648 fsl,pins = < 649 MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x1b0b0 650 >; 651 }; 652 653 pinctrl_pwm1: pwm1grp { 654 fsl,pins = < 655 MX6QDL_PAD_SD1_DAT3__PWM1_OUT 0x1b0b1 656 >; 657 }; 658 659 pinctrl_sensors_reg: sensorsreggrp { 660 fsl,pins = < 661 MX6QDL_PAD_EIM_EB3__GPIO2_IO31 0x1b0b0 662 >; 663 }; 664 665 pinctrl_uart1: uart1grp { 666 fsl,pins = < 667 MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1 668 MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1 669 >; 670 }; 671 672 pinctrl_usbotg: usbotggrp { 673 fsl,pins = < 674 MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059 675 >; 676 }; 677 678 pinctrl_usdhc2: usdhc2grp { 679 fsl,pins = < 680 MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059 681 MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059 682 MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059 683 MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059 684 MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059 685 MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059 686 MX6QDL_PAD_NANDF_D4__SD2_DATA4 0x17059 687 MX6QDL_PAD_NANDF_D5__SD2_DATA5 0x17059 688 MX6QDL_PAD_NANDF_D6__SD2_DATA6 0x17059 689 MX6QDL_PAD_NANDF_D7__SD2_DATA7 0x17059 690 >; 691 }; 692 693 pinctrl_usdhc3: usdhc3grp { 694 fsl,pins = < 695 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 696 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 697 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 698 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 699 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 700 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 701 MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059 702 MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059 703 MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059 704 MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059 705 >; 706 }; 707 708 pinctrl_usdhc4: usdhc4grp { 709 fsl,pins = < 710 MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059 711 MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10059 712 MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059 713 MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059 714 MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059 715 MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059 716 MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x17059 717 MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x17059 718 MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x17059 719 MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x17059 720 >; 721 }; 722 723 pinctrl_wdog: wdoggrp { 724 fsl,pins = < 725 MX6QDL_PAD_GPIO_1__WDOG2_B 0x1b0b0 726 >; 727 }; 728 729 pinctrl_gpio_leds: gpioledsgrp { 730 fsl,pins = < 731 MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b0b0 732 >; 733 }; 734}; 735 736&ldb { 737 status = "okay"; 738 739 lvds-channel@1 { 740 fsl,data-mapping = "spwg"; 741 fsl,data-width = <18>; 742 status = "okay"; 743 744 port@4 { 745 reg = <4>; 746 747 lvds0_out: endpoint { 748 remote-endpoint = <&panel_in>; 749 }; 750 }; 751 }; 752}; 753 754&pcie { 755 pinctrl-names = "default"; 756 pinctrl-0 = <&pinctrl_pcie>; 757 reset-gpio = <&gpio7 12 GPIO_ACTIVE_LOW>; 758 vpcie-supply = <®_pcie>; 759 status = "okay"; 760}; 761 762&pwm1 { 763 pinctrl-names = "default"; 764 pinctrl-0 = <&pinctrl_pwm1>; 765 status = "okay"; 766}; 767 768®_arm { 769 vin-supply = <&sw1a_reg>; 770}; 771 772®_pu { 773 vin-supply = <&sw1c_reg>; 774}; 775 776®_soc { 777 vin-supply = <&sw1c_reg>; 778}; 779 780®_vdd1p1 { 781 vin-supply = <&vgen5_reg>; 782}; 783 784®_vdd2p5 { 785 vin-supply = <&vgen5_reg>; 786}; 787 788&snvs_poweroff { 789 status = "okay"; 790}; 791 792&snvs_pwrkey { 793 status = "okay"; 794}; 795 796&ssi2 { 797 status = "okay"; 798}; 799 800&uart1 { 801 pinctrl-names = "default"; 802 pinctrl-0 = <&pinctrl_uart1>; 803 status = "okay"; 804}; 805 806&usbh1 { 807 vbus-supply = <®_usb_h1_vbus>; 808 status = "okay"; 809}; 810 811&usbotg { 812 vbus-supply = <®_usb_otg_vbus>; 813 pinctrl-names = "default"; 814 pinctrl-0 = <&pinctrl_usbotg>; 815 disable-over-current; 816 dr_mode = "otg"; 817 status = "okay"; 818}; 819 820&usdhc2 { 821 pinctrl-names = "default"; 822 pinctrl-0 = <&pinctrl_usdhc2>; 823 bus-width = <8>; 824 cd-gpios = <&gpio2 2 GPIO_ACTIVE_LOW>; 825 wp-gpios = <&gpio2 3 GPIO_ACTIVE_HIGH>; 826 status = "okay"; 827}; 828 829&usdhc3 { 830 pinctrl-names = "default"; 831 pinctrl-0 = <&pinctrl_usdhc3>; 832 bus-width = <8>; 833 cd-gpios = <&gpio2 0 GPIO_ACTIVE_LOW>; 834 wp-gpios = <&gpio2 1 GPIO_ACTIVE_HIGH>; 835 status = "okay"; 836}; 837 838&usdhc4 { 839 pinctrl-names = "default"; 840 pinctrl-0 = <&pinctrl_usdhc4>; 841 bus-width = <8>; 842 non-removable; 843 no-1-8-v; 844 status = "okay"; 845}; 846 847&wdog1 { 848 status = "disabled"; 849}; 850 851&wdog2 { 852 pinctrl-names = "default"; 853 pinctrl-0 = <&pinctrl_wdog>; 854 fsl,ext-reset-output; 855 status = "okay"; 856};
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