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imx6qdl-nitrogen6_max.dtsi
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linux-6.19.14/arch/arm/boot/dts/nxp/imx/imx6qdl-nitrogen6_max.dtsi
1// SPDX-License-Identifier: GPL-2.0 OR X11 2/* 3 * Copyright 2015 Boundary Devices, Inc. 4 */ 5#include <dt-bindings/gpio/gpio.h> 6#include <dt-bindings/input/input.h> 7 8/ { 9 chosen { 10 stdout-path = &uart2; 11 }; 12 13 memory@10000000 { 14 device_type = "memory"; 15 reg = <0x10000000 0xF0000000>; 16 }; 17 18 reg_1p8v: regulator-1p8v { 19 compatible = "regulator-fixed"; 20 regulator-name = "1P8V"; 21 regulator-min-microvolt = <1800000>; 22 regulator-max-microvolt = <1800000>; 23 regulator-always-on; 24 }; 25 26 reg_2p5v: regulator-2p5v { 27 compatible = "regulator-fixed"; 28 regulator-name = "2P5V"; 29 regulator-min-microvolt = <2500000>; 30 regulator-max-microvolt = <2500000>; 31 regulator-always-on; 32 }; 33 34 reg_3p3v: regulator-3p3v { 35 compatible = "regulator-fixed"; 36 regulator-name = "3P3V"; 37 regulator-min-microvolt = <3300000>; 38 regulator-max-microvolt = <3300000>; 39 regulator-always-on; 40 }; 41 42 reg_usb_otg_vbus: regulator-usb-otg { 43 compatible = "regulator-fixed"; 44 regulator-name = "usb_otg_vbus"; 45 regulator-min-microvolt = <5000000>; 46 regulator-max-microvolt = <5000000>; 47 gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>; 48 enable-active-high; 49 }; 50 51 reg_usb_h1_vbus: regulator-usb-h1-vbus { 52 compatible = "regulator-fixed"; 53 pinctrl-names = "default"; 54 pinctrl-0 = <&pinctrl_usbh1>; 55 regulator-name = "usb_h1_vbus"; 56 regulator-min-microvolt = <3300000>; 57 regulator-max-microvolt = <3300000>; 58 gpio = <&gpio7 12 GPIO_ACTIVE_HIGH>; 59 enable-active-high; 60 }; 61 62 reg_wlan_vmmc: regulator-wlan-vmmc { 63 compatible = "regulator-fixed"; 64 pinctrl-names = "default"; 65 pinctrl-0 = <&pinctrl_wlan_vmmc>; 66 regulator-name = "reg_wlan_vmmc"; 67 regulator-min-microvolt = <3300000>; 68 regulator-max-microvolt = <3300000>; 69 gpio = <&gpio6 15 GPIO_ACTIVE_HIGH>; 70 startup-delay-us = <70000>; 71 enable-active-high; 72 }; 73 74 reg_can_xcvr: regulator-can-xcvr { 75 compatible = "regulator-fixed"; 76 regulator-name = "CAN XCVR"; 77 regulator-min-microvolt = <3300000>; 78 regulator-max-microvolt = <3300000>; 79 pinctrl-names = "default"; 80 pinctrl-0 = <&pinctrl_can_xcvr>; 81 gpio = <&gpio1 2 GPIO_ACTIVE_LOW>; 82 }; 83 84 gpio-keys { 85 compatible = "gpio-keys"; 86 pinctrl-names = "default"; 87 pinctrl-0 = <&pinctrl_gpio_keys>; 88 89 key-power { 90 label = "Power Button"; 91 gpios = <&gpio2 3 GPIO_ACTIVE_LOW>; 92 linux,code = <KEY_POWER>; 93 wakeup-source; 94 }; 95 96 key-menu { 97 label = "Menu"; 98 gpios = <&gpio2 1 GPIO_ACTIVE_LOW>; 99 linux,code = <KEY_MENU>; 100 }; 101 102 key-home { 103 label = "Home"; 104 gpios = <&gpio2 4 GPIO_ACTIVE_LOW>; 105 linux,code = <KEY_HOME>; 106 }; 107 108 key-back { 109 label = "Back"; 110 gpios = <&gpio2 2 GPIO_ACTIVE_LOW>; 111 linux,code = <KEY_BACK>; 112 }; 113 114 key-volume-up { 115 label = "Volume Up"; 116 gpios = <&gpio7 13 GPIO_ACTIVE_LOW>; 117 linux,code = <KEY_VOLUMEUP>; 118 }; 119 120 key-volume-down { 121 label = "Volume Down"; 122 gpios = <&gpio7 1 GPIO_ACTIVE_LOW>; 123 linux,code = <KEY_VOLUMEDOWN>; 124 }; 125 }; 126 127 i2c-mux-2 { 128 compatible = "i2c-mux-gpio"; 129 pinctrl-names = "default"; 130 pinctrl-0 = <&pinctrl_i2c2mux>; 131 #address-cells = <1>; 132 #size-cells = <0>; 133 mux-gpios = <&gpio3 20 GPIO_ACTIVE_HIGH 134 &gpio4 15 GPIO_ACTIVE_HIGH>; 135 i2c-parent = <&i2c2>; 136 idle-state = <0>; 137 138 i2c@1 { 139 reg = <1>; 140 #address-cells = <1>; 141 #size-cells = <0>; 142 }; 143 144 i2c@2 { 145 reg = <2>; 146 #address-cells = <1>; 147 #size-cells = <0>; 148 }; 149 }; 150 151 i2c-mux-3 { 152 compatible = "i2c-mux-gpio"; 153 pinctrl-names = "default"; 154 pinctrl-0 = <&pinctrl_i2c3mux>; 155 #address-cells = <1>; 156 #size-cells = <0>; 157 mux-gpios = <&gpio2 25 GPIO_ACTIVE_HIGH>; 158 i2c-parent = <&i2c3>; 159 idle-state = <0>; 160 161 i2c@1 { 162 reg = <1>; 163 #address-cells = <1>; 164 #size-cells = <0>; 165 }; 166 }; 167 168 leds { 169 compatible = "gpio-leds"; 170 171 led-speaker-enable { 172 gpios = <&gpio1 29 GPIO_ACTIVE_HIGH>; 173 retain-state-suspended; 174 default-state = "off"; 175 }; 176 177 led-ttymxc4-rs232 { 178 gpios = <&gpio6 10 GPIO_ACTIVE_HIGH>; 179 retain-state-suspended; 180 default-state = "on"; 181 }; 182 }; 183 184 backlight_lcd: backlight-lcd { 185 compatible = "pwm-backlight"; 186 pwms = <&pwm1 0 5000000 0>; 187 brightness-levels = <0 4 8 16 32 64 128 255>; 188 default-brightness-level = <7>; 189 power-supply = <®_3p3v>; 190 status = "okay"; 191 }; 192 193 backlight_lvds0: backlight-lvds0 { 194 compatible = "pwm-backlight"; 195 pwms = <&pwm4 0 5000000 0>; 196 brightness-levels = <0 4 8 16 32 64 128 255>; 197 default-brightness-level = <7>; 198 power-supply = <®_3p3v>; 199 status = "okay"; 200 }; 201 202 backlight_lvds1: backlight-lvds1 { 203 compatible = "pwm-backlight"; 204 pwms = <&pwm2 0 5000000 0>; 205 brightness-levels = <0 4 8 16 32 64 128 255>; 206 default-brightness-level = <7>; 207 power-supply = <®_3p3v>; 208 status = "okay"; 209 }; 210 211 lcd_display: disp0 { 212 compatible = "fsl,imx-parallel-display"; 213 #address-cells = <1>; 214 #size-cells = <0>; 215 interface-pix-fmt = "bgr666"; 216 pinctrl-names = "default"; 217 pinctrl-0 = <&pinctrl_j15>; 218 status = "okay"; 219 220 port@0 { 221 reg = <0>; 222 223 lcd_display_in: endpoint { 224 remote-endpoint = <&ipu1_di0_disp0>; 225 }; 226 }; 227 228 port@1 { 229 reg = <1>; 230 231 lcd_display_out: endpoint { 232 remote-endpoint = <&lcd_panel_in>; 233 }; 234 }; 235 }; 236 237 panel-lcd { 238 compatible = "okaya,rs800480t-7x0gp"; 239 backlight = <&backlight_lcd>; 240 power-supply = <®_3p3v>; 241 242 port { 243 lcd_panel_in: endpoint { 244 remote-endpoint = <&lcd_display_out>; 245 }; 246 }; 247 }; 248 249 panel-lvds0 { 250 compatible = "hannstar,hsd100pxn1"; 251 backlight = <&backlight_lvds0>; 252 power-supply = <®_3p3v>; 253 254 port { 255 panel_in_lvds0: endpoint { 256 remote-endpoint = <&lvds0_out>; 257 }; 258 }; 259 }; 260 261 panel-lvds1 { 262 compatible = "hannstar,hsd100pxn1"; 263 backlight = <&backlight_lvds1>; 264 power-supply = <®_3p3v>; 265 266 port { 267 panel_in_lvds1: endpoint { 268 remote-endpoint = <&lvds1_out>; 269 }; 270 }; 271 }; 272 273 sound { 274 compatible = "fsl,imx6q-nitrogen6_max-sgtl5000", 275 "fsl,imx-audio-sgtl5000"; 276 model = "imx6q-nitrogen6_max-sgtl5000"; 277 ssi-controller = <&ssi1>; 278 audio-codec = <&codec>; 279 audio-routing = 280 "MIC_IN", "Mic Jack", 281 "Mic Jack", "Mic Bias", 282 "Headphone Jack", "HP_OUT"; 283 mux-int-port = <1>; 284 mux-ext-port = <3>; 285 }; 286}; 287 288&audmux { 289 pinctrl-names = "default"; 290 pinctrl-0 = <&pinctrl_audmux>; 291 status = "okay"; 292}; 293 294&can1 { 295 pinctrl-names = "default"; 296 pinctrl-0 = <&pinctrl_can1>; 297 xceiver-supply = <®_can_xcvr>; 298 status = "okay"; 299}; 300 301&clks { 302 assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, 303 <&clks IMX6QDL_CLK_LDB_DI1_SEL>; 304 assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>, 305 <&clks IMX6QDL_CLK_PLL3_USB_OTG>; 306}; 307 308&ecspi1 { 309 cs-gpios = <&gpio3 19 GPIO_ACTIVE_LOW>; 310 pinctrl-names = "default"; 311 pinctrl-0 = <&pinctrl_ecspi1>; 312 status = "okay"; 313 314 flash: flash@0 { 315 compatible = "microchip,sst25vf016b"; 316 spi-max-frequency = <20000000>; 317 reg = <0>; 318 }; 319}; 320 321&fec { 322 pinctrl-names = "default"; 323 pinctrl-0 = <&pinctrl_enet>; 324 phy-mode = "rgmii"; 325 phy-handle = <ðphy>; 326 phy-reset-gpios = <&gpio1 27 GPIO_ACTIVE_LOW>; 327 /delete-property/ interrupts; 328 interrupts-extended = <&gpio1 6 IRQ_TYPE_LEVEL_HIGH>, 329 <&intc 0 119 IRQ_TYPE_LEVEL_HIGH>; 330 fsl,err006687-workaround-present; 331 status = "okay"; 332 333 mdio { 334 #address-cells = <1>; 335 #size-cells = <0>; 336 337 ethphy: ethernet-phy { 338 compatible = "ethernet-phy-ieee802.3-c22"; 339 txen-skew-ps = <0>; 340 txc-skew-ps = <3000>; 341 rxdv-skew-ps = <0>; 342 rxc-skew-ps = <3000>; 343 rxd0-skew-ps = <0>; 344 rxd1-skew-ps = <0>; 345 rxd2-skew-ps = <0>; 346 rxd3-skew-ps = <0>; 347 txd0-skew-ps = <0>; 348 txd1-skew-ps = <0>; 349 txd2-skew-ps = <0>; 350 txd3-skew-ps = <0>; 351 }; 352 }; 353}; 354 355&hdmi { 356 ddc-i2c-bus = <&i2c2>; 357 status = "okay"; 358}; 359 360&i2c1 { 361 clock-frequency = <100000>; 362 pinctrl-names = "default"; 363 pinctrl-0 = <&pinctrl_i2c1>; 364 status = "okay"; 365 366 codec: sgtl5000@a { 367 compatible = "fsl,sgtl5000"; 368 pinctrl-names = "default"; 369 pinctrl-0 = <&pinctrl_sgtl5000>; 370 reg = <0x0a>; 371 #sound-dai-cells = <0>; 372 clocks = <&clks IMX6QDL_CLK_CKO>; 373 VDDA-supply = <®_2p5v>; 374 VDDIO-supply = <®_3p3v>; 375 }; 376 377 rtc: rtc@68 { 378 compatible = "microcrystal,rv4162"; 379 pinctrl-names = "default"; 380 pinctrl-0 = <&pinctrl_rv4162>; 381 reg = <0x68>; 382 interrupts-extended = <&gpio4 6 IRQ_TYPE_LEVEL_LOW>; 383 }; 384}; 385 386&i2c2 { 387 clock-frequency = <100000>; 388 pinctrl-names = "default"; 389 pinctrl-0 = <&pinctrl_i2c2>; 390 status = "okay"; 391}; 392 393&i2c3 { 394 clock-frequency = <100000>; 395 pinctrl-names = "default"; 396 pinctrl-0 = <&pinctrl_i2c3>; 397 status = "okay"; 398 399 touchscreen@4 { 400 compatible = "eeti,egalax_ts"; 401 reg = <0x04>; 402 interrupt-parent = <&gpio1>; 403 interrupts = <9 IRQ_TYPE_EDGE_FALLING>; 404 wakeup-gpios = <&gpio1 9 GPIO_ACTIVE_LOW>; 405 }; 406 407 touchscreen@38 { 408 compatible = "edt,edt-ft5x06"; 409 reg = <0x38>; 410 interrupt-parent = <&gpio1>; 411 interrupts = <9 IRQ_TYPE_EDGE_FALLING>; 412 wakeup-source; 413 }; 414}; 415 416&iomuxc { 417 pinctrl_audmux: audmuxgrp { 418 fsl,pins = < 419 MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x130b0 420 MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x130b0 421 MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x110b0 422 MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x130b0 423 >; 424 }; 425 426 pinctrl_can1: can1grp { 427 fsl,pins = < 428 MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x1b0b0 429 MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b0b0 430 >; 431 }; 432 433 pinctrl_can_xcvr: can-xcvrgrp { 434 fsl,pins = < 435 /* Flexcan XCVR enable */ 436 MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b0b0 437 >; 438 }; 439 440 pinctrl_ecspi1: ecspi1grp { 441 fsl,pins = < 442 MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1 443 MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1 444 MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1 445 MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x000b1 446 >; 447 }; 448 449 pinctrl_enet: enetgrp { 450 fsl,pins = < 451 MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x100b0 452 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x100b0 453 MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x10030 454 MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x10030 455 MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x10030 456 MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x10030 457 MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x10030 458 MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x10030 459 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x100b0 460 MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 461 MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 462 MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 463 MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 464 MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 465 MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 466 /* Phy reset */ 467 MX6QDL_PAD_ENET_RXD0__GPIO1_IO27 0x0f0b0 468 MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x1b0b0 469 MX6QDL_PAD_GPIO_6__ENET_IRQ 0x000b1 470 >; 471 }; 472 473 pinctrl_gpio_keys: gpio-keysgrp { 474 fsl,pins = < 475 /* Power Button */ 476 MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x1b0b0 477 /* Menu Button */ 478 MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x1b0b0 479 /* Home Button */ 480 MX6QDL_PAD_NANDF_D4__GPIO2_IO04 0x1b0b0 481 /* Back Button */ 482 MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x1b0b0 483 /* Volume Up Button */ 484 MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x1b0b0 485 /* Volume Down Button */ 486 MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0x1b0b0 487 >; 488 }; 489 490 pinctrl_i2c1: i2c1grp { 491 fsl,pins = < 492 MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 493 MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 494 >; 495 }; 496 497 pinctrl_i2c2: i2c2grp { 498 fsl,pins = < 499 MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 500 MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 501 >; 502 }; 503 504 pinctrl_i2c2mux: i2c2muxgrp { 505 fsl,pins = < 506 /* ov5642 camera i2c enable */ 507 MX6QDL_PAD_EIM_D20__GPIO3_IO20 0x000b0 508 /* ov5640_mipi camera i2c enable */ 509 MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x000b0 510 >; 511 }; 512 513 pinctrl_i2c3: i2c3grp { 514 fsl,pins = < 515 MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1 516 MX6QDL_PAD_GPIO_16__I2C3_SDA 0x4001b8b1 517 MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x1b0b0 518 >; 519 }; 520 521 pinctrl_i2c3mux: i2c3muxgrp { 522 fsl,pins = < 523 /* PCIe I2C enable */ 524 MX6QDL_PAD_EIM_OE__GPIO2_IO25 0x000b0 525 >; 526 }; 527 528 pinctrl_j15: j15grp { 529 fsl,pins = < 530 MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10 531 MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x10 532 MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x10 533 MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x10 534 MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x10 535 MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x10 536 MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x10 537 MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x10 538 MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x10 539 MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x10 540 MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x10 541 MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x10 542 MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x10 543 MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x10 544 MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x10 545 MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x10 546 MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x10 547 MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x10 548 MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x10 549 MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x10 550 MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x10 551 MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x10 552 MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0x10 553 MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0x10 554 MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0x10 555 MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0x10 556 MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0x10 557 MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0x10 558 >; 559 }; 560 561 pinctrl_pcie: pciegrp { 562 fsl,pins = < 563 /* PCIe reset */ 564 MX6QDL_PAD_EIM_BCLK__GPIO6_IO31 0x000b0 565 >; 566 }; 567 568 pinctrl_pwm1: pwm1grp { 569 fsl,pins = < 570 MX6QDL_PAD_SD1_DAT3__PWM1_OUT 0x1b0b1 571 >; 572 }; 573 574 pinctrl_pwm2: pwm2grp { 575 fsl,pins = < 576 MX6QDL_PAD_SD1_DAT2__PWM2_OUT 0x1b0b1 577 >; 578 }; 579 580 pinctrl_pwm3: pwm3grp { 581 fsl,pins = < 582 MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x1b0b1 583 >; 584 }; 585 586 pinctrl_pwm4: pwm4grp { 587 fsl,pins = < 588 MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x1b0b1 589 >; 590 }; 591 592 pinctrl_rv4162: rv4162grp { 593 fsl,pins = < 594 MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x1b0b0 595 >; 596 }; 597 598 pinctrl_sgtl5000: sgtl5000grp { 599 fsl,pins = < 600 MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x000b0 601 MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x1b0b0 602 MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x1b0b0 603 >; 604 }; 605 606 pinctrl_uart1: uart1grp { 607 fsl,pins = < 608 MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1 609 MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1 610 >; 611 }; 612 613 pinctrl_uart2: uart2grp { 614 fsl,pins = < 615 MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1 616 MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1 617 >; 618 }; 619 620 pinctrl_uart5: uart5grp { 621 fsl,pins = < 622 MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x130b1 623 MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x030b1 624 /* RS485 RX Enable: pull up */ 625 MX6QDL_PAD_NANDF_RB0__GPIO6_IO10 0x1b0b1 626 /* RS485 DEN: pull down */ 627 MX6QDL_PAD_NANDF_CLE__GPIO6_IO07 0x030b1 628 /* RS485/!RS232 Select: pull down (rs232) */ 629 MX6QDL_PAD_EIM_CS1__GPIO2_IO24 0x030b1 630 /* ON: pull down */ 631 MX6QDL_PAD_NANDF_ALE__GPIO6_IO08 0x030b1 632 >; 633 }; 634 635 pinctrl_usbh1: usbh1grp { 636 fsl,pins = < 637 MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x0b0b0 638 >; 639 }; 640 641 pinctrl_usbotg: usbotggrp { 642 fsl,pins = < 643 MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 644 MX6QDL_PAD_KEY_COL4__USB_OTG_OC 0x1b0b0 645 /* power enable, high active */ 646 MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x000b0 647 >; 648 }; 649 650 pinctrl_usdhc2: usdhc2grp { 651 fsl,pins = < 652 MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059 653 MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059 654 MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059 655 MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059 656 MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059 657 MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059 658 >; 659 }; 660 661 pinctrl_usdhc3: usdhc3grp { 662 fsl,pins = < 663 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 664 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 665 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 666 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 667 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 668 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 669 MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x100b0 670 MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x1b0b0 671 >; 672 }; 673 674 pinctrl_usdhc4: usdhc4grp { 675 fsl,pins = < 676 MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059 677 MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10059 678 MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059 679 MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059 680 MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059 681 MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059 682 MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x17059 683 MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x17059 684 MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x17059 685 MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x17059 686 >; 687 }; 688 689 pinctrl_wlan_vmmc: wlan-vmmcgrp { 690 fsl,pins = < 691 MX6QDL_PAD_NANDF_CS0__GPIO6_IO11 0x100b0 692 MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x000b0 693 MX6QDL_PAD_NANDF_CS3__GPIO6_IO16 0x000b0 694 MX6QDL_PAD_SD1_CLK__OSC32K_32K_OUT 0x000b0 695 >; 696 }; 697}; 698 699&ipu1_di0_disp0 { 700 remote-endpoint = <&lcd_display_in>; 701}; 702 703&ldb { 704 status = "okay"; 705 706 lvds-channel@0 { 707 status = "okay"; 708 709 port@4 { 710 reg = <4>; 711 712 lvds0_out: endpoint { 713 remote-endpoint = <&panel_in_lvds0>; 714 }; 715 }; 716 }; 717 718 lvds-channel@1 { 719 status = "okay"; 720 721 port@4 { 722 reg = <4>; 723 724 lvds1_out: endpoint { 725 remote-endpoint = <&panel_in_lvds1>; 726 }; 727 }; 728 }; 729}; 730 731&pcie { 732 pinctrl-names = "default"; 733 pinctrl-0 = <&pinctrl_pcie>; 734 reset-gpio = <&gpio6 31 GPIO_ACTIVE_LOW>; 735 status = "okay"; 736}; 737 738&pwm1 { 739 pinctrl-names = "default"; 740 pinctrl-0 = <&pinctrl_pwm1>; 741 status = "okay"; 742}; 743 744&pwm2 { 745 pinctrl-names = "default"; 746 pinctrl-0 = <&pinctrl_pwm2>; 747 status = "okay"; 748}; 749 750&pwm3 { 751 pinctrl-names = "default"; 752 pinctrl-0 = <&pinctrl_pwm3>; 753 status = "okay"; 754}; 755 756&pwm4 { 757 pinctrl-names = "default"; 758 pinctrl-0 = <&pinctrl_pwm4>; 759 status = "okay"; 760}; 761 762&ssi1 { 763 status = "okay"; 764}; 765 766&uart1 { 767 pinctrl-names = "default"; 768 pinctrl-0 = <&pinctrl_uart1>; 769 status = "okay"; 770}; 771 772&uart2 { 773 pinctrl-names = "default"; 774 pinctrl-0 = <&pinctrl_uart2>; 775 status = "okay"; 776}; 777 778&uart5 { 779 pinctrl-names = "default"; 780 pinctrl-0 = <&pinctrl_uart5>; 781 status = "okay"; 782}; 783 784&usbh1 { 785 vbus-supply = <®_usb_h1_vbus>; 786 status = "okay"; 787}; 788 789&usbotg { 790 vbus-supply = <®_usb_otg_vbus>; 791 pinctrl-names = "default"; 792 pinctrl-0 = <&pinctrl_usbotg>; 793 disable-over-current; 794 status = "okay"; 795}; 796 797&usdhc2 { 798 pinctrl-names = "default"; 799 pinctrl-0 = <&pinctrl_usdhc2>; 800 bus-width = <4>; 801 non-removable; 802 vmmc-supply = <®_wlan_vmmc>; 803 cap-power-off-card; 804 keep-power-in-suspend; 805 status = "okay"; 806 807 #address-cells = <1>; 808 #size-cells = <0>; 809 wlcore: wlcore@2 { 810 compatible = "ti,wl1271"; 811 reg = <2>; 812 interrupt-parent = <&gpio6>; 813 interrupts = <11 IRQ_TYPE_LEVEL_HIGH>; 814 ref-clock-frequency = <38400000>; 815 }; 816}; 817 818&usdhc3 { 819 pinctrl-names = "default"; 820 pinctrl-0 = <&pinctrl_usdhc3>; 821 cd-gpios = <&gpio7 0 GPIO_ACTIVE_LOW>; 822 bus-width = <4>; 823 vmmc-supply = <®_3p3v>; 824 status = "okay"; 825}; 826 827&usdhc4 { 828 pinctrl-names = "default"; 829 pinctrl-0 = <&pinctrl_usdhc4>; 830 bus-width = <8>; 831 non-removable; 832 vmmc-supply = <®_1p8v>; 833 keep-power-in-suspend; 834 status = "okay"; 835};
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