imx6q-bx50v3.dtsi

  1/*
  2 * Copyright 2015 Timesys Corporation.
  3 * Copyright 2015 General Electric Company
  4 *
  5 * This file is dual-licensed: you can use it either under the terms
  6 * of the GPL or the X11 license, at your option. Note that this dual
  7 * licensing only applies to this file, and not this project as a
  8 * whole.
  9 *
 10 *  a) This file is free software; you can redistribute it and/or
 11 *     modify it under the terms of the GNU General Public License
 12 *     version 2 as published by the Free Software Foundation.
 13 *
 14 *     This file is distributed in the hope that it will be useful,
 15 *     but WITHOUT ANY WARRANTY; without even the implied warranty of
 16 *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 17 *     GNU General Public License for more details.
 18 *
 19 * Or, alternatively,
 20 *
 21 *  b) Permission is hereby granted, free of charge, to any person
 22 *     obtaining a copy of this software and associated documentation
 23 *     files (the "Software"), to deal in the Software without
 24 *     restriction, including without limitation the rights to use,
 25 *     copy, modify, merge, publish, distribute, sublicense, and/or
 26 *     sell copies of the Software, and to permit persons to whom the
 27 *     Software is furnished to do so, subject to the following
 28 *     conditions:
 29 *
 30 *     The above copyright notice and this permission notice shall be
 31 *     included in all copies or substantial portions of the Software.
 32 *
 33 *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
 34 *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
 35 *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
 36 *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
 37 *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
 38 *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 39 *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 40 *     OTHER DEALINGS IN THE SOFTWARE.
 41 */
 42
 43#include "imx6q-ba16.dtsi"
 44
 45/ {
 46	mclk: clock-mclk {
 47		compatible = "fixed-clock";
 48		#clock-cells = <0>;
 49		clock-frequency = <22000000>;
 50	};
 51
 52	gpio-poweroff {
 53		compatible = "gpio-poweroff";
 54		gpios = <&gpio4 11 GPIO_ACTIVE_LOW>;
 55		status = "okay";
 56	};
 57
 58	reg_wl18xx_vmmc: regulator-wl18xx {
 59		compatible = "regulator-fixed";
 60		regulator-name = "vwl1807";
 61		regulator-min-microvolt = <3300000>;
 62		regulator-max-microvolt = <3300000>;
 63		gpio = <&pca9539 3 GPIO_ACTIVE_HIGH>;
 64		startup-delay-us = <70000>;
 65		enable-active-high;
 66	};
 67
 68	reg_wlan: regulator-wlan {
 69		compatible = "regulator-fixed";
 70		regulator-name = "3P3V_wlan";
 71		regulator-min-microvolt = <3300000>;
 72		regulator-max-microvolt = <3300000>;
 73		regulator-always-on;
 74		regulator-boot-on;
 75		gpio = <&gpio6 14 GPIO_ACTIVE_HIGH>;
 76	};
 77
 78	sound {
 79		compatible = "fsl,imx6q-ba16-sgtl5000",
 80			     "fsl,imx-audio-sgtl5000";
 81		model = "imx6q-ba16-sgtl5000";
 82		ssi-controller = <&ssi1>;
 83		audio-codec = <&sgtl5000>;
 84		audio-routing =
 85			"MIC_IN", "Mic Jack",
 86			"Mic Jack", "Mic Bias",
 87			"LINE_IN", "Line In Jack",
 88			"Headphone Jack", "HP_OUT";
 89		mux-int-port = <1>;
 90		mux-ext-port = <4>;
 91	};
 92
 93	aliases {
 94		mdio-gpio0 = &mdio0;
 95	};
 96
 97	mdio0: mdio {
 98		compatible = "virtual,mdio-gpio";
 99		gpios = <&gpio2 5 GPIO_ACTIVE_HIGH>, /* mdc */
100			<&gpio2 7 GPIO_ACTIVE_HIGH>; /* mdio */
101
102		#address-cells = <1>;
103		#size-cells = <0>;
104
105		switch: switch@0 {
106			compatible = "marvell,mv88e6085"; /* 88e6240*/
107			reg = <0>;
108
109			interrupt-parent = <&gpio2>;
110			interrupts = <2 IRQ_TYPE_LEVEL_LOW>;
111			interrupt-controller;
112			#interrupt-cells = <2>;
113
114			switch_ports: ports {
115				#address-cells = <1>;
116				#size-cells = <0>;
117			};
118
119			mdio {
120				#address-cells = <1>;
121				#size-cells = <0>;
122
123				switchphy0: switchphy@0 {
124					reg = <0>;
125					interrupt-parent = <&switch>;
126					interrupts = <0 IRQ_TYPE_LEVEL_HIGH>;
127				};
128
129				switchphy1: switchphy@1 {
130					reg = <1>;
131					interrupt-parent = <&switch>;
132					interrupts = <1 IRQ_TYPE_LEVEL_HIGH>;
133				};
134
135				switchphy2: switchphy@2 {
136					reg = <2>;
137					interrupt-parent = <&switch>;
138					interrupts = <2 IRQ_TYPE_LEVEL_HIGH>;
139				};
140
141				switchphy3: switchphy@3 {
142					reg = <3>;
143					interrupt-parent = <&switch>;
144					interrupts = <3 IRQ_TYPE_LEVEL_HIGH>;
145				};
146
147				switchphy4: switchphy@4 {
148					reg = <4>;
149					interrupt-parent = <&switch>;
150					interrupts = <4 IRQ_TYPE_LEVEL_HIGH>;
151				};
152			};
153		};
154	};
155};
156
157&ecspi5 {
158	cs-gpios = <&gpio1 17 GPIO_ACTIVE_LOW>;
159	pinctrl-names = "default";
160	pinctrl-0 = <&pinctrl_ecspi5>;
161	status = "okay";
162
163	m25_eeprom: eeprom@0 {
164		compatible = "atmel,at25";
165		spi-max-frequency = <10000000>;
166		size = <0x8000>;
167		pagesize = <64>;
168		reg = <0>;
169		address-width = <16>;
170	};
171};
172
173&i2c1 {
174	pinctrl-names = "default", "gpio";
175	pinctrl-1 = <&pinctrl_i2c1_gpio>;
176	sda-gpios = <&gpio5 26 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
177	scl-gpios = <&gpio5 27 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
178
179	pca9547: mux@70 {
180		compatible = "nxp,pca9547";
181		reg = <0x70>;
182		#address-cells = <1>;
183		#size-cells = <0>;
184
185		mux1_i2c1: i2c@0 {
186			#address-cells = <1>;
187			#size-cells = <0>;
188			reg = <0x0>;
189
190			ads7830: ads7830@48 {
191				compatible = "ti,ads7830";
192				reg = <0x48>;
193			};
194
195			mma8453: mma8453@1c {
196				compatible = "fsl,mma8453";
197				reg = <0x1c>;
198				vdd-supply = <&reg_3p3v>;
199				vddio-supply = <&reg_3p3v>;
200			};
201		};
202
203		mux1_i2c2: i2c@1 {
204			#address-cells = <1>;
205			#size-cells = <0>;
206			reg = <0x1>;
207
208			eeprom: eeprom@50 {
209				compatible = "atmel,24c08";
210				reg = <0x50>;
211			};
212
213			mpl3115: mpl3115@60 {
214				compatible = "fsl,mpl3115";
215				reg = <0x60>;
216				vdd-supply = <&reg_3p3v>;
217				vddio-supply = <&reg_3p3v>;
218			};
219		};
220
221		mux1_i2c3: i2c@2 {
222			#address-cells = <1>;
223			#size-cells = <0>;
224			reg = <0x2>;
225		};
226
227		mux1_i2c4: i2c@3 {
228			#address-cells = <1>;
229			#size-cells = <0>;
230			reg = <0x3>;
231
232			sgtl5000: codec@a {
233				compatible = "fsl,sgtl5000";
234				reg = <0x0a>;
235				#sound-dai-cells = <0>;
236				clocks = <&mclk>;
237				VDDA-supply = <&reg_1p8v>;
238				VDDIO-supply = <&reg_3p3v>;
239			};
240		};
241
242		mux1_i2c5: i2c@4 {
243			#address-cells = <1>;
244			#size-cells = <0>;
245			reg = <0x4>;
246
247			pca9539: pca9539@74 {
248				compatible = "nxp,pca9539";
249				reg = <0x74>;
250				gpio-controller;
251				#gpio-cells = <2>;
252				#interrupt-cells = <2>;
253				interrupt-controller;
254				interrupt-parent = <&gpio2>;
255				interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
256
257				P12-hog {
258					gpio-hog;
259					gpios = <10 0>;
260					output-low;
261					line-name = "PCA9539-P12";
262				};
263
264				P13-hog {
265					gpio-hog;
266					gpios = <11 0>;
267					output-low;
268					line-name = "PCA9539-P13";
269				};
270
271				P14-hog {
272					gpio-hog;
273					gpios = <12 0>;
274					output-low;
275					line-name = "PCA9539-P14";
276				};
277
278				P15-hog {
279					gpio-hog;
280					gpios = <13 0>;
281					output-low;
282					line-name = "PCA9539-P15";
283				};
284
285				P16-hog {
286					gpio-hog;
287					gpios = <14 0>;
288					output-low;
289					line-name = "PCA9539-P16";
290				};
291
292				P17-hog {
293					gpio-hog;
294					gpios = <15 0>;
295					output-low;
296					line-name = "PCA9539-P17";
297				};
298			};
299		};
300
301		mux1_i2c6: i2c@5 {
302			#address-cells = <1>;
303			#size-cells = <0>;
304			reg = <0x5>;
305		};
306
307		mux1_i2c7: i2c@6 {
308			#address-cells = <1>;
309			#size-cells = <0>;
310			reg = <0x6>;
311		};
312
313		mux1_i2c8: i2c@7 {
314			#address-cells = <1>;
315			#size-cells = <0>;
316			reg = <0x7>;
317		};
318	};
319};
320
321&i2c2 {
322	pinctrl-names = "default", "gpio";
323	pinctrl-1 = <&pinctrl_i2c2_gpio>;
324	sda-gpios = <&gpio4 13 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
325	scl-gpios = <&gpio4 12 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
326};
327
328&i2c3 {
329	pinctrl-names = "default", "gpio";
330	pinctrl-1 = <&pinctrl_i2c3_gpio>;
331	sda-gpios = <&gpio1 6 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
332	scl-gpios = <&gpio1 3 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
333};
334
335&iomuxc {
336	pinctrl_i2c1_gpio: i2c1gpiogrp {
337		fsl,pins = <
338			MX6QDL_PAD_CSI0_DAT8__GPIO5_IO26	0x1b0b0
339			MX6QDL_PAD_CSI0_DAT9__GPIO5_IO27	0x1b0b0
340		>;
341	};
342
343	pinctrl_i2c2_gpio: i2c2gpiogrp {
344		fsl,pins = <
345			MX6QDL_PAD_KEY_COL3__GPIO4_IO12	0x1b0b0
346			MX6QDL_PAD_KEY_ROW3__GPIO4_IO13	0x1b0b0
347		>;
348	};
349
350	pinctrl_i2c3_gpio: i2c3gpiogrp {
351		fsl,pins = <
352			MX6QDL_PAD_GPIO_3__GPIO1_IO03	0x1b0b0
353			MX6QDL_PAD_GPIO_6__GPIO1_IO06	0x1b0b0
354		>;
355	};
356};
357
358&pmu {
359	secure-reg-access;
360};
361
362&usdhc2 {
363	status = "disabled";
364};
365
366&usdhc4 {
367	pinctrl-names = "default";
368	pinctrl-0 = <&pinctrl_usdhc4>;
369	bus-width = <4>;
370	vmmc-supply = <&reg_wl18xx_vmmc>;
371	no-1-8-v;
372	non-removable;
373	wakeup-source;
374	keep-power-in-suspend;
375	cap-power-off-card;
376	max-frequency = <25000000>;
377	#address-cells = <1>;
378	#size-cells = <0>;
379	status = "okay";
380
381	wlcore: wlcore@2 {
382		compatible = "ti,wl1837";
383		reg = <2>;
384		interrupt-parent = <&gpio2>;
385		interrupts = <6 IRQ_TYPE_LEVEL_HIGH>;
386		tcxo-clock-frequency = <26000000>;
387	};
388};
389
390&pcie {
391	/* Synopsys, Inc. Device */
392	pci_root: root@0,0 {
393		compatible = "pci16c3,abcd";
394		reg = <0x00000000 0 0 0 0>;
395
396		#address-cells = <3>;
397		#size-cells = <2>;
398	};
399};
400
401&clks {
402	assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>,
403			  <&clks IMX6QDL_CLK_LDB_DI1_SEL>,
404			  <&clks IMX6QDL_CLK_IPU1_DI0_PRE_SEL>,
405			  <&clks IMX6QDL_CLK_IPU1_DI1_PRE_SEL>,
406			  <&clks IMX6QDL_CLK_IPU2_DI0_PRE_SEL>,
407			  <&clks IMX6QDL_CLK_IPU2_DI1_PRE_SEL>;
408	assigned-clock-parents = <&clks IMX6QDL_CLK_PLL5_VIDEO_DIV>,
409				 <&clks IMX6QDL_CLK_PLL5_VIDEO_DIV>,
410				 <&clks IMX6QDL_CLK_PLL2_PFD0_352M>,
411				 <&clks IMX6QDL_CLK_PLL2_PFD0_352M>,
412				 <&clks IMX6QDL_CLK_PLL2_PFD0_352M>,
413				 <&clks IMX6QDL_CLK_PLL2_PFD0_352M>;
414};