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imx6dl-qmx6.dtsi
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linux-6.19.14/arch/arm/boot/dts/nxp/imx/imx6dl-qmx6.dtsi
1// SPDX-License-Identifier: GPL-2.0 OR MIT 2// 3// Device Tree Source for i.MX6DL based congatec QMX6 4// System on Module 5// 6// Copyright 2018-2021 General Electric Company 7// Copyright 2018-2021 Collabora 8// Copyright 2016 congatec AG 9 10#include "imx6dl.dtsi" 11#include <dt-bindings/gpio/gpio.h> 12#include <dt-bindings/sound/fsl-imx-audmux.h> 13 14/ { 15 memory@10000000 { 16 reg = <0x10000000 0x40000000>; 17 device_type = "memory"; 18 }; 19 20 reg_3p3v: 3p3v { 21 compatible = "regulator-fixed"; 22 regulator-name = "3P3V"; 23 regulator-min-microvolt = <3300000>; 24 regulator-max-microvolt = <3300000>; 25 }; 26 27 i2cmux { 28 compatible = "i2c-mux-gpio"; 29 #address-cells = <1>; 30 #size-cells = <0>; 31 mux-gpios = <&gpio6 9 GPIO_ACTIVE_HIGH>; 32 i2c-parent = <&i2c2>; 33 34 i2c5: i2c@0 { 35 reg = <0>; 36 #address-cells = <1>; 37 #size-cells = <0>; 38 }; 39 40 i2c6: i2c@1 { 41 reg = <1>; 42 #address-cells = <1>; 43 #size-cells = <0>; 44 }; 45 }; 46}; 47 48&audmux { 49 pinctrl-names = "default"; 50 pinctrl-0 = <&pinctrl_audmux>; 51 52 mux-ssi1 { 53 fsl,audmux-port = <MX51_AUDMUX_PORT1_SSI0>; 54 fsl,port-config = < 55 (IMX_AUDMUX_V2_PTCR_TFSDIR | 56 IMX_AUDMUX_V2_PTCR_TFSEL(MX51_AUDMUX_PORT6) | 57 IMX_AUDMUX_V2_PTCR_TCLKDIR | 58 IMX_AUDMUX_V2_PTCR_TCSEL(MX51_AUDMUX_PORT6) | 59 IMX_AUDMUX_V2_PTCR_SYN) 60 IMX_AUDMUX_V2_PDCR_RXDSEL(MX51_AUDMUX_PORT6) 61 >; 62 }; 63 64 mux-aud6 { 65 fsl,audmux-port = <MX51_AUDMUX_PORT6>; 66 fsl,port-config = < 67 IMX_AUDMUX_V2_PTCR_SYN 68 IMX_AUDMUX_V2_PDCR_RXDSEL(MX51_AUDMUX_PORT1_SSI0) 69 >; 70 }; 71}; 72 73&clks { 74 clocks = <&rtc_sqw>; 75 clock-names = "ckil"; 76 assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, 77 <&clks IMX6QDL_CLK_LDB_DI1_SEL>; 78 assigned-clock-parents = <&clks IMX6QDL_CLK_PLL2_PFD0_352M>, 79 <&clks IMX6QDL_CLK_PLL2_PFD0_352M>; 80}; 81 82&ecspi1 { 83 cs-gpios = <&gpio3 19 GPIO_ACTIVE_LOW>; 84 pinctrl-names = "default"; 85 pinctrl-0 = <&pinctrl_spi1>; 86 status = "okay"; 87 88 flash@0 { 89 #address-cells = <1>; 90 #size-cells = <1>; 91 compatible = "sst,sst25vf032b", "jedec,spi-nor"; 92 spi-max-frequency = <20000000>; 93 reg = <0>; 94 95 partition@0 { 96 label = "bootloader"; 97 reg = <0x0000000 0x100000>; 98 }; 99 100 partition@100000 { 101 label = "user"; 102 reg = <0x0100000 0x2fc000>; 103 }; 104 105 partition@3fc000 { 106 label = "reserved"; 107 reg = <0x03fc000 0x4000>; 108 read-only; 109 }; 110 }; 111}; 112 113&fec { 114 pinctrl-names = "default"; 115 pinctrl-0 = <&pinctrl_enet &pinctrl_phy_reset>; 116 phy-mode = "rgmii-id"; 117 phy-reset-gpios = <&gpio3 23 GPIO_ACTIVE_LOW>; 118 fsl,magic-packet; 119 phy-handle = <&phy0>; 120 121 mdio { 122 #address-cells = <1>; 123 #size-cells = <0>; 124 125 phy0: ethernet-phy@6 { 126 reg = <6>; 127 qca,clk-out-frequency = <125000000>; 128 }; 129 }; 130}; 131 132&i2c1 { 133 clock-frequency = <100000>; 134 pinctrl-names = "default", "gpio"; 135 pinctrl-0 = <&pinctrl_i2c1>; 136 pinctrl-1 = <&pinctrl_i2c1_gpio>; 137 scl-gpios = <&gpio3 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 138 sda-gpios = <&gpio3 28 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 139 status = "okay"; 140}; 141 142&i2c2 { 143 clock-frequency = <100000>; 144 pinctrl-names = "default", "gpio"; 145 pinctrl-0 = <&pinctrl_i2c2>; 146 pinctrl-1 = <&pinctrl_i2c2_gpio>; 147 scl-gpios = <&gpio4 12 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 148 sda-gpios = <&gpio4 13 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 149 status = "okay"; 150}; 151 152&i2c3 { 153 clock-frequency = <100000>; 154 pinctrl-names = "default", "gpio"; 155 pinctrl-0 = <&pinctrl_i2c3>; 156 pinctrl-1 = <&pinctrl_i2c3_gpio>; 157 scl-gpios = <&gpio1 3 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 158 sda-gpios = <&gpio1 6 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 159 status = "okay"; 160 161 rtc: rtc@68 { 162 compatible = "st,m41t62"; 163 reg = <0x68>; 164 165 rtc_sqw: clock { 166 compatible = "fixed-clock"; 167 #clock-cells = <0>; 168 clock-frequency = <32768>; 169 }; 170 }; 171}; 172 173&i2c6 { 174 pmic@8 { 175 compatible = "fsl,pfuze100"; 176 reg = <0x08>; 177 178 regulators { 179 sw1a_reg: sw1ab { 180 regulator-min-microvolt = <300000>; 181 regulator-max-microvolt = <1875000>; 182 regulator-boot-on; 183 regulator-always-on; 184 regulator-ramp-delay = <6250>; 185 }; 186 187 sw1c_reg: sw1c { 188 regulator-min-microvolt = <300000>; 189 regulator-max-microvolt = <1875000>; 190 regulator-boot-on; 191 regulator-always-on; 192 regulator-ramp-delay = <6250>; 193 }; 194 195 sw2_reg: sw2 { 196 regulator-min-microvolt = <800000>; 197 regulator-max-microvolt = <3300000>; 198 regulator-boot-on; 199 regulator-always-on; 200 }; 201 202 sw3a_reg: sw3a { 203 regulator-min-microvolt = <400000>; 204 regulator-max-microvolt = <1975000>; 205 regulator-boot-on; 206 regulator-always-on; 207 }; 208 209 sw3b_reg: sw3b { 210 regulator-min-microvolt = <400000>; 211 regulator-max-microvolt = <1975000>; 212 regulator-boot-on; 213 regulator-always-on; 214 }; 215 216 sw4_reg: sw4 { 217 regulator-min-microvolt = <675000>; 218 regulator-max-microvolt = <3300000>; 219 regulator-boot-on; 220 regulator-always-on; 221 }; 222 223 swbst_reg: swbst { 224 regulator-min-microvolt = <5000000>; 225 regulator-max-microvolt = <5150000>; 226 }; 227 228 snvs_reg: vsnvs { 229 regulator-min-microvolt = <1000000>; 230 regulator-max-microvolt = <3000000>; 231 regulator-boot-on; 232 regulator-always-on; 233 }; 234 235 vref_reg: vrefddr { 236 regulator-boot-on; 237 regulator-always-on; 238 }; 239 240 /* 241 * keep VGEN3, VGEN4 and VGEN5 enabled in order to 242 * maintain backward compatibility with hw-rev. A.0 243 */ 244 vgen3_reg: vgen3 { 245 regulator-min-microvolt = <1800000>; 246 regulator-max-microvolt = <3300000>; 247 regulator-always-on; 248 }; 249 250 vgen4_reg: vgen4 { 251 regulator-min-microvolt = <2500000>; 252 regulator-max-microvolt = <2500000>; 253 regulator-always-on; 254 }; 255 256 vgen5_reg: vgen5 { 257 regulator-min-microvolt = <1800000>; 258 regulator-max-microvolt = <3300000>; 259 regulator-always-on; 260 }; 261 262 /* supply voltage for eMMC */ 263 vgen6_reg: vgen6 { 264 regulator-min-microvolt = <1800000>; 265 regulator-max-microvolt = <1800000>; 266 regulator-boot-on; 267 regulator-always-on; 268 }; 269 }; 270 }; 271}; 272 273&pcie { 274 reset-gpio = <&gpio1 20 0>; 275}; 276 277&pwm4 { 278 pinctrl-names = "default"; 279 pinctrl-0 = <&pinctrl_pwm4>; 280}; 281 282®_arm { 283 vin-supply = <&sw1a_reg>; 284}; 285 286®_pu { 287 vin-supply = <&sw1c_reg>; 288}; 289 290®_soc { 291 vin-supply = <&sw1c_reg>; 292}; 293 294&snvs_poweroff { 295 status = "okay"; 296}; 297 298&uart2 { 299 pinctrl-names = "default"; 300 pinctrl-0 = <&pinctrl_uart2>; 301 status = "okay"; 302}; 303 304&uart3 { 305 pinctrl-names = "default"; 306 pinctrl-0 = <&pinctrl_uart3>; 307 status = "okay"; 308}; 309 310&usbh1 { 311 /* Connected to USB-Hub SMSC USB2514, provides P0, P2, P3, P4 on Qseven connector */ 312 vbus-supply = <®_5v>; 313 status = "okay"; 314}; 315 316&usbotg { 317 pinctrl-names = "default"; 318 pinctrl-0 = <&pinctrl_usbotg>; 319}; 320 321&usdhc2 { 322 /* MicroSD card slot */ 323 pinctrl-names = "default"; 324 pinctrl-0 = <&pinctrl_usdhc2>; 325 cd-gpios = <&gpio1 4 GPIO_ACTIVE_LOW>; 326 no-1-8-v; 327 keep-power-in-suspend; 328 wakeup-source; 329 vmmc-supply = <®_3p3v>; 330 status = "okay"; 331}; 332 333&usdhc3 { 334 /* eMMC module */ 335 pinctrl-names = "default"; 336 pinctrl-0 = <&pinctrl_usdhc3>; 337 non-removable; 338 bus-width = <8>; 339 no-1-8-v; 340 keep-power-in-suspend; 341 wakeup-source; 342 vmmc-supply = <®_3p3v>; 343 status = "okay"; 344}; 345 346&wdog1 { 347 pinctrl-names = "default"; 348 pinctrl-0 = <&pinctrl_wdog>; 349 fsl,ext-reset-output; 350}; 351 352&iomuxc { 353 pinctrl-names = "default"; 354 pinctrl-0 = <&pinctrl_hog>; 355 356 pinctrl_audmux: audmuxgrp { 357 fsl,pins = < 358 MX6QDL_PAD_DI0_PIN2__AUD6_TXD 0x110b0 /* Q7[67] HDA_SDO */ 359 MX6QDL_PAD_DI0_PIN3__AUD6_TXFS 0x30b0 /* Q7[59] HDA_SYNC */ 360 MX6QDL_PAD_DI0_PIN4__AUD6_RXD 0x30b0 /* Q7[65] HDA_SDI */ 361 MX6QDL_PAD_DI0_PIN15__AUD6_TXC 0x30b0 /* Q7[63] HDA_BITCLK */ 362 >; 363 }; 364 365 /* PHY is on System on Module, Q7[3-15] have Ethernet lines */ 366 pinctrl_enet: enetgrp { 367 fsl,pins = < 368 MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 369 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 370 MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030 371 MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030 372 MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030 373 MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030 374 MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030 375 MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030 376 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 377 MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 378 MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 379 MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 380 MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 381 MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 382 MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 383 MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x1b0b0 384 >; 385 }; 386 387 pinctrl_hog: hoggrp { 388 fsl,pins = < 389 MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x80000000 /* PCIE_WAKE_B */ 390 MX6QDL_PAD_NANDF_WP_B__GPIO6_IO09 0x80000000 /* I2C multiplexer */ 391 MX6QDL_PAD_NANDF_D6__GPIO2_IO06 0x80000000 /* SD4_CD# */ 392 MX6QDL_PAD_NANDF_D7__GPIO2_IO07 0x80000000 /* SD4_WP */ 393 MX6QDL_PAD_CSI0_MCLK__CCM_CLKO1 0x80000000 /* Camera MCLK */ 394 >; 395 }; 396 397 pinctrl_i2c1: i2c1grp { 398 fsl,pins = < 399 MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 /* Q7[66] I2C_CLK */ 400 MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 /* Q7[68] I2C_DAT */ 401 >; 402 }; 403 404 pinctrl_i2c1_gpio: i2c1-gpiogrp { 405 fsl,pins = < 406 MX6QDL_PAD_EIM_D21__GPIO3_IO21 0x1b0b0 /* Q7[66] I2C_CLK */ 407 MX6QDL_PAD_EIM_D28__GPIO3_IO28 0x1b0b0 /* Q7[68] I2C_DAT */ 408 >; 409 }; 410 411 pinctrl_i2c2: i2c2grp { 412 fsl,pins = < 413 MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 /* Q7[152] SDVO_CTRL_CLK */ 414 MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 /* Q7[150] SDVO_CTRL_DAT */ 415 >; 416 }; 417 418 pinctrl_i2c2_gpio: i2c2-gpiogrp { 419 fsl,pins = < 420 MX6QDL_PAD_KEY_COL3__GPIO4_IO12 0x1b0b0 /* Q7[152] SDVO_CTRL_CLK */ 421 MX6QDL_PAD_KEY_ROW3__GPIO4_IO13 0x1b0b0 /* Q7[150] SDVO_CTRL_DAT */ 422 >; 423 }; 424 425 pinctrl_i2c3: i2c3grp { 426 fsl,pins = < 427 MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1 /* Q7[60] SMB_CLK */ 428 MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 /* Q7[62] SMB_DAT */ 429 >; 430 }; 431 432 pinctrl_i2c3_gpio: i2c3-gpiogrp { 433 fsl,pins = < 434 MX6QDL_PAD_GPIO_3__GPIO1_IO03 0x1b0b0 /* Q7[60] SMB_CLK */ 435 MX6QDL_PAD_GPIO_6__GPIO1_IO06 0x1b0b0 /* Q7[62] SMB_DAT */ 436 >; 437 }; 438 439 pinctrl_phy_reset: phy-resetgrp { 440 fsl,pins = < 441 MX6QDL_PAD_EIM_D23__GPIO3_IO23 0x1b0b0 /* RGMII Phy Reset */ 442 >; 443 }; 444 445 pinctrl_pwm4: pwm4grp { 446 fsl,pins = < 447 MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x1b0b1 /* Q7[123] LVDS_BLT_CTRL */ 448 >; 449 }; 450 451 pinctrl_q7_backlight_enable: q7-backlight-enablegrp { 452 fsl,pins = < 453 MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x1b0b0 /* Q7[112] LVDS_BLEN */ 454 >; 455 }; 456 457 pinctrl_q7_gpio0: q7-gpio0grp { 458 fsl,pins = < 459 MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x1b0b0 /* Q7[185] GPIO0 */ 460 >; 461 }; 462 463 pinctrl_q7_gpio1: q7-gpio1grp { 464 fsl,pins = < 465 MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x1b0b0 /* Q7[186] GPIO1 */ 466 >; 467 }; 468 469 pinctrl_q7_gpio2: q7-gpio2grp { 470 fsl,pins = < 471 MX6QDL_PAD_DISP0_DAT5__GPIO4_IO26 0x1b0b0 /* Q7[187] GPIO2 */ 472 >; 473 }; 474 475 pinctrl_q7_gpio3: q7-gpio3grp { 476 fsl,pins = < 477 MX6QDL_PAD_DISP0_DAT6__GPIO4_IO27 0x1b0b0 /* Q7[188] GPIO3 */ 478 >; 479 }; 480 481 pinctrl_q7_gpio4: q7-gpio4grp { 482 fsl,pins = < 483 MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x1b0b0 /* Q7[189] GPIO4 */ 484 >; 485 }; 486 487 pinctrl_q7_gpio5: q7-gpio5grp { 488 fsl,pins = < 489 MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x1b0b0 /* Q7[190] GPIO5 */ 490 >; 491 }; 492 493 pinctrl_q7_gpio6: q7-gpio6grp { 494 fsl,pins = < 495 MX6QDL_PAD_GPIO_16__GPIO7_IO11 0x1b0b0 /* Q7[191] GPIO6 */ 496 >; 497 }; 498 499 pinctrl_q7_gpio7: q7-gpio7grp { 500 fsl,pins = < 501 MX6QDL_PAD_KEY_COL4__GPIO4_IO14 0x1b0b0 /* Q7[192] GPIO7 */ 502 >; 503 }; 504 505 pinctrl_q7_hda_reset: q7-hda-resetgrp { 506 fsl,pins = < 507 MX6QDL_PAD_NANDF_ALE__GPIO6_IO08 0x1b0b0 /* Q7[61] HDA_RST_N */ 508 >; 509 }; 510 511 pinctrl_q7_lcd_power: lcd-powergrp { 512 fsl,pins = < 513 MX6QDL_PAD_GPIO_7__GPIO1_IO07 0x1b0b0 /* Q7[111] LVDS_PPEN */ 514 >; 515 }; 516 517 pinctrl_q7_sdio_power: q7-sdio-powergrp { 518 fsl,pins = < 519 MX6QDL_PAD_DISP0_DAT9__GPIO4_IO30 0x1b0b0 /* Q7[47] SDIO_PWR# */ 520 >; 521 }; 522 523 pinctrl_q7_sleep_button: q7-sleep-buttongrp { 524 fsl,pins = < 525 MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x1b0b0 /* Q7[21] SLP_BTN# */ 526 >; 527 }; 528 529 pinctrl_q7_spi_cs1: spi-cs1grp { 530 fsl,pins = < 531 MX6QDL_PAD_DISP0_DAT4__GPIO4_IO25 0x1b0b0 /* Q7[202] SPI_CS1# */ 532 >; 533 }; 534 535 /* SPI1 bus does not leave System on Module */ 536 pinctrl_spi1: spi1grp { 537 fsl,pins = < 538 MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1 539 MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1 540 MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1 541 MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x1b0b0 542 >; 543 }; 544 545 /* Debug connector on Q7 module */ 546 pinctrl_uart2: uart2grp { 547 fsl,pins = < 548 MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1 549 MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1 550 >; 551 }; 552 553 pinctrl_uart3: uart3grp { 554 fsl,pins = < 555 MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1 /* Q7[177] UART0_RX */ 556 MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1 /* Q7[171] UART0_TX */ 557 >; 558 }; 559 560 pinctrl_usbotg: usbotggrp { 561 fsl,pins = < 562 MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 /* Q7[92] USB_ID */ 563 >; 564 }; 565 566 /* µSD card slot on Q7 module */ 567 pinctrl_usdhc2: usdhc2grp { 568 fsl,pins = < 569 MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059 570 MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059 571 MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059 572 MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059 573 MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059 574 MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059 575 MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1b0b0 /* SD2_CD */ 576 >; 577 }; 578 579 /* eMMC module on Q7 module */ 580 pinctrl_usdhc3: usdhc3grp { 581 fsl,pins = < 582 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 583 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 584 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 585 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 586 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 587 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 588 MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059 589 MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059 590 MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059 591 MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059 592 >; 593 }; 594 595 pinctrl_usdhc4: usdhc4grp { 596 fsl,pins = < 597 MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059 /* Q7[45] SDIO_CMD */ 598 MX6QDL_PAD_SD4_CLK__SD4_CLK 0x17059 /* Q7[42] SDIO_CLK */ 599 MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059 /* Q7[48] SDIO_DAT1 */ 600 MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059 /* Q7[49] SDIO_DAT0 */ 601 MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059 /* Q7[50] SDIO_DAT3 */ 602 MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059 /* Q7[51] SDIO_DAT2 */ 603 >; 604 }; 605 606 pinctrl_wdog: wdoggrp { 607 fsl,pins = < 608 MX6QDL_PAD_DISP0_DAT8__WDOG1_B 0x1b0b0 /* Watchdog output signal */ 609 >; 610 }; 611};
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