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tegra124.dtsi
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linux-6.19.14/arch/arm/boot/dts/nvidia/tegra124.dtsi
1// SPDX-License-Identifier: GPL-2.0 2#include <dt-bindings/clock/tegra124-car.h> 3#include <dt-bindings/gpio/tegra-gpio.h> 4#include <dt-bindings/memory/tegra124-mc.h> 5#include <dt-bindings/pinctrl/pinctrl-tegra.h> 6#include <dt-bindings/interrupt-controller/arm-gic.h> 7#include <dt-bindings/reset/tegra124-car.h> 8#include <dt-bindings/thermal/tegra124-soctherm.h> 9#include <dt-bindings/soc/tegra-pmc.h> 10 11#include "tegra124-peripherals-opp.dtsi" 12 13/ { 14 compatible = "nvidia,tegra124"; 15 interrupt-parent = <&lic>; 16 #address-cells = <2>; 17 #size-cells = <2>; 18 19 memory@80000000 { 20 device_type = "memory"; 21 reg = <0x0 0x80000000 0x0 0x0>; 22 }; 23 24 pcie@1003000 { 25 compatible = "nvidia,tegra124-pcie"; 26 device_type = "pci"; 27 reg = <0x0 0x01003000 0x0 0x00000800>, /* PADS registers */ 28 <0x0 0x01003800 0x0 0x00000800>, /* AFI registers */ 29 <0x0 0x02000000 0x0 0x10000000>; /* configuration space */ 30 reg-names = "pads", "afi", "cs"; 31 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 32 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 33 interrupt-names = "intr", "msi"; 34 35 #interrupt-cells = <1>; 36 interrupt-map-mask = <0 0 0 0>; 37 interrupt-map = <0 0 0 0 &gic GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 38 39 bus-range = <0x00 0xff>; 40 #address-cells = <3>; 41 #size-cells = <2>; 42 43 ranges = <0x02000000 0 0x01000000 0x0 0x01000000 0 0x00001000>, /* port 0 configuration space */ 44 <0x02000000 0 0x01001000 0x0 0x01001000 0 0x00001000>, /* port 1 configuration space */ 45 <0x01000000 0 0x0 0x0 0x12000000 0 0x00010000>, /* downstream I/O (64 KiB) */ 46 <0x02000000 0 0x13000000 0x0 0x13000000 0 0x0d000000>, /* non-prefetchable memory (208 MiB) */ 47 <0x42000000 0 0x20000000 0x0 0x20000000 0 0x20000000>; /* prefetchable memory (512 MiB) */ 48 49 clocks = <&tegra_car TEGRA124_CLK_PCIE>, 50 <&tegra_car TEGRA124_CLK_AFI>, 51 <&tegra_car TEGRA124_CLK_PLL_E>, 52 <&tegra_car TEGRA124_CLK_CML0>; 53 clock-names = "pex", "afi", "pll_e", "cml"; 54 resets = <&tegra_car 70>, 55 <&tegra_car 72>, 56 <&tegra_car 74>; 57 reset-names = "pex", "afi", "pcie_x"; 58 status = "disabled"; 59 60 pci@1,0 { 61 device_type = "pci"; 62 assigned-addresses = <0x82000800 0 0x01000000 0 0x1000>; 63 reg = <0x000800 0 0 0 0>; 64 bus-range = <0x00 0xff>; 65 status = "disabled"; 66 67 #address-cells = <3>; 68 #size-cells = <2>; 69 ranges; 70 71 nvidia,num-lanes = <2>; 72 }; 73 74 pci@2,0 { 75 device_type = "pci"; 76 assigned-addresses = <0x82001000 0 0x01001000 0 0x1000>; 77 reg = <0x001000 0 0 0 0>; 78 bus-range = <0x00 0xff>; 79 status = "disabled"; 80 81 #address-cells = <3>; 82 #size-cells = <2>; 83 ranges; 84 85 nvidia,num-lanes = <1>; 86 }; 87 }; 88 89 host1x@50000000 { 90 compatible = "nvidia,tegra124-host1x"; 91 reg = <0x0 0x50000000 0x0 0x00034000>; 92 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */ 93 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* general */ 94 interrupt-names = "syncpt", "host1x"; 95 clocks = <&tegra_car TEGRA124_CLK_HOST1X>; 96 clock-names = "host1x"; 97 resets = <&tegra_car 28>, <&mc TEGRA124_MC_RESET_HC>; 98 reset-names = "host1x", "mc"; 99 iommus = <&mc TEGRA_SWGROUP_HC>; 100 101 #address-cells = <2>; 102 #size-cells = <2>; 103 104 ranges = <0 0x54000000 0 0x54000000 0 0x01000000>; 105 106 vi@54080000 { 107 compatible = "nvidia,tegra124-vi"; 108 reg = <0x0 0x54080000 0x0 0x00040000>; 109 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; 110 clocks = <&tegra_car TEGRA124_CLK_VI>; 111 resets = <&tegra_car 20>; 112 reset-names = "vi"; 113 114 iommus = <&mc TEGRA_SWGROUP_VI>; 115 116 status = "disabled"; 117 }; 118 119 isp@54600000 { 120 compatible = "nvidia,tegra124-isp"; 121 reg = <0x0 0x54600000 0x0 0x00040000>; 122 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 123 clocks = <&tegra_car TEGRA124_CLK_ISP>; 124 resets = <&tegra_car TEGRA124_CLK_ISP>; 125 reset-names = "isp"; 126 127 iommus = <&mc TEGRA_SWGROUP_ISP2>; 128 129 status = "disabled"; 130 }; 131 132 isp@54680000 { 133 compatible = "nvidia,tegra124-isp"; 134 reg = <0x0 0x54680000 0x0 0x00040000>; 135 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; 136 clocks = <&tegra_car TEGRA124_CLK_ISPB>; 137 resets = <&tegra_car TEGRA124_CLK_ISPB>; 138 reset-names = "isp"; 139 140 iommus = <&mc TEGRA_SWGROUP_ISP2B>; 141 142 status = "disabled"; 143 }; 144 145 dc@54200000 { 146 compatible = "nvidia,tegra124-dc"; 147 reg = <0x0 0x54200000 0x0 0x00040000>; 148 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 149 clocks = <&tegra_car TEGRA124_CLK_DISP1>; 150 clock-names = "dc"; 151 resets = <&tegra_car 27>; 152 reset-names = "dc"; 153 154 iommus = <&mc TEGRA_SWGROUP_DC>; 155 156 nvidia,head = <0>; 157 158 interconnects = <&mc TEGRA124_MC_DISPLAY0A &emc>, 159 <&mc TEGRA124_MC_DISPLAY0B &emc>, 160 <&mc TEGRA124_MC_DISPLAY0C &emc>, 161 <&mc TEGRA124_MC_DISPLAYHC &emc>, 162 <&mc TEGRA124_MC_DISPLAYD &emc>, 163 <&mc TEGRA124_MC_DISPLAYT &emc>; 164 interconnect-names = "wina", 165 "winb", 166 "winc", 167 "cursor", 168 "wind", 169 "wint"; 170 }; 171 172 dc@54240000 { 173 compatible = "nvidia,tegra124-dc"; 174 reg = <0x0 0x54240000 0x0 0x00040000>; 175 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 176 clocks = <&tegra_car TEGRA124_CLK_DISP2>; 177 clock-names = "dc"; 178 resets = <&tegra_car 26>; 179 reset-names = "dc"; 180 181 iommus = <&mc TEGRA_SWGROUP_DCB>; 182 183 nvidia,head = <1>; 184 185 interconnects = <&mc TEGRA124_MC_DISPLAY0AB &emc>, 186 <&mc TEGRA124_MC_DISPLAY0BB &emc>, 187 <&mc TEGRA124_MC_DISPLAY0CB &emc>, 188 <&mc TEGRA124_MC_DISPLAYHCB &emc>; 189 interconnect-names = "wina", 190 "winb", 191 "winc", 192 "cursor"; 193 }; 194 195 hdmi: hdmi@54280000 { 196 compatible = "nvidia,tegra124-hdmi"; 197 reg = <0x0 0x54280000 0x0 0x00040000>; 198 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 199 clocks = <&tegra_car TEGRA124_CLK_HDMI>, 200 <&tegra_car TEGRA124_CLK_PLL_D2_OUT0>; 201 clock-names = "hdmi", "parent"; 202 resets = <&tegra_car 51>; 203 reset-names = "hdmi"; 204 status = "disabled"; 205 }; 206 207 dsia: dsi@54300000 { 208 compatible = "nvidia,tegra124-dsi"; 209 reg = <0x0 0x54300000 0x0 0x00040000>; 210 clocks = <&tegra_car TEGRA124_CLK_DSIA>, 211 <&tegra_car TEGRA124_CLK_DSIALP>, 212 <&tegra_car TEGRA124_CLK_PLL_D_OUT0>; 213 clock-names = "dsi", "lp", "parent"; 214 resets = <&tegra_car 48>; 215 reset-names = "dsi"; 216 nvidia,mipi-calibrate = <&mipi 0x060>; /* DSIA & DSIB pads */ 217 status = "disabled"; 218 219 #address-cells = <1>; 220 #size-cells = <0>; 221 }; 222 223 vic@54340000 { 224 compatible = "nvidia,tegra124-vic"; 225 reg = <0x0 0x54340000 0x0 0x00040000>; 226 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 227 clocks = <&tegra_car TEGRA124_CLK_VIC03>; 228 clock-names = "vic"; 229 resets = <&tegra_car 178>; 230 reset-names = "vic"; 231 232 iommus = <&mc TEGRA_SWGROUP_VIC>; 233 }; 234 235 dsib: dsi@54400000 { 236 compatible = "nvidia,tegra124-dsi"; 237 reg = <0x0 0x54400000 0x0 0x00040000>; 238 clocks = <&tegra_car TEGRA124_CLK_DSIB>, 239 <&tegra_car TEGRA124_CLK_DSIBLP>, 240 <&tegra_car TEGRA124_CLK_PLL_D_OUT0>; 241 clock-names = "dsi", "lp", "parent"; 242 resets = <&tegra_car 82>; 243 reset-names = "dsi"; 244 nvidia,mipi-calibrate = <&mipi 0x180>; /* DSIC & DSID pads */ 245 status = "disabled"; 246 247 #address-cells = <1>; 248 #size-cells = <0>; 249 }; 250 251 msenc@544c0000 { 252 compatible = "nvidia,tegra124-msenc"; 253 reg = <0x0 0x544c0000 0x0 0x00040000>; 254 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>; 255 clocks = <&tegra_car TEGRA124_CLK_MSENC>; 256 resets = <&tegra_car TEGRA124_CLK_MSENC>; 257 reset-names = "mpe"; 258 259 iommus = <&mc TEGRA_SWGROUP_MSENC>; 260 261 status = "disabled"; 262 }; 263 264 tsec@54500000 { 265 compatible = "nvidia,tegra124-tsec"; 266 reg = <0x0 0x54500000 0x0 0x00040000>; 267 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; 268 clocks = <&tegra_car TEGRA124_CLK_TSEC>; 269 resets = <&tegra_car TEGRA124_CLK_TSEC>; 270 271 iommus = <&mc TEGRA_SWGROUP_TSEC>; 272 273 status = "disabled"; 274 }; 275 276 sor@54540000 { 277 compatible = "nvidia,tegra124-sor"; 278 reg = <0x0 0x54540000 0x0 0x00040000>; 279 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; 280 clocks = <&tegra_car TEGRA124_CLK_SOR0>, 281 <&tegra_car TEGRA124_CLK_SOR0_OUT>, 282 <&tegra_car TEGRA124_CLK_PLL_D_OUT0>, 283 <&tegra_car TEGRA124_CLK_PLL_DP>, 284 <&tegra_car TEGRA124_CLK_CLK_M>; 285 clock-names = "sor", "out", "parent", "dp", "safe"; 286 resets = <&tegra_car 182>; 287 reset-names = "sor"; 288 status = "disabled"; 289 }; 290 291 dpaux: dpaux@545c0000 { 292 compatible = "nvidia,tegra124-dpaux"; 293 reg = <0x0 0x545c0000 0x0 0x00040000>; 294 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>; 295 clocks = <&tegra_car TEGRA124_CLK_DPAUX>, 296 <&tegra_car TEGRA124_CLK_PLL_DP>; 297 clock-names = "dpaux", "parent"; 298 resets = <&tegra_car 181>; 299 reset-names = "dpaux"; 300 status = "disabled"; 301 302 i2c-bus { 303 #address-cells = <1>; 304 #size-cells = <0>; 305 }; 306 }; 307 }; 308 309 gic: interrupt-controller@50041000 { 310 compatible = "arm,cortex-a15-gic"; 311 #interrupt-cells = <3>; 312 interrupt-controller; 313 reg = <0x0 0x50041000 0x0 0x1000>, 314 <0x0 0x50042000 0x0 0x1000>, 315 <0x0 0x50044000 0x0 0x2000>, 316 <0x0 0x50046000 0x0 0x2000>; 317 interrupts = <GIC_PPI 9 318 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 319 interrupt-parent = <&gic>; 320 }; 321 322 gpu@57000000 { 323 compatible = "nvidia,gk20a"; 324 reg = <0x0 0x57000000 0x0 0x01000000>, 325 <0x0 0x58000000 0x0 0x01000000>; 326 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>, 327 <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>; 328 interrupt-names = "stall", "nonstall"; 329 clocks = <&tegra_car TEGRA124_CLK_GPU>, 330 <&tegra_car TEGRA124_CLK_PLL_P_OUT5>; 331 clock-names = "gpu", "pwr"; 332 resets = <&tegra_car 184>; 333 reset-names = "gpu"; 334 335 iommus = <&mc TEGRA_SWGROUP_GPU>; 336 337 status = "disabled"; 338 }; 339 340 lic: interrupt-controller@60004000 { 341 compatible = "nvidia,tegra124-ictlr", "nvidia,tegra30-ictlr"; 342 reg = <0x0 0x60004000 0x0 0x100>, 343 <0x0 0x60004100 0x0 0x100>, 344 <0x0 0x60004200 0x0 0x100>, 345 <0x0 0x60004300 0x0 0x100>, 346 <0x0 0x60004400 0x0 0x100>; 347 interrupt-controller; 348 #interrupt-cells = <3>; 349 interrupt-parent = <&gic>; 350 }; 351 352 timer@60005000 { 353 compatible = "nvidia,tegra124-timer", "nvidia,tegra30-timer"; 354 reg = <0x0 0x60005000 0x0 0x400>; 355 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 356 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 357 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, 358 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, 359 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 360 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; 361 clocks = <&tegra_car TEGRA124_CLK_TIMER>; 362 }; 363 364 tegra_car: clock@60006000 { 365 compatible = "nvidia,tegra124-car"; 366 reg = <0x0 0x60006000 0x0 0x1000>; 367 #clock-cells = <1>; 368 #reset-cells = <1>; 369 nvidia,external-memory-controller = <&emc>; 370 }; 371 372 flow-controller@60007000 { 373 compatible = "nvidia,tegra124-flowctrl"; 374 reg = <0x0 0x60007000 0x0 0x1000>; 375 }; 376 377 actmon: actmon@6000c800 { 378 compatible = "nvidia,tegra124-actmon"; 379 reg = <0x0 0x6000c800 0x0 0x400>; 380 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 381 clocks = <&tegra_car TEGRA124_CLK_ACTMON>, 382 <&tegra_car TEGRA124_CLK_EMC>; 383 clock-names = "actmon", "emc"; 384 resets = <&tegra_car 119>; 385 reset-names = "actmon"; 386 operating-points-v2 = <&emc_bw_dfs_opp_table>; 387 interconnects = <&mc TEGRA124_MC_MPCORER &emc>; 388 interconnect-names = "cpu-read"; 389 #cooling-cells = <2>; 390 }; 391 392 gpio: gpio@6000d000 { 393 compatible = "nvidia,tegra124-gpio", "nvidia,tegra30-gpio"; 394 reg = <0x0 0x6000d000 0x0 0x1000>; 395 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, 396 <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>, 397 <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>, 398 <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>, 399 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>, 400 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>, 401 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>, 402 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; 403 #gpio-cells = <2>; 404 gpio-controller; 405 #interrupt-cells = <2>; 406 interrupt-controller; 407 gpio-ranges = <&pinmux 0 0 251>; 408 }; 409 410 apbdma: dma@60020000 { 411 compatible = "nvidia,tegra124-apbdma", "nvidia,tegra148-apbdma"; 412 reg = <0x0 0x60020000 0x0 0x1400>; 413 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 414 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 415 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 416 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 417 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 418 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 419 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 420 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 421 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 422 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 423 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 424 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 425 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 426 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 427 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 428 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, 429 <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, 430 <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>, 431 <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, 432 <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 433 <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, 434 <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, 435 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, 436 <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, 437 <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 438 <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, 439 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, 440 <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>, 441 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>, 442 <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, 443 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 444 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; 445 clocks = <&tegra_car TEGRA124_CLK_APBDMA>; 446 resets = <&tegra_car 34>; 447 reset-names = "dma"; 448 #dma-cells = <1>; 449 }; 450 451 apbmisc@70000800 { 452 compatible = "nvidia,tegra124-apbmisc", "nvidia,tegra20-apbmisc"; 453 reg = <0x0 0x70000800 0x0 0x64>, /* Chip revision */ 454 <0x0 0x7000e864 0x0 0x04>; /* Strapping options */ 455 }; 456 457 pinmux: pinmux@70000868 { 458 compatible = "nvidia,tegra124-pinmux"; 459 reg = <0x0 0x70000868 0x0 0x164>, /* Pad control registers */ 460 <0x0 0x70003000 0x0 0x434>, /* Mux registers */ 461 <0x0 0x70000820 0x0 0x008>; /* MIPI pad control */ 462 }; 463 464 /* 465 * There are two serial driver i.e. 8250 based simple serial 466 * driver and APB DMA based serial driver for higher baudrate 467 * and performace. To enable the 8250 based driver, the compatible 468 * is "nvidia,tegra124-uart", "nvidia,tegra20-uart" and to enable 469 * the APB DMA based serial driver, the compatible is 470 * "nvidia,tegra124-hsuart", "nvidia,tegra30-hsuart". 471 */ 472 uarta: serial@70006000 { 473 compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart"; 474 reg = <0x0 0x70006000 0x0 0x40>; 475 reg-shift = <2>; 476 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 477 clocks = <&tegra_car TEGRA124_CLK_UARTA>; 478 resets = <&tegra_car 6>; 479 dmas = <&apbdma 8>, <&apbdma 8>; 480 dma-names = "rx", "tx"; 481 status = "disabled"; 482 }; 483 484 uartb: serial@70006040 { 485 compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart"; 486 reg = <0x0 0x70006040 0x0 0x40>; 487 reg-shift = <2>; 488 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 489 clocks = <&tegra_car TEGRA124_CLK_UARTB>; 490 resets = <&tegra_car 7>; 491 dmas = <&apbdma 9>, <&apbdma 9>; 492 dma-names = "rx", "tx"; 493 status = "disabled"; 494 }; 495 496 uartc: serial@70006200 { 497 compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart"; 498 reg = <0x0 0x70006200 0x0 0x40>; 499 reg-shift = <2>; 500 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; 501 clocks = <&tegra_car TEGRA124_CLK_UARTC>; 502 resets = <&tegra_car 55>; 503 dmas = <&apbdma 10>, <&apbdma 10>; 504 dma-names = "rx", "tx"; 505 status = "disabled"; 506 }; 507 508 uartd: serial@70006300 { 509 compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart"; 510 reg = <0x0 0x70006300 0x0 0x40>; 511 reg-shift = <2>; 512 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; 513 clocks = <&tegra_car TEGRA124_CLK_UARTD>; 514 resets = <&tegra_car 65>; 515 dmas = <&apbdma 19>, <&apbdma 19>; 516 dma-names = "rx", "tx"; 517 status = "disabled"; 518 }; 519 520 pwm: pwm@7000a000 { 521 compatible = "nvidia,tegra124-pwm", "nvidia,tegra20-pwm"; 522 reg = <0x0 0x7000a000 0x0 0x100>; 523 #pwm-cells = <2>; 524 clocks = <&tegra_car TEGRA124_CLK_PWM>; 525 resets = <&tegra_car 17>; 526 reset-names = "pwm"; 527 status = "disabled"; 528 }; 529 530 i2c@7000c000 { 531 compatible = "nvidia,tegra124-i2c"; 532 reg = <0x0 0x7000c000 0x0 0x100>; 533 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 534 #address-cells = <1>; 535 #size-cells = <0>; 536 clocks = <&tegra_car TEGRA124_CLK_I2C1>; 537 clock-names = "div-clk"; 538 resets = <&tegra_car 12>; 539 reset-names = "i2c"; 540 dmas = <&apbdma 21>, <&apbdma 21>; 541 dma-names = "rx", "tx"; 542 status = "disabled"; 543 }; 544 545 i2c@7000c400 { 546 compatible = "nvidia,tegra124-i2c"; 547 reg = <0x0 0x7000c400 0x0 0x100>; 548 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 549 #address-cells = <1>; 550 #size-cells = <0>; 551 clocks = <&tegra_car TEGRA124_CLK_I2C2>; 552 clock-names = "div-clk"; 553 resets = <&tegra_car 54>; 554 reset-names = "i2c"; 555 dmas = <&apbdma 22>, <&apbdma 22>; 556 dma-names = "rx", "tx"; 557 status = "disabled"; 558 }; 559 560 i2c@7000c500 { 561 compatible = "nvidia,tegra124-i2c"; 562 reg = <0x0 0x7000c500 0x0 0x100>; 563 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; 564 #address-cells = <1>; 565 #size-cells = <0>; 566 clocks = <&tegra_car TEGRA124_CLK_I2C3>; 567 clock-names = "div-clk"; 568 resets = <&tegra_car 67>; 569 reset-names = "i2c"; 570 dmas = <&apbdma 23>, <&apbdma 23>; 571 dma-names = "rx", "tx"; 572 status = "disabled"; 573 }; 574 575 i2c@7000c700 { 576 compatible = "nvidia,tegra124-i2c"; 577 reg = <0x0 0x7000c700 0x0 0x100>; 578 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; 579 #address-cells = <1>; 580 #size-cells = <0>; 581 clocks = <&tegra_car TEGRA124_CLK_I2C4>; 582 clock-names = "div-clk"; 583 resets = <&tegra_car 103>; 584 reset-names = "i2c"; 585 dmas = <&apbdma 26>, <&apbdma 26>; 586 dma-names = "rx", "tx"; 587 status = "disabled"; 588 }; 589 590 i2c@7000d000 { 591 compatible = "nvidia,tegra124-i2c"; 592 reg = <0x0 0x7000d000 0x0 0x100>; 593 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 594 #address-cells = <1>; 595 #size-cells = <0>; 596 clocks = <&tegra_car TEGRA124_CLK_I2C5>; 597 clock-names = "div-clk"; 598 resets = <&tegra_car 47>; 599 reset-names = "i2c"; 600 dmas = <&apbdma 24>, <&apbdma 24>; 601 dma-names = "rx", "tx"; 602 status = "disabled"; 603 }; 604 605 i2c@7000d100 { 606 compatible = "nvidia,tegra124-i2c"; 607 reg = <0x0 0x7000d100 0x0 0x100>; 608 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 609 #address-cells = <1>; 610 #size-cells = <0>; 611 clocks = <&tegra_car TEGRA124_CLK_I2C6>; 612 clock-names = "div-clk"; 613 resets = <&tegra_car 166>; 614 reset-names = "i2c"; 615 dmas = <&apbdma 30>, <&apbdma 30>; 616 dma-names = "rx", "tx"; 617 status = "disabled"; 618 }; 619 620 spi@7000d400 { 621 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi"; 622 reg = <0x0 0x7000d400 0x0 0x200>; 623 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; 624 #address-cells = <1>; 625 #size-cells = <0>; 626 clocks = <&tegra_car TEGRA124_CLK_SBC1>; 627 clock-names = "spi"; 628 resets = <&tegra_car 41>; 629 reset-names = "spi"; 630 dmas = <&apbdma 15>, <&apbdma 15>; 631 dma-names = "rx", "tx"; 632 status = "disabled"; 633 }; 634 635 spi@7000d600 { 636 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi"; 637 reg = <0x0 0x7000d600 0x0 0x200>; 638 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 639 #address-cells = <1>; 640 #size-cells = <0>; 641 clocks = <&tegra_car TEGRA124_CLK_SBC2>; 642 clock-names = "spi"; 643 resets = <&tegra_car 44>; 644 reset-names = "spi"; 645 dmas = <&apbdma 16>, <&apbdma 16>; 646 dma-names = "rx", "tx"; 647 status = "disabled"; 648 }; 649 650 spi@7000d800 { 651 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi"; 652 reg = <0x0 0x7000d800 0x0 0x200>; 653 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 654 #address-cells = <1>; 655 #size-cells = <0>; 656 clocks = <&tegra_car TEGRA124_CLK_SBC3>; 657 clock-names = "spi"; 658 resets = <&tegra_car 46>; 659 reset-names = "spi"; 660 dmas = <&apbdma 17>, <&apbdma 17>; 661 dma-names = "rx", "tx"; 662 status = "disabled"; 663 }; 664 665 spi@7000da00 { 666 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi"; 667 reg = <0x0 0x7000da00 0x0 0x200>; 668 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; 669 #address-cells = <1>; 670 #size-cells = <0>; 671 clocks = <&tegra_car TEGRA124_CLK_SBC4>; 672 clock-names = "spi"; 673 resets = <&tegra_car 68>; 674 reset-names = "spi"; 675 dmas = <&apbdma 18>, <&apbdma 18>; 676 dma-names = "rx", "tx"; 677 status = "disabled"; 678 }; 679 680 spi@7000dc00 { 681 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi"; 682 reg = <0x0 0x7000dc00 0x0 0x200>; 683 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; 684 #address-cells = <1>; 685 #size-cells = <0>; 686 clocks = <&tegra_car TEGRA124_CLK_SBC5>; 687 clock-names = "spi"; 688 resets = <&tegra_car 104>; 689 reset-names = "spi"; 690 dmas = <&apbdma 27>, <&apbdma 27>; 691 dma-names = "rx", "tx"; 692 status = "disabled"; 693 }; 694 695 spi@7000de00 { 696 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi"; 697 reg = <0x0 0x7000de00 0x0 0x200>; 698 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; 699 #address-cells = <1>; 700 #size-cells = <0>; 701 clocks = <&tegra_car TEGRA124_CLK_SBC6>; 702 clock-names = "spi"; 703 resets = <&tegra_car 105>; 704 reset-names = "spi"; 705 dmas = <&apbdma 28>, <&apbdma 28>; 706 dma-names = "rx", "tx"; 707 status = "disabled"; 708 }; 709 710 rtc@7000e000 { 711 compatible = "nvidia,tegra124-rtc", "nvidia,tegra20-rtc"; 712 reg = <0x0 0x7000e000 0x0 0x100>; 713 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 714 clocks = <&tegra_car TEGRA124_CLK_RTC>; 715 }; 716 717 tegra_pmc: pmc@7000e400 { 718 compatible = "nvidia,tegra124-pmc"; 719 reg = <0x0 0x7000e400 0x0 0x400>; 720 clocks = <&tegra_car TEGRA124_CLK_PCLK>, <&clk32k_in>; 721 clock-names = "pclk", "clk32k_in"; 722 #clock-cells = <1>; 723 }; 724 725 fuse@7000f800 { 726 compatible = "nvidia,tegra124-efuse"; 727 reg = <0x0 0x7000f800 0x0 0x400>; 728 clocks = <&tegra_car TEGRA124_CLK_FUSE>; 729 clock-names = "fuse"; 730 resets = <&tegra_car 39>; 731 reset-names = "fuse"; 732 }; 733 734 cec@70015000 { 735 compatible = "nvidia,tegra124-cec"; 736 reg = <0x0 0x70015000 0x0 0x00001000>; 737 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 738 clocks = <&tegra_car TEGRA124_CLK_CEC>; 739 clock-names = "cec"; 740 status = "disabled"; 741 hdmi-phandle = <&hdmi>; 742 }; 743 744 mc: memory-controller@70019000 { 745 compatible = "nvidia,tegra124-mc"; 746 reg = <0x0 0x70019000 0x0 0x1000>; 747 clocks = <&tegra_car TEGRA124_CLK_MC>; 748 clock-names = "mc"; 749 750 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 751 752 #iommu-cells = <1>; 753 #reset-cells = <1>; 754 #interconnect-cells = <1>; 755 }; 756 757 emc: external-memory-controller@7001b000 { 758 compatible = "nvidia,tegra124-emc"; 759 reg = <0x0 0x7001b000 0x0 0x1000>; 760 clocks = <&tegra_car TEGRA124_CLK_EMC>; 761 clock-names = "emc"; 762 763 nvidia,memory-controller = <&mc>; 764 operating-points-v2 = <&emc_icc_dvfs_opp_table>; 765 766 #interconnect-cells = <0>; 767 }; 768 769 sata@70020000 { 770 compatible = "nvidia,tegra124-ahci"; 771 reg = <0x0 0x70027000 0x0 0x2000>, /* AHCI */ 772 <0x0 0x70020000 0x0 0x7000>; /* SATA */ 773 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 774 clocks = <&tegra_car TEGRA124_CLK_SATA>, 775 <&tegra_car TEGRA124_CLK_SATA_OOB>; 776 clock-names = "sata", "sata-oob"; 777 resets = <&tegra_car 124>, 778 <&tegra_car 129>, 779 <&tegra_car 123>; 780 reset-names = "sata", "sata-cold", "sata-oob"; 781 status = "disabled"; 782 }; 783 784 hda@70030000 { 785 compatible = "nvidia,tegra124-hda", "nvidia,tegra30-hda"; 786 reg = <0x0 0x70030000 0x0 0x10000>; 787 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 788 clocks = <&tegra_car TEGRA124_CLK_HDA>, 789 <&tegra_car TEGRA124_CLK_HDA2HDMI>, 790 <&tegra_car TEGRA124_CLK_HDA2CODEC_2X>; 791 clock-names = "hda", "hda2hdmi", "hda2codec_2x"; 792 resets = <&tegra_car 125>, /* hda */ 793 <&tegra_car 128>, /* hda2hdmi */ 794 <&tegra_car 111>; /* hda2codec_2x */ 795 reset-names = "hda", "hda2hdmi", "hda2codec_2x"; 796 status = "disabled"; 797 }; 798 799 usb@70090000 { 800 compatible = "nvidia,tegra124-xusb"; 801 reg = <0x0 0x70090000 0x0 0x8000>, 802 <0x0 0x70098000 0x0 0x1000>, 803 <0x0 0x70099000 0x0 0x1000>; 804 reg-names = "hcd", "fpci", "ipfs"; 805 806 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, 807 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; 808 809 clocks = <&tegra_car TEGRA124_CLK_XUSB_HOST>, 810 <&tegra_car TEGRA124_CLK_XUSB_HOST_SRC>, 811 <&tegra_car TEGRA124_CLK_XUSB_FALCON_SRC>, 812 <&tegra_car TEGRA124_CLK_XUSB_SS>, 813 <&tegra_car TEGRA124_CLK_XUSB_SS_DIV2>, 814 <&tegra_car TEGRA124_CLK_XUSB_SS_SRC>, 815 <&tegra_car TEGRA124_CLK_XUSB_HS_SRC>, 816 <&tegra_car TEGRA124_CLK_XUSB_FS_SRC>, 817 <&tegra_car TEGRA124_CLK_PLL_U_480M>, 818 <&tegra_car TEGRA124_CLK_CLK_M>, 819 <&tegra_car TEGRA124_CLK_PLL_E>; 820 clock-names = "xusb_host", "xusb_host_src", 821 "xusb_falcon_src", "xusb_ss", 822 "xusb_ss_div2", "xusb_ss_src", 823 "xusb_hs_src", "xusb_fs_src", 824 "pll_u_480m", "clk_m", "pll_e"; 825 resets = <&tegra_car 89>, <&tegra_car 156>, 826 <&tegra_car 143>; 827 reset-names = "xusb_host", "xusb_ss", "xusb_src"; 828 829 nvidia,xusb-padctl = <&padctl>; 830 831 status = "disabled"; 832 }; 833 834 padctl: padctl@7009f000 { 835 compatible = "nvidia,tegra124-xusb-padctl"; 836 reg = <0x0 0x7009f000 0x0 0x1000>; 837 resets = <&tegra_car 142>; 838 reset-names = "padctl"; 839 840 pads { 841 usb2 { 842 status = "disabled"; 843 844 lanes { 845 usb2-0 { 846 status = "disabled"; 847 #phy-cells = <0>; 848 }; 849 850 usb2-1 { 851 status = "disabled"; 852 #phy-cells = <0>; 853 }; 854 855 usb2-2 { 856 status = "disabled"; 857 #phy-cells = <0>; 858 }; 859 }; 860 }; 861 862 ulpi { 863 status = "disabled"; 864 865 lanes { 866 ulpi-0 { 867 status = "disabled"; 868 #phy-cells = <0>; 869 }; 870 }; 871 }; 872 873 hsic { 874 status = "disabled"; 875 876 lanes { 877 hsic-0 { 878 status = "disabled"; 879 #phy-cells = <0>; 880 }; 881 882 hsic-1 { 883 status = "disabled"; 884 #phy-cells = <0>; 885 }; 886 }; 887 }; 888 889 pcie { 890 status = "disabled"; 891 892 lanes { 893 pcie-0 { 894 status = "disabled"; 895 #phy-cells = <0>; 896 }; 897 898 pcie-1 { 899 status = "disabled"; 900 #phy-cells = <0>; 901 }; 902 903 pcie-2 { 904 status = "disabled"; 905 #phy-cells = <0>; 906 }; 907 908 pcie-3 { 909 status = "disabled"; 910 #phy-cells = <0>; 911 }; 912 913 pcie-4 { 914 status = "disabled"; 915 #phy-cells = <0>; 916 }; 917 }; 918 }; 919 920 sata { 921 status = "disabled"; 922 923 lanes { 924 sata-0 { 925 status = "disabled"; 926 #phy-cells = <0>; 927 }; 928 }; 929 }; 930 }; 931 932 ports { 933 usb2-0 { 934 status = "disabled"; 935 }; 936 937 usb2-1 { 938 status = "disabled"; 939 }; 940 941 usb2-2 { 942 status = "disabled"; 943 }; 944 945 ulpi-0 { 946 status = "disabled"; 947 }; 948 949 hsic-0 { 950 status = "disabled"; 951 }; 952 953 hsic-1 { 954 status = "disabled"; 955 }; 956 957 usb3-0 { 958 status = "disabled"; 959 }; 960 961 usb3-1 { 962 status = "disabled"; 963 }; 964 }; 965 }; 966 967 mmc@700b0000 { 968 compatible = "nvidia,tegra124-sdhci"; 969 reg = <0x0 0x700b0000 0x0 0x200>; 970 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 971 clocks = <&tegra_car TEGRA124_CLK_SDMMC1>; 972 clock-names = "sdhci"; 973 resets = <&tegra_car 14>; 974 reset-names = "sdhci"; 975 status = "disabled"; 976 }; 977 978 mmc@700b0200 { 979 compatible = "nvidia,tegra124-sdhci"; 980 reg = <0x0 0x700b0200 0x0 0x200>; 981 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 982 clocks = <&tegra_car TEGRA124_CLK_SDMMC2>; 983 clock-names = "sdhci"; 984 resets = <&tegra_car 9>; 985 reset-names = "sdhci"; 986 status = "disabled"; 987 }; 988 989 mmc@700b0400 { 990 compatible = "nvidia,tegra124-sdhci"; 991 reg = <0x0 0x700b0400 0x0 0x200>; 992 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 993 clocks = <&tegra_car TEGRA124_CLK_SDMMC3>; 994 clock-names = "sdhci"; 995 resets = <&tegra_car 69>; 996 reset-names = "sdhci"; 997 status = "disabled"; 998 }; 999 1000 mmc@700b0600 { 1001 compatible = "nvidia,tegra124-sdhci"; 1002 reg = <0x0 0x700b0600 0x0 0x200>; 1003 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 1004 clocks = <&tegra_car TEGRA124_CLK_SDMMC4>; 1005 clock-names = "sdhci"; 1006 resets = <&tegra_car 15>; 1007 reset-names = "sdhci"; 1008 status = "disabled"; 1009 }; 1010 1011 soctherm: thermal-sensor@700e2000 { 1012 compatible = "nvidia,tegra124-soctherm"; 1013 reg = <0x0 0x700e2000 0x0 0x600>, /* SOC_THERM reg_base */ 1014 <0x0 0x60006000 0x0 0x400>; /* CAR reg_base */ 1015 reg-names = "soctherm-reg", "car-reg"; 1016 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>, 1017 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; 1018 interrupt-names = "thermal", "edp"; 1019 clocks = <&tegra_car TEGRA124_CLK_TSENSOR>, 1020 <&tegra_car TEGRA124_CLK_SOC_THERM>; 1021 clock-names = "tsensor", "soctherm"; 1022 resets = <&tegra_car 78>; 1023 reset-names = "soctherm"; 1024 #thermal-sensor-cells = <1>; 1025 1026 throttle-cfgs { 1027 throttle_heavy: heavy { 1028 nvidia,priority = <100>; 1029 nvidia,cpu-throt-percent = <85>; 1030 nvidia,gpu-throt-level = <TEGRA_SOCTHERM_THROT_LEVEL_HIGH>; 1031 1032 #cooling-cells = <2>; 1033 }; 1034 }; 1035 }; 1036 1037 mipi: mipi@700e3000 { 1038 compatible = "nvidia,tegra124-mipi"; 1039 reg = <0x0 0x700e3000 0x0 0x100>; 1040 clocks = <&tegra_car TEGRA124_CLK_MIPI_CAL>; 1041 clock-names = "mipi-cal"; 1042 #nvidia,mipi-calibrate-cells = <1>; 1043 }; 1044 1045 dfll: clock@70110000 { 1046 compatible = "nvidia,tegra124-dfll"; 1047 reg = <0 0x70110000 0 0x100>, /* DFLL control */ 1048 <0 0x70110000 0 0x100>, /* I2C output control */ 1049 <0 0x70110100 0 0x100>, /* Integrated I2C controller */ 1050 <0 0x70110200 0 0x100>; /* Look-up table RAM */ 1051 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 1052 clocks = <&tegra_car TEGRA124_CLK_DFLL_SOC>, 1053 <&tegra_car TEGRA124_CLK_DFLL_REF>, 1054 <&tegra_car TEGRA124_CLK_I2C5>; 1055 clock-names = "soc", "ref", "i2c"; 1056 resets = <&tegra_car TEGRA124_RST_DFLL_DVCO>; 1057 reset-names = "dvco"; 1058 #clock-cells = <0>; 1059 clock-output-names = "dfllCPU_out"; 1060 nvidia,sample-rate = <12500>; 1061 nvidia,droop-ctrl = <0x00000f00>; 1062 nvidia,force-mode = <1>; 1063 nvidia,cf = <10>; 1064 nvidia,ci = <0>; 1065 nvidia,cg = <2>; 1066 status = "disabled"; 1067 }; 1068 1069 ahub@70300000 { 1070 compatible = "nvidia,tegra124-ahub"; 1071 reg = <0x0 0x70300000 0x0 0x200>, 1072 <0x0 0x70300800 0x0 0x800>, 1073 <0x0 0x70300200 0x0 0x600>; 1074 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 1075 clocks = <&tegra_car TEGRA124_CLK_D_AUDIO>, 1076 <&tegra_car TEGRA124_CLK_APBIF>; 1077 clock-names = "d_audio", "apbif"; 1078 resets = <&tegra_car 106>, /* d_audio */ 1079 <&tegra_car 107>, /* apbif */ 1080 <&tegra_car 30>, /* i2s0 */ 1081 <&tegra_car 11>, /* i2s1 */ 1082 <&tegra_car 18>, /* i2s2 */ 1083 <&tegra_car 101>, /* i2s3 */ 1084 <&tegra_car 102>, /* i2s4 */ 1085 <&tegra_car 108>, /* dam0 */ 1086 <&tegra_car 109>, /* dam1 */ 1087 <&tegra_car 110>, /* dam2 */ 1088 <&tegra_car 10>, /* spdif */ 1089 <&tegra_car 153>, /* amx */ 1090 <&tegra_car 185>, /* amx1 */ 1091 <&tegra_car 154>, /* adx */ 1092 <&tegra_car 180>, /* adx1 */ 1093 <&tegra_car 186>, /* afc0 */ 1094 <&tegra_car 187>, /* afc1 */ 1095 <&tegra_car 188>, /* afc2 */ 1096 <&tegra_car 189>, /* afc3 */ 1097 <&tegra_car 190>, /* afc4 */ 1098 <&tegra_car 191>; /* afc5 */ 1099 reset-names = "d_audio", "apbif", "i2s0", "i2s1", "i2s2", 1100 "i2s3", "i2s4", "dam0", "dam1", "dam2", 1101 "spdif", "amx", "amx1", "adx", "adx1", 1102 "afc0", "afc1", "afc2", "afc3", "afc4", "afc5"; 1103 dmas = <&apbdma 1>, <&apbdma 1>, 1104 <&apbdma 2>, <&apbdma 2>, 1105 <&apbdma 3>, <&apbdma 3>, 1106 <&apbdma 4>, <&apbdma 4>, 1107 <&apbdma 6>, <&apbdma 6>, 1108 <&apbdma 7>, <&apbdma 7>, 1109 <&apbdma 12>, <&apbdma 12>, 1110 <&apbdma 13>, <&apbdma 13>, 1111 <&apbdma 14>, <&apbdma 14>, 1112 <&apbdma 29>, <&apbdma 29>; 1113 dma-names = "rx0", "tx0", "rx1", "tx1", "rx2", "tx2", 1114 "rx3", "tx3", "rx4", "tx4", "rx5", "tx5", 1115 "rx6", "tx6", "rx7", "tx7", "rx8", "tx8", 1116 "rx9", "tx9"; 1117 ranges; 1118 #address-cells = <2>; 1119 #size-cells = <2>; 1120 1121 tegra_i2s0: i2s@70301000 { 1122 compatible = "nvidia,tegra124-i2s"; 1123 reg = <0x0 0x70301000 0x0 0x100>; 1124 nvidia,ahub-cif-ids = <4 4>; 1125 clocks = <&tegra_car TEGRA124_CLK_I2S0>; 1126 resets = <&tegra_car 30>; 1127 reset-names = "i2s"; 1128 status = "disabled"; 1129 }; 1130 1131 tegra_i2s1: i2s@70301100 { 1132 compatible = "nvidia,tegra124-i2s"; 1133 reg = <0x0 0x70301100 0x0 0x100>; 1134 nvidia,ahub-cif-ids = <5 5>; 1135 clocks = <&tegra_car TEGRA124_CLK_I2S1>; 1136 resets = <&tegra_car 11>; 1137 reset-names = "i2s"; 1138 status = "disabled"; 1139 }; 1140 1141 tegra_i2s2: i2s@70301200 { 1142 compatible = "nvidia,tegra124-i2s"; 1143 reg = <0x0 0x70301200 0x0 0x100>; 1144 nvidia,ahub-cif-ids = <6 6>; 1145 clocks = <&tegra_car TEGRA124_CLK_I2S2>; 1146 resets = <&tegra_car 18>; 1147 reset-names = "i2s"; 1148 status = "disabled"; 1149 }; 1150 1151 tegra_i2s3: i2s@70301300 { 1152 compatible = "nvidia,tegra124-i2s"; 1153 reg = <0x0 0x70301300 0x0 0x100>; 1154 nvidia,ahub-cif-ids = <7 7>; 1155 clocks = <&tegra_car TEGRA124_CLK_I2S3>; 1156 resets = <&tegra_car 101>; 1157 reset-names = "i2s"; 1158 status = "disabled"; 1159 }; 1160 1161 tegra_i2s4: i2s@70301400 { 1162 compatible = "nvidia,tegra124-i2s"; 1163 reg = <0x0 0x70301400 0x0 0x100>; 1164 nvidia,ahub-cif-ids = <8 8>; 1165 clocks = <&tegra_car TEGRA124_CLK_I2S4>; 1166 resets = <&tegra_car 102>; 1167 reset-names = "i2s"; 1168 status = "disabled"; 1169 }; 1170 }; 1171 1172 usb@7d000000 { 1173 compatible = "nvidia,tegra124-ehci", "nvidia,tegra30-ehci"; 1174 reg = <0x0 0x7d000000 0x0 0x4000>; 1175 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 1176 phy_type = "utmi"; 1177 clocks = <&tegra_car TEGRA124_CLK_USBD>; 1178 resets = <&tegra_car 22>; 1179 reset-names = "usb"; 1180 nvidia,phy = <&phy1>; 1181 status = "disabled"; 1182 }; 1183 1184 phy1: usb-phy@7d000000 { 1185 compatible = "nvidia,tegra124-usb-phy", "nvidia,tegra30-usb-phy"; 1186 reg = <0x0 0x7d000000 0x0 0x4000>, 1187 <0x0 0x7d000000 0x0 0x4000>; 1188 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 1189 phy_type = "utmi"; 1190 clocks = <&tegra_car TEGRA124_CLK_USBD>, 1191 <&tegra_car TEGRA124_CLK_PLL_U>, 1192 <&tegra_car TEGRA124_CLK_USBD>; 1193 clock-names = "reg", "pll_u", "utmi-pads"; 1194 resets = <&tegra_car 22>, <&tegra_car 22>; 1195 reset-names = "usb", "utmi-pads"; 1196 #phy-cells = <0>; 1197 nvidia,hssync-start-delay = <0>; 1198 nvidia,idle-wait-delay = <17>; 1199 nvidia,elastic-limit = <16>; 1200 nvidia,term-range-adj = <6>; 1201 nvidia,xcvr-setup = <9>; 1202 nvidia,xcvr-lsfslew = <0>; 1203 nvidia,xcvr-lsrslew = <3>; 1204 nvidia,hssquelch-level = <2>; 1205 nvidia,hsdiscon-level = <5>; 1206 nvidia,xcvr-hsslew = <12>; 1207 nvidia,has-utmi-pad-registers; 1208 nvidia,pmc = <&tegra_pmc 0>; 1209 status = "disabled"; 1210 }; 1211 1212 usb@7d004000 { 1213 compatible = "nvidia,tegra124-ehci", "nvidia,tegra30-ehci"; 1214 reg = <0x0 0x7d004000 0x0 0x4000>; 1215 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 1216 phy_type = "utmi"; 1217 clocks = <&tegra_car TEGRA124_CLK_USB2>; 1218 resets = <&tegra_car 58>; 1219 reset-names = "usb"; 1220 nvidia,phy = <&phy2>; 1221 status = "disabled"; 1222 }; 1223 1224 phy2: usb-phy@7d004000 { 1225 compatible = "nvidia,tegra124-usb-phy", "nvidia,tegra30-usb-phy"; 1226 reg = <0x0 0x7d004000 0x0 0x4000>, 1227 <0x0 0x7d000000 0x0 0x4000>; 1228 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 1229 phy_type = "utmi"; 1230 clocks = <&tegra_car TEGRA124_CLK_USB2>, 1231 <&tegra_car TEGRA124_CLK_PLL_U>, 1232 <&tegra_car TEGRA124_CLK_USBD>; 1233 clock-names = "reg", "pll_u", "utmi-pads"; 1234 resets = <&tegra_car 58>, <&tegra_car 22>; 1235 reset-names = "usb", "utmi-pads"; 1236 #phy-cells = <0>; 1237 nvidia,hssync-start-delay = <0>; 1238 nvidia,idle-wait-delay = <17>; 1239 nvidia,elastic-limit = <16>; 1240 nvidia,term-range-adj = <6>; 1241 nvidia,xcvr-setup = <9>; 1242 nvidia,xcvr-lsfslew = <0>; 1243 nvidia,xcvr-lsrslew = <3>; 1244 nvidia,hssquelch-level = <2>; 1245 nvidia,hsdiscon-level = <5>; 1246 nvidia,xcvr-hsslew = <12>; 1247 nvidia,pmc = <&tegra_pmc 1>; 1248 status = "disabled"; 1249 }; 1250 1251 usb@7d008000 { 1252 compatible = "nvidia,tegra124-ehci", "nvidia,tegra30-ehci"; 1253 reg = <0x0 0x7d008000 0x0 0x4000>; 1254 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 1255 phy_type = "utmi"; 1256 clocks = <&tegra_car TEGRA124_CLK_USB3>; 1257 resets = <&tegra_car 59>; 1258 reset-names = "usb"; 1259 nvidia,phy = <&phy3>; 1260 status = "disabled"; 1261 }; 1262 1263 phy3: usb-phy@7d008000 { 1264 compatible = "nvidia,tegra124-usb-phy", "nvidia,tegra30-usb-phy"; 1265 reg = <0x0 0x7d008000 0x0 0x4000>, 1266 <0x0 0x7d000000 0x0 0x4000>; 1267 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 1268 phy_type = "utmi"; 1269 clocks = <&tegra_car TEGRA124_CLK_USB3>, 1270 <&tegra_car TEGRA124_CLK_PLL_U>, 1271 <&tegra_car TEGRA124_CLK_USBD>; 1272 clock-names = "reg", "pll_u", "utmi-pads"; 1273 resets = <&tegra_car 59>, <&tegra_car 22>; 1274 reset-names = "usb", "utmi-pads"; 1275 #phy-cells = <0>; 1276 nvidia,hssync-start-delay = <0>; 1277 nvidia,idle-wait-delay = <17>; 1278 nvidia,elastic-limit = <16>; 1279 nvidia,term-range-adj = <6>; 1280 nvidia,xcvr-setup = <9>; 1281 nvidia,xcvr-lsfslew = <0>; 1282 nvidia,xcvr-lsrslew = <3>; 1283 nvidia,hssquelch-level = <2>; 1284 nvidia,hsdiscon-level = <5>; 1285 nvidia,xcvr-hsslew = <12>; 1286 nvidia,pmc = <&tegra_pmc 2>; 1287 status = "disabled"; 1288 }; 1289 1290 cpus { 1291 #address-cells = <1>; 1292 #size-cells = <0>; 1293 1294 cpu@0 { 1295 device_type = "cpu"; 1296 compatible = "arm,cortex-a15"; 1297 reg = <0>; 1298 1299 clocks = <&tegra_car TEGRA124_CLK_CCLK_G>, 1300 <&tegra_car TEGRA124_CLK_CCLK_LP>, 1301 <&tegra_car TEGRA124_CLK_PLL_X>, 1302 <&tegra_car TEGRA124_CLK_PLL_P>, 1303 <&dfll>; 1304 clock-names = "cpu_g", "cpu_lp", "pll_x", "pll_p", "dfll"; 1305 /* FIXME: what's the actual transition time? */ 1306 clock-latency = <300000>; 1307 }; 1308 1309 cpu@1 { 1310 device_type = "cpu"; 1311 compatible = "arm,cortex-a15"; 1312 reg = <1>; 1313 }; 1314 1315 cpu@2 { 1316 device_type = "cpu"; 1317 compatible = "arm,cortex-a15"; 1318 reg = <2>; 1319 }; 1320 1321 cpu@3 { 1322 device_type = "cpu"; 1323 compatible = "arm,cortex-a15"; 1324 reg = <3>; 1325 }; 1326 }; 1327 1328 pmu { 1329 compatible = "arm,cortex-a15-pmu"; 1330 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, 1331 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 1332 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, 1333 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>; 1334 interrupt-affinity = <&{/cpus/cpu@0}>, 1335 <&{/cpus/cpu@1}>, 1336 <&{/cpus/cpu@2}>, 1337 <&{/cpus/cpu@3}>; 1338 }; 1339 1340 thermal-zones { 1341 cpu-thermal { 1342 polling-delay-passive = <1000>; 1343 polling-delay = <1000>; 1344 1345 thermal-sensors = 1346 <&soctherm TEGRA124_SOCTHERM_SENSOR_CPU>; 1347 1348 trips { 1349 cpu-shutdown-trip { 1350 temperature = <103000>; 1351 hysteresis = <0>; 1352 type = "critical"; 1353 }; 1354 cpu_throttle_trip: throttle-trip { 1355 temperature = <100000>; 1356 hysteresis = <1000>; 1357 type = "hot"; 1358 }; 1359 }; 1360 1361 cooling-maps { 1362 map0 { 1363 trip = <&cpu_throttle_trip>; 1364 cooling-device = <&throttle_heavy 1 1>; 1365 }; 1366 }; 1367 }; 1368 1369 mem-thermal { 1370 polling-delay-passive = <1000>; 1371 polling-delay = <1000>; 1372 1373 thermal-sensors = 1374 <&soctherm TEGRA124_SOCTHERM_SENSOR_MEM>; 1375 1376 trips { 1377 mem-shutdown-trip { 1378 temperature = <103000>; 1379 hysteresis = <0>; 1380 type = "critical"; 1381 }; 1382 mem-throttle-trip { 1383 temperature = <99000>; 1384 hysteresis = <1000>; 1385 type = "hot"; 1386 }; 1387 }; 1388 1389 cooling-maps { 1390 /* 1391 * There are currently no cooling maps, 1392 * because there are no cooling devices. 1393 */ 1394 }; 1395 }; 1396 1397 gpu-thermal { 1398 polling-delay-passive = <1000>; 1399 polling-delay = <1000>; 1400 1401 thermal-sensors = 1402 <&soctherm TEGRA124_SOCTHERM_SENSOR_GPU>; 1403 1404 trips { 1405 gpu-shutdown-trip { 1406 temperature = <101000>; 1407 hysteresis = <0>; 1408 type = "critical"; 1409 }; 1410 gpu_throttle_trip: throttle-trip { 1411 temperature = <99000>; 1412 hysteresis = <1000>; 1413 type = "hot"; 1414 }; 1415 }; 1416 1417 cooling-maps { 1418 map0 { 1419 trip = <&gpu_throttle_trip>; 1420 cooling-device = <&throttle_heavy 1 1>; 1421 }; 1422 }; 1423 }; 1424 1425 pllx-thermal { 1426 polling-delay-passive = <1000>; 1427 polling-delay = <1000>; 1428 1429 thermal-sensors = 1430 <&soctherm TEGRA124_SOCTHERM_SENSOR_PLLX>; 1431 1432 trips { 1433 pllx-shutdown-trip { 1434 temperature = <103000>; 1435 hysteresis = <0>; 1436 type = "critical"; 1437 }; 1438 pllx-throttle-trip { 1439 temperature = <99000>; 1440 hysteresis = <1000>; 1441 type = "hot"; 1442 }; 1443 }; 1444 1445 cooling-maps { 1446 /* 1447 * There are currently no cooling maps, 1448 * because there are no cooling devices. 1449 */ 1450 }; 1451 }; 1452 }; 1453 1454 timer { 1455 compatible = "arm,armv7-timer"; 1456 interrupts = <GIC_PPI 13 1457 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 1458 <GIC_PPI 14 1459 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 1460 <GIC_PPI 11 1461 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 1462 <GIC_PPI 10 1463 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 1464 interrupt-parent = <&gic>; 1465 }; 1466};
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