nuvoton-npcm750.dtsi

  1// SPDX-License-Identifier: GPL-2.0
  2// Copyright (c) 2018 Nuvoton Technology tomer.maimon@nuvoton.com
  3// Copyright 2018 Google, Inc.
  4
  5#include "nuvoton-common-npcm7xx.dtsi"
  6
  7/ {
  8	#address-cells = <1>;
  9	#size-cells = <1>;
 10	interrupt-parent = <&gic>;
 11
 12	cpus {
 13		#address-cells = <1>;
 14		#size-cells = <0>;
 15		enable-method = "nuvoton,npcm750-smp";
 16
 17		cpu@0 {
 18			device_type = "cpu";
 19			compatible = "arm,cortex-a9";
 20			clocks = <&clk NPCM7XX_CLK_CPU>;
 21			clock-names = "clk_cpu";
 22			reg = <0>;
 23			next-level-cache = <&l2>;
 24		};
 25
 26		cpu@1 {
 27			device_type = "cpu";
 28			compatible = "arm,cortex-a9";
 29			clocks = <&clk NPCM7XX_CLK_CPU>;
 30			clock-names = "clk_cpu";
 31			reg = <1>;
 32			next-level-cache = <&l2>;
 33		};
 34	};
 35
 36	soc {
 37		timer@3fe600 {
 38			compatible = "arm,cortex-a9-twd-timer";
 39			reg = <0x3fe600 0x20>;
 40			interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) |
 41						  IRQ_TYPE_LEVEL_HIGH)>;
 42			clocks = <&clk NPCM7XX_CLK_AHB>;
 43		};
 44	};
 45
 46	ahb {
 47		gmac1: ethernet@f0804000 {
 48			device_type = "network";
 49			compatible = "snps,dwmac";
 50			reg = <0xf0804000 0x2000>;
 51			interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
 52			interrupt-names = "macirq";
 53			ethernet = <1>;
 54			clocks = <&clk_rg2refck>, <&clk NPCM7XX_CLK_AHB>;
 55			clock-names = "stmmaceth", "clk_gmac";
 56			pinctrl-names = "default";
 57			pinctrl-0 = <&rg2_pins
 58					&rg2mdio_pins>;
 59			status = "disabled";
 60		};
 61
 62		udc0: usb@f0830000 {
 63			compatible = "nuvoton,npcm750-udc";
 64			reg = <0xf0830000 0x1000
 65			       0xfffd0000 0x800>;
 66			interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
 67			clocks = <&clk NPCM7XX_CLK_SU>;
 68			clock-names = "clk_usb_bridge";
 69			phys = <&udc0_phy>;
 70			phy_type = "utmi_wide";
 71			dr_mode = "peripheral";
 72			status = "disabled";
 73		};
 74
 75		udc1: usb@f0831000 {
 76			compatible = "nuvoton,npcm750-udc";
 77			reg = <0xf0831000 0x1000
 78			       0xfffd0800 0x800>;
 79			interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
 80			clocks = <&clk NPCM7XX_CLK_SU>;
 81			clock-names = "clk_usb_bridge";
 82			phys = <&udc0_phy>;
 83			phy_type = "utmi_wide";
 84			dr_mode = "peripheral";
 85			status = "disabled";
 86		};
 87
 88		udc2: usb@f0832000 {
 89			compatible = "nuvoton,npcm750-udc";
 90			reg = <0xf0832000 0x1000
 91			       0xfffd1000 0x800>;
 92			interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
 93			clocks = <&clk NPCM7XX_CLK_SU>;
 94			clock-names = "clk_usb_bridge";
 95			phys = <&udc0_phy>;
 96			phy_type = "utmi_wide";
 97			dr_mode = "peripheral";
 98			status = "disabled";
 99		};
100
101		udc3: usb@f0833000 {
102			compatible = "nuvoton,npcm750-udc";
103			reg = <0xf0833000 0x1000
104			       0xfffd1800 0x800>;
105			interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
106			clocks = <&clk NPCM7XX_CLK_SU>;
107			clock-names = "clk_usb_bridge";
108			phys = <&udc0_phy>;
109			phy_type = "utmi_wide";
110			dr_mode = "peripheral";
111			status = "disabled";
112		};
113
114		udc4: usb@f0834000 {
115			compatible = "nuvoton,npcm750-udc";
116			reg = <0xf0834000 0x1000
117			       0xfffd2000 0x800>;
118			interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
119			clocks = <&clk NPCM7XX_CLK_SU>;
120			clock-names = "clk_usb_bridge";
121			phys = <&udc0_phy>;
122			phy_type = "utmi_wide";
123			dr_mode = "peripheral";
124			status = "disabled";
125		};
126	};
127};