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nuvoton-common-npcm7xx.dtsi
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linux-6.19.14/arch/arm/boot/dts/nuvoton/nuvoton-common-npcm7xx.dtsi
1// SPDX-License-Identifier: GPL-2.0 2// Copyright (c) 2018 Nuvoton Technology tomer.maimon@nuvoton.com 3// Copyright 2018 Google, Inc. 4 5#include <dt-bindings/interrupt-controller/arm-gic.h> 6#include <dt-bindings/clock/nuvoton,npcm7xx-clock.h> 7#include <dt-bindings/reset/nuvoton,npcm7xx-reset.h> 8 9/ { 10 #address-cells = <1>; 11 #size-cells = <1>; 12 interrupt-parent = <&gic>; 13 14 /* external reference clock */ 15 clk_refclk: clk_refclk { 16 compatible = "fixed-clock"; 17 #clock-cells = <0>; 18 clock-frequency = <25000000>; 19 clock-output-names = "refclk"; 20 }; 21 22 /* external reference clock for cpu. float in normal operation */ 23 clk_sysbypck: clk_sysbypck { 24 compatible = "fixed-clock"; 25 #clock-cells = <0>; 26 clock-frequency = <800000000>; 27 clock-output-names = "sysbypck"; 28 }; 29 30 /* external reference clock for MC. float in normal operation */ 31 clk_mcbypck: clk_mcbypck { 32 compatible = "fixed-clock"; 33 #clock-cells = <0>; 34 clock-frequency = <800000000>; 35 clock-output-names = "mcbypck"; 36 }; 37 38 /* external clock signal rg1refck, supplied by the phy */ 39 clk_rg1refck: clk_rg1refck { 40 compatible = "fixed-clock"; 41 #clock-cells = <0>; 42 clock-frequency = <125000000>; 43 clock-output-names = "clk_rg1refck"; 44 }; 45 46 /* external clock signal rg2refck, supplied by the phy */ 47 clk_rg2refck: clk_rg2refck { 48 compatible = "fixed-clock"; 49 #clock-cells = <0>; 50 clock-frequency = <125000000>; 51 clock-output-names = "clk_rg2refck"; 52 }; 53 54 clk_xin: clk_xin { 55 compatible = "fixed-clock"; 56 #clock-cells = <0>; 57 clock-frequency = <50000000>; 58 clock-output-names = "clk_xin"; 59 }; 60 61 soc { 62 #address-cells = <1>; 63 #size-cells = <1>; 64 compatible = "simple-bus"; 65 interrupt-parent = <&gic>; 66 ranges = <0x0 0xf0000000 0x00900000>; 67 68 scu: scu@3fe000 { 69 compatible = "arm,cortex-a9-scu"; 70 reg = <0x3fe000 0x1000>; 71 }; 72 73 l2: cache-controller@3fc000 { 74 compatible = "arm,pl310-cache"; 75 reg = <0x3fc000 0x1000>; 76 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 77 cache-unified; 78 cache-level = <2>; 79 clocks = <&clk NPCM7XX_CLK_AXI>; 80 arm,shared-override; 81 }; 82 83 gic: interrupt-controller@3ff000 { 84 compatible = "arm,cortex-a9-gic"; 85 interrupt-controller; 86 #interrupt-cells = <3>; 87 reg = <0x3ff000 0x1000>, 88 <0x3fe100 0x100>; 89 }; 90 91 gcr: gcr@800000 { 92 compatible = "nuvoton,npcm750-gcr", "syscon", "simple-mfd"; 93 reg = <0x800000 0x1000>; 94 }; 95 96 rst: rst@801000 { 97 compatible = "nuvoton,npcm750-rst", "syscon", "simple-mfd"; 98 reg = <0x801000 0x6C>; 99 }; 100 }; 101 102 udc0_phy: usb-phy { 103 compatible = "usb-nop-xceiv"; 104 #phy-cells = <0>; 105 }; 106 107 ahb { 108 #address-cells = <1>; 109 #size-cells = <1>; 110 compatible = "simple-bus"; 111 interrupt-parent = <&gic>; 112 ranges; 113 114 rstc: rstc@f0801000 { 115 compatible = "nuvoton,npcm750-reset"; 116 reg = <0xf0801000 0x70>; 117 #reset-cells = <2>; 118 nuvoton,sysgcr = <&gcr>; 119 }; 120 121 clk: clock-controller@f0801000 { 122 compatible = "nuvoton,npcm750-clk", "syscon"; 123 #clock-cells = <1>; 124 clock-controller; 125 reg = <0xf0801000 0x1000>; 126 clock-names = "refclk", "sysbypck", "mcbypck"; 127 clocks = <&clk_refclk>, <&clk_sysbypck>, <&clk_mcbypck>; 128 }; 129 130 mc: memory-controller@f0824000 { 131 compatible = "nuvoton,npcm750-memory-controller"; 132 reg = <0xf0824000 0x1000>; 133 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 134 status = "disabled"; 135 }; 136 137 gmac0: ethernet@f0802000 { 138 device_type = "network"; 139 compatible = "snps,dwmac"; 140 reg = <0xf0802000 0x2000>; 141 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 142 interrupt-names = "macirq"; 143 ethernet = <0>; 144 clocks = <&clk_rg1refck>, <&clk NPCM7XX_CLK_AHB>; 145 clock-names = "stmmaceth", "clk_gmac"; 146 pinctrl-names = "default"; 147 pinctrl-0 = <&rg1_pins 148 &rg1mdio_pins>; 149 status = "disabled"; 150 }; 151 152 sdmmc: mmc@f0842000 { 153 compatible = "nuvoton,npcm750-sdhci"; 154 status = "disabled"; 155 reg = <0xf0842000 0x200>; 156 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 157 clocks = <&clk NPCM7XX_CLK_AHB>; 158 clock-names = "clk_mmc"; 159 pinctrl-names = "default"; 160 pinctrl-0 = <&mmc8_pins 161 &mmc_pins>; 162 }; 163 164 sdhci: mmc@f0840000 { 165 compatible = "nuvoton,npcm750-sdhci"; 166 status = "disabled"; 167 reg = <0xf0840000 0x200>; 168 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 169 clocks = <&clk NPCM7XX_CLK_AHB>; 170 clock-names = "clk_sdhc"; 171 pinctrl-names = "default"; 172 pinctrl-0 = <&sd1_pins>; 173 }; 174 175 ehci1: usb@f0806000 { 176 compatible = "nuvoton,npcm750-ehci"; 177 reg = <0xf0806000 0x1000>; 178 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; 179 status = "disabled"; 180 }; 181 182 ohci1: usb@f0807000 { 183 compatible = "generic-ohci"; 184 reg = <0xf0807000 0x1000>; 185 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 186 status = "disabled"; 187 }; 188 189 fiu0: spi@fb000000 { 190 compatible = "nuvoton,npcm750-fiu"; 191 #address-cells = <1>; 192 #size-cells = <0>; 193 reg = <0xfb000000 0x1000>; 194 reg-names = "control", "memory"; 195 clocks = <&clk NPCM7XX_CLK_SPI0>; 196 clock-names = "clk_spi0"; 197 status = "disabled"; 198 }; 199 200 fiu3: spi@c0000000 { 201 compatible = "nuvoton,npcm750-fiu"; 202 #address-cells = <1>; 203 #size-cells = <0>; 204 reg = <0xc0000000 0x1000>; 205 reg-names = "control", "memory"; 206 clocks = <&clk NPCM7XX_CLK_SPI3>; 207 clock-names = "clk_spi3"; 208 pinctrl-names = "default"; 209 pinctrl-0 = <&spi3_pins>; 210 status = "disabled"; 211 }; 212 213 fiux: spi@fb001000 { 214 compatible = "nuvoton,npcm750-fiu"; 215 #address-cells = <1>; 216 #size-cells = <0>; 217 reg = <0xfb001000 0x1000>; 218 reg-names = "control", "memory"; 219 clocks = <&clk NPCM7XX_CLK_SPIX>; 220 clock-names = "clk_spix"; 221 status = "disabled"; 222 }; 223 224 udc5: usb@f0835000 { 225 compatible = "nuvoton,npcm750-udc"; 226 reg = <0xf0835000 0x1000 227 0xfffd2800 0x800>; 228 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; 229 clocks = <&clk NPCM7XX_CLK_SU>; 230 clock-names = "clk_usb_bridge"; 231 phys = <&udc0_phy>; 232 phy_type = "utmi_wide"; 233 dr_mode = "peripheral"; 234 status = "disabled"; 235 }; 236 237 udc6: usb@f0836000 { 238 compatible = "nuvoton,npcm750-udc"; 239 reg = <0xf0836000 0x1000 240 0xfffd3000 0x800>; 241 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; 242 clocks = <&clk NPCM7XX_CLK_SU>; 243 clock-names = "clk_usb_bridge"; 244 phys = <&udc0_phy>; 245 phy_type = "utmi_wide"; 246 dr_mode = "peripheral"; 247 status = "disabled"; 248 }; 249 250 udc7: usb@f0837000 { 251 compatible = "nuvoton,npcm750-udc"; 252 reg = <0xf0837000 0x1000 253 0xfffd3800 0x800>; 254 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>; 255 clocks = <&clk NPCM7XX_CLK_SU>; 256 clock-names = "clk_usb_bridge"; 257 phys = <&udc0_phy>; 258 phy_type = "utmi_wide"; 259 dr_mode = "peripheral"; 260 status = "disabled"; 261 }; 262 263 udc8: usb@f0838000 { 264 compatible = "nuvoton,npcm750-udc"; 265 reg = <0xf0838000 0x1000 266 0xfffd4000 0x800>; 267 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; 268 clocks = <&clk NPCM7XX_CLK_SU>; 269 clock-names = "clk_usb_bridge"; 270 phys = <&udc0_phy>; 271 phy_type = "utmi_wide"; 272 dr_mode = "peripheral"; 273 status = "disabled"; 274 }; 275 276 udc9: usb@f0839000 { 277 compatible = "nuvoton,npcm750-udc"; 278 reg = <0xf0839000 0x1000 279 0xfffd4800 0x800>; 280 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; 281 clocks = <&clk NPCM7XX_CLK_SU>; 282 clock-names = "clk_usb_bridge"; 283 nuvoton,sysgcr = <&gcr>; 284 phys = <&udc0_phy>; 285 phy_type = "utmi_wide"; 286 dr_mode = "peripheral"; 287 status = "disabled"; 288 }; 289 290 apb { 291 #address-cells = <1>; 292 #size-cells = <1>; 293 compatible = "simple-bus"; 294 interrupt-parent = <&gic>; 295 ranges = <0x0 0xf0000000 0x00300000>; 296 297 lpc_kcs: lpc_kcs@7000 { 298 compatible = "nuvoton,npcm750-lpc-kcs", "simple-mfd", "syscon"; 299 reg = <0x7000 0x40>; 300 reg-io-width = <1>; 301 302 #address-cells = <1>; 303 #size-cells = <1>; 304 ranges = <0x0 0x7000 0x40>; 305 306 kcs1: kcs1@0 { 307 compatible = "nuvoton,npcm750-kcs-bmc"; 308 reg = <0x0 0x40>; 309 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 310 kcs_chan = <1>; 311 status = "disabled"; 312 }; 313 314 kcs2: kcs2@0 { 315 compatible = "nuvoton,npcm750-kcs-bmc"; 316 reg = <0x0 0x40>; 317 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 318 kcs_chan = <2>; 319 status = "disabled"; 320 }; 321 322 kcs3: kcs3@0 { 323 compatible = "nuvoton,npcm750-kcs-bmc"; 324 reg = <0x0 0x40>; 325 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 326 kcs_chan = <3>; 327 status = "disabled"; 328 }; 329 }; 330 331 peci: peci-controller@f0100000 { 332 compatible = "nuvoton,npcm750-peci"; 333 reg = <0xf0100000 0x200>; 334 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 335 clocks = <&clk NPCM7XX_CLK_APB3>; 336 cmd-timeout-ms = <1000>; 337 status = "disabled"; 338 }; 339 340 spi0: spi@200000 { 341 compatible = "nuvoton,npcm750-pspi"; 342 reg = <0x200000 0x1000>; 343 pinctrl-names = "default"; 344 pinctrl-0 = <&pspi1_pins>; 345 #address-cells = <1>; 346 #size-cells = <0>; 347 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 348 clocks = <&clk NPCM7XX_CLK_APB5>; 349 clock-names = "clk_apb5"; 350 resets = <&rstc NPCM7XX_RESET_IPSRST2 NPCM7XX_RESET_PSPI1>; 351 status = "disabled"; 352 }; 353 354 spi1: spi@201000 { 355 compatible = "nuvoton,npcm750-pspi"; 356 reg = <0x201000 0x1000>; 357 pinctrl-names = "default"; 358 pinctrl-0 = <&pspi2_pins>; 359 #address-cells = <1>; 360 #size-cells = <0>; 361 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 362 clocks = <&clk NPCM7XX_CLK_APB5>; 363 clock-names = "clk_apb5"; 364 resets = <&rstc NPCM7XX_RESET_IPSRST2 NPCM7XX_RESET_PSPI2>; 365 status = "disabled"; 366 }; 367 368 timer0: timer@8000 { 369 compatible = "nuvoton,npcm750-timer"; 370 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 371 reg = <0x8000 0x1C>; 372 clocks = <&clk NPCM7XX_CLK_TIMER>; 373 }; 374 375 watchdog0: watchdog@801C { 376 compatible = "nuvoton,npcm750-wdt"; 377 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; 378 reg = <0x801C 0x4>; 379 status = "disabled"; 380 clocks = <&clk NPCM7XX_CLK_TIMER>; 381 }; 382 383 watchdog1: watchdog@901C { 384 compatible = "nuvoton,npcm750-wdt"; 385 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; 386 reg = <0x901C 0x4>; 387 status = "disabled"; 388 clocks = <&clk NPCM7XX_CLK_TIMER>; 389 }; 390 391 watchdog2: watchdog@a01C { 392 compatible = "nuvoton,npcm750-wdt"; 393 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; 394 reg = <0xa01C 0x4>; 395 status = "disabled"; 396 clocks = <&clk NPCM7XX_CLK_TIMER>; 397 }; 398 399 serial0: serial@1000 { 400 compatible = "nuvoton,npcm750-uart"; 401 reg = <0x1000 0x1000>; 402 clocks = <&clk NPCM7XX_CLK_UART>; 403 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 404 reg-shift = <2>; 405 status = "disabled"; 406 }; 407 408 serial1: serial@2000 { 409 compatible = "nuvoton,npcm750-uart"; 410 reg = <0x2000 0x1000>; 411 clocks = <&clk NPCM7XX_CLK_UART>; 412 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 413 reg-shift = <2>; 414 status = "disabled"; 415 }; 416 417 serial2: serial@3000 { 418 compatible = "nuvoton,npcm750-uart"; 419 reg = <0x3000 0x1000>; 420 clocks = <&clk NPCM7XX_CLK_UART>; 421 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 422 reg-shift = <2>; 423 status = "disabled"; 424 }; 425 426 serial3: serial@4000 { 427 compatible = "nuvoton,npcm750-uart"; 428 reg = <0x4000 0x1000>; 429 clocks = <&clk NPCM7XX_CLK_UART>; 430 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 431 reg-shift = <2>; 432 status = "disabled"; 433 }; 434 435 rng: rng@b000 { 436 compatible = "nuvoton,npcm750-rng"; 437 reg = <0xb000 0x8>; 438 status = "disabled"; 439 }; 440 441 adc: adc@c000 { 442 compatible = "nuvoton,npcm750-adc"; 443 reg = <0xc000 0x8>; 444 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; 445 clocks = <&clk NPCM7XX_CLK_ADC>; 446 resets = <&rstc NPCM7XX_RESET_IPSRST1 NPCM7XX_RESET_ADC>; 447 status = "disabled"; 448 }; 449 450 pwm_fan: pwm-fan-controller@103000 { 451 #address-cells = <1>; 452 #size-cells = <0>; 453 compatible = "nuvoton,npcm750-pwm-fan"; 454 reg = <0x103000 0x2000>, <0x180000 0x8000>; 455 reg-names = "pwm", "fan"; 456 clocks = <&clk NPCM7XX_CLK_APB3>, 457 <&clk NPCM7XX_CLK_APB4>; 458 clock-names = "pwm","fan"; 459 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, 460 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 461 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 462 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 463 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 464 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 465 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 466 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 467 pinctrl-names = "default"; 468 pinctrl-0 = <&pwm0_pins &pwm1_pins 469 &pwm2_pins &pwm3_pins 470 &pwm4_pins &pwm5_pins 471 &pwm6_pins &pwm7_pins 472 &fanin0_pins &fanin1_pins 473 &fanin2_pins &fanin3_pins 474 &fanin4_pins &fanin5_pins 475 &fanin6_pins &fanin7_pins 476 &fanin8_pins &fanin9_pins 477 &fanin10_pins &fanin11_pins 478 &fanin12_pins &fanin13_pins 479 &fanin14_pins &fanin15_pins>; 480 status = "disabled"; 481 }; 482 483 i2c0: i2c@80000 { 484 reg = <0x80000 0x1000>; 485 compatible = "nuvoton,npcm750-i2c"; 486 #address-cells = <1>; 487 #size-cells = <0>; 488 clocks = <&clk NPCM7XX_CLK_APB2>; 489 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 490 pinctrl-names = "default"; 491 pinctrl-0 = <&smb0_pins>; 492 status = "disabled"; 493 }; 494 495 i2c1: i2c@81000 { 496 reg = <0x81000 0x1000>; 497 compatible = "nuvoton,npcm750-i2c"; 498 #address-cells = <1>; 499 #size-cells = <0>; 500 clocks = <&clk NPCM7XX_CLK_APB2>; 501 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 502 pinctrl-names = "default"; 503 pinctrl-0 = <&smb1_pins>; 504 status = "disabled"; 505 }; 506 507 i2c2: i2c@82000 { 508 reg = <0x82000 0x1000>; 509 compatible = "nuvoton,npcm750-i2c"; 510 #address-cells = <1>; 511 #size-cells = <0>; 512 clocks = <&clk NPCM7XX_CLK_APB2>; 513 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>; 514 pinctrl-names = "default"; 515 pinctrl-0 = <&smb2_pins>; 516 status = "disabled"; 517 }; 518 519 i2c3: i2c@83000 { 520 reg = <0x83000 0x1000>; 521 compatible = "nuvoton,npcm750-i2c"; 522 #address-cells = <1>; 523 #size-cells = <0>; 524 clocks = <&clk NPCM7XX_CLK_APB2>; 525 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; 526 pinctrl-names = "default"; 527 pinctrl-0 = <&smb3_pins>; 528 status = "disabled"; 529 }; 530 531 i2c4: i2c@84000 { 532 reg = <0x84000 0x1000>; 533 compatible = "nuvoton,npcm750-i2c"; 534 #address-cells = <1>; 535 #size-cells = <0>; 536 clocks = <&clk NPCM7XX_CLK_APB2>; 537 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>; 538 pinctrl-names = "default"; 539 pinctrl-0 = <&smb4_pins>; 540 status = "disabled"; 541 }; 542 543 i2c5: i2c@85000 { 544 reg = <0x85000 0x1000>; 545 compatible = "nuvoton,npcm750-i2c"; 546 #address-cells = <1>; 547 #size-cells = <0>; 548 clocks = <&clk NPCM7XX_CLK_APB2>; 549 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; 550 pinctrl-names = "default"; 551 pinctrl-0 = <&smb5_pins>; 552 status = "disabled"; 553 }; 554 555 i2c6: i2c@86000 { 556 reg = <0x86000 0x1000>; 557 compatible = "nuvoton,npcm750-i2c"; 558 #address-cells = <1>; 559 #size-cells = <0>; 560 clocks = <&clk NPCM7XX_CLK_APB2>; 561 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; 562 pinctrl-names = "default"; 563 pinctrl-0 = <&smb6_pins>; 564 status = "disabled"; 565 }; 566 567 i2c7: i2c@87000 { 568 reg = <0x87000 0x1000>; 569 compatible = "nuvoton,npcm750-i2c"; 570 #address-cells = <1>; 571 #size-cells = <0>; 572 clocks = <&clk NPCM7XX_CLK_APB2>; 573 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 574 pinctrl-names = "default"; 575 pinctrl-0 = <&smb7_pins>; 576 status = "disabled"; 577 }; 578 579 i2c8: i2c@88000 { 580 reg = <0x88000 0x1000>; 581 compatible = "nuvoton,npcm750-i2c"; 582 #address-cells = <1>; 583 #size-cells = <0>; 584 clocks = <&clk NPCM7XX_CLK_APB2>; 585 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 586 pinctrl-names = "default"; 587 pinctrl-0 = <&smb8_pins>; 588 status = "disabled"; 589 }; 590 591 i2c9: i2c@89000 { 592 reg = <0x89000 0x1000>; 593 compatible = "nuvoton,npcm750-i2c"; 594 #address-cells = <1>; 595 #size-cells = <0>; 596 clocks = <&clk NPCM7XX_CLK_APB2>; 597 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 598 pinctrl-names = "default"; 599 pinctrl-0 = <&smb9_pins>; 600 status = "disabled"; 601 }; 602 603 i2c10: i2c@8a000 { 604 reg = <0x8a000 0x1000>; 605 compatible = "nuvoton,npcm750-i2c"; 606 #address-cells = <1>; 607 #size-cells = <0>; 608 clocks = <&clk NPCM7XX_CLK_APB2>; 609 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 610 pinctrl-names = "default"; 611 pinctrl-0 = <&smb10_pins>; 612 status = "disabled"; 613 }; 614 615 i2c11: i2c@8b000 { 616 reg = <0x8b000 0x1000>; 617 compatible = "nuvoton,npcm750-i2c"; 618 #address-cells = <1>; 619 #size-cells = <0>; 620 clocks = <&clk NPCM7XX_CLK_APB2>; 621 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 622 pinctrl-names = "default"; 623 pinctrl-0 = <&smb11_pins>; 624 status = "disabled"; 625 }; 626 627 i2c12: i2c@8c000 { 628 reg = <0x8c000 0x1000>; 629 compatible = "nuvoton,npcm750-i2c"; 630 #address-cells = <1>; 631 #size-cells = <0>; 632 clocks = <&clk NPCM7XX_CLK_APB2>; 633 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; 634 pinctrl-names = "default"; 635 pinctrl-0 = <&smb12_pins>; 636 status = "disabled"; 637 }; 638 639 i2c13: i2c@8d000 { 640 reg = <0x8d000 0x1000>; 641 compatible = "nuvoton,npcm750-i2c"; 642 #address-cells = <1>; 643 #size-cells = <0>; 644 clocks = <&clk NPCM7XX_CLK_APB2>; 645 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 646 pinctrl-names = "default"; 647 pinctrl-0 = <&smb13_pins>; 648 status = "disabled"; 649 }; 650 651 i2c14: i2c@8e000 { 652 reg = <0x8e000 0x1000>; 653 compatible = "nuvoton,npcm750-i2c"; 654 #address-cells = <1>; 655 #size-cells = <0>; 656 clocks = <&clk NPCM7XX_CLK_APB2>; 657 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; 658 pinctrl-names = "default"; 659 pinctrl-0 = <&smb14_pins>; 660 status = "disabled"; 661 }; 662 663 i2c15: i2c@8f000 { 664 reg = <0x8f000 0x1000>; 665 compatible = "nuvoton,npcm750-i2c"; 666 #address-cells = <1>; 667 #size-cells = <0>; 668 clocks = <&clk NPCM7XX_CLK_APB2>; 669 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; 670 pinctrl-names = "default"; 671 pinctrl-0 = <&smb15_pins>; 672 status = "disabled"; 673 }; 674 }; 675 }; 676 677 pinctrl: pinctrl@f0800000 { 678 #address-cells = <1>; 679 #size-cells = <1>; 680 compatible = "nuvoton,npcm750-pinctrl", "syscon", "simple-mfd"; 681 ranges = <0 0xf0010000 0x8000>; 682 gpio0: gpio@f0010000 { 683 gpio-controller; 684 #gpio-cells = <2>; 685 reg = <0x0 0x80>; 686 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 687 gpio-ranges = <&pinctrl 0 0 32>; 688 }; 689 gpio1: gpio@f0011000 { 690 gpio-controller; 691 #gpio-cells = <2>; 692 reg = <0x1000 0x80>; 693 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 694 gpio-ranges = <&pinctrl 0 32 32>; 695 }; 696 gpio2: gpio@f0012000 { 697 gpio-controller; 698 #gpio-cells = <2>; 699 reg = <0x2000 0x80>; 700 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 701 gpio-ranges = <&pinctrl 0 64 32>; 702 }; 703 gpio3: gpio@f0013000 { 704 gpio-controller; 705 #gpio-cells = <2>; 706 reg = <0x3000 0x80>; 707 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; 708 gpio-ranges = <&pinctrl 0 96 32>; 709 }; 710 gpio4: gpio@f0014000 { 711 gpio-controller; 712 #gpio-cells = <2>; 713 reg = <0x4000 0x80>; 714 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; 715 gpio-ranges = <&pinctrl 0 128 32>; 716 }; 717 gpio5: gpio@f0015000 { 718 gpio-controller; 719 #gpio-cells = <2>; 720 reg = <0x5000 0x80>; 721 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; 722 gpio-ranges = <&pinctrl 0 160 32>; 723 }; 724 gpio6: gpio@f0016000 { 725 gpio-controller; 726 #gpio-cells = <2>; 727 reg = <0x6000 0x80>; 728 interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; 729 gpio-ranges = <&pinctrl 0 192 32>; 730 }; 731 gpio7: gpio@f0017000 { 732 gpio-controller; 733 #gpio-cells = <2>; 734 reg = <0x7000 0x80>; 735 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; 736 gpio-ranges = <&pinctrl 0 224 32>; 737 }; 738 739 iox1_pins: iox1-pins { 740 groups = "iox1"; 741 function = "iox1"; 742 }; 743 iox2_pins: iox2-pins { 744 groups = "iox2"; 745 function = "iox2"; 746 }; 747 smb1d_pins: smb1d-pins { 748 groups = "smb1d"; 749 function = "smb1d"; 750 }; 751 smb2d_pins: smb2d-pins { 752 groups = "smb2d"; 753 function = "smb2d"; 754 }; 755 lkgpo1_pins: lkgpo1-pins { 756 groups = "lkgpo1"; 757 function = "lkgpo1"; 758 }; 759 lkgpo2_pins: lkgpo2-pins { 760 groups = "lkgpo2"; 761 function = "lkgpo2"; 762 }; 763 ioxh_pins: ioxh-pins { 764 groups = "ioxh"; 765 function = "ioxh"; 766 }; 767 gspi_pins: gspi-pins { 768 groups = "gspi"; 769 function = "gspi"; 770 }; 771 smb5b_pins: smb5b-pins { 772 groups = "smb5b"; 773 function = "smb5b"; 774 }; 775 smb5c_pins: smb5c-pins { 776 groups = "smb5c"; 777 function = "smb5c"; 778 }; 779 lkgpo0_pins: lkgpo0-pins { 780 groups = "lkgpo0"; 781 function = "lkgpo0"; 782 }; 783 pspi2_pins: pspi2-pins { 784 groups = "pspi2"; 785 function = "pspi2"; 786 }; 787 smb4den_pins: smb4den-pins { 788 groups = "smb4den"; 789 function = "smb4den"; 790 }; 791 smb4b_pins: smb4b-pins { 792 groups = "smb4b"; 793 function = "smb4b"; 794 }; 795 smb4c_pins: smb4c-pins { 796 groups = "smb4c"; 797 function = "smb4c"; 798 }; 799 smb15_pins: smb15-pins { 800 groups = "smb15"; 801 function = "smb15"; 802 }; 803 smb4d_pins: smb4d-pins { 804 groups = "smb4d"; 805 function = "smb4d"; 806 }; 807 smb14_pins: smb14-pins { 808 groups = "smb14"; 809 function = "smb14"; 810 }; 811 smb5_pins: smb5-pins { 812 groups = "smb5"; 813 function = "smb5"; 814 }; 815 smb4_pins: smb4-pins { 816 groups = "smb4"; 817 function = "smb4"; 818 }; 819 smb3_pins: smb3-pins { 820 groups = "smb3"; 821 function = "smb3"; 822 }; 823 spi0cs1_pins: spi0cs1-pins { 824 groups = "spi0cs1"; 825 function = "spi0cs1"; 826 }; 827 spi0cs2_pins: spi0cs2-pins { 828 groups = "spi0cs2"; 829 function = "spi0cs2"; 830 }; 831 spi0cs3_pins: spi0cs3-pins { 832 groups = "spi0cs3"; 833 function = "spi0cs3"; 834 }; 835 smb3c_pins: smb3c-pins { 836 groups = "smb3c"; 837 function = "smb3c"; 838 }; 839 smb3b_pins: smb3b-pins { 840 groups = "smb3b"; 841 function = "smb3b"; 842 }; 843 bmcuart0a_pins: bmcuart0a-pins { 844 groups = "bmcuart0a"; 845 function = "bmcuart0a"; 846 }; 847 uart1_pins: uart1-pins { 848 groups = "uart1"; 849 function = "uart1"; 850 }; 851 jtag2_pins: jtag2-pins { 852 groups = "jtag2"; 853 function = "jtag2"; 854 }; 855 bmcuart1_pins: bmcuart1-pins { 856 groups = "bmcuart1"; 857 function = "bmcuart1"; 858 }; 859 uart2_pins: uart2-pins { 860 groups = "uart2"; 861 function = "uart2"; 862 }; 863 bmcuart0b_pins: bmcuart0b-pins { 864 groups = "bmcuart0b"; 865 function = "bmcuart0b"; 866 }; 867 r1err_pins: r1err-pins { 868 groups = "r1err"; 869 function = "r1err"; 870 }; 871 r1md_pins: r1md-pins { 872 groups = "r1md"; 873 function = "r1md"; 874 }; 875 smb3d_pins: smb3d-pins { 876 groups = "smb3d"; 877 function = "smb3d"; 878 }; 879 fanin0_pins: fanin0-pins { 880 groups = "fanin0"; 881 function = "fanin0"; 882 }; 883 fanin1_pins: fanin1-pins { 884 groups = "fanin1"; 885 function = "fanin1"; 886 }; 887 fanin2_pins: fanin2-pins { 888 groups = "fanin2"; 889 function = "fanin2"; 890 }; 891 fanin3_pins: fanin3-pins { 892 groups = "fanin3"; 893 function = "fanin3"; 894 }; 895 fanin4_pins: fanin4-pins { 896 groups = "fanin4"; 897 function = "fanin4"; 898 }; 899 fanin5_pins: fanin5-pins { 900 groups = "fanin5"; 901 function = "fanin5"; 902 }; 903 fanin6_pins: fanin6-pins { 904 groups = "fanin6"; 905 function = "fanin6"; 906 }; 907 fanin7_pins: fanin7-pins { 908 groups = "fanin7"; 909 function = "fanin7"; 910 }; 911 fanin8_pins: fanin8-pins { 912 groups = "fanin8"; 913 function = "fanin8"; 914 }; 915 fanin9_pins: fanin9-pins { 916 groups = "fanin9"; 917 function = "fanin9"; 918 }; 919 fanin10_pins: fanin10-pins { 920 groups = "fanin10"; 921 function = "fanin10"; 922 }; 923 fanin11_pins: fanin11-pins { 924 groups = "fanin11"; 925 function = "fanin11"; 926 }; 927 fanin12_pins: fanin12-pins { 928 groups = "fanin12"; 929 function = "fanin12"; 930 }; 931 fanin13_pins: fanin13-pins { 932 groups = "fanin13"; 933 function = "fanin13"; 934 }; 935 fanin14_pins: fanin14-pins { 936 groups = "fanin14"; 937 function = "fanin14"; 938 }; 939 fanin15_pins: fanin15-pins { 940 groups = "fanin15"; 941 function = "fanin15"; 942 }; 943 pwm0_pins: pwm0-pins { 944 groups = "pwm0"; 945 function = "pwm0"; 946 }; 947 pwm1_pins: pwm1-pins { 948 groups = "pwm1"; 949 function = "pwm1"; 950 }; 951 pwm2_pins: pwm2-pins { 952 groups = "pwm2"; 953 function = "pwm2"; 954 }; 955 pwm3_pins: pwm3-pins { 956 groups = "pwm3"; 957 function = "pwm3"; 958 }; 959 r2_pins: r2-pins { 960 groups = "r2"; 961 function = "r2"; 962 }; 963 r2err_pins: r2err-pins { 964 groups = "r2err"; 965 function = "r2err"; 966 }; 967 r2md_pins: r2md-pins { 968 groups = "r2md"; 969 function = "r2md"; 970 }; 971 ga20kbc_pins: ga20kbc-pins { 972 groups = "ga20kbc"; 973 function = "ga20kbc"; 974 }; 975 smb5d_pins: smb5d-pins { 976 groups = "smb5d"; 977 function = "smb5d"; 978 }; 979 lpc_pins: lpc-pins { 980 groups = "lpc"; 981 function = "lpc"; 982 }; 983 espi_pins: espi-pins { 984 groups = "espi"; 985 function = "espi"; 986 }; 987 rg1_pins: rg1-pins { 988 groups = "rg1"; 989 function = "rg1"; 990 }; 991 rg1mdio_pins: rg1mdio-pins { 992 groups = "rg1mdio"; 993 function = "rg1mdio"; 994 }; 995 rg2_pins: rg2-pins { 996 groups = "rg2"; 997 function = "rg2"; 998 }; 999 ddr_pins: ddr-pins { 1000 groups = "ddr"; 1001 function = "ddr"; 1002 }; 1003 smb0_pins: smb0-pins { 1004 groups = "smb0"; 1005 function = "smb0"; 1006 }; 1007 smb1_pins: smb1-pins { 1008 groups = "smb1"; 1009 function = "smb1"; 1010 }; 1011 smb2_pins: smb2-pins { 1012 groups = "smb2"; 1013 function = "smb2"; 1014 }; 1015 smb2c_pins: smb2c-pins { 1016 groups = "smb2c"; 1017 function = "smb2c"; 1018 }; 1019 smb2b_pins: smb2b-pins { 1020 groups = "smb2b"; 1021 function = "smb2b"; 1022 }; 1023 smb1c_pins: smb1c-pins { 1024 groups = "smb1c"; 1025 function = "smb1c"; 1026 }; 1027 smb1b_pins: smb1b-pins { 1028 groups = "smb1b"; 1029 function = "smb1b"; 1030 }; 1031 smb8_pins: smb8-pins { 1032 groups = "smb8"; 1033 function = "smb8"; 1034 }; 1035 smb9_pins: smb9-pins { 1036 groups = "smb9"; 1037 function = "smb9"; 1038 }; 1039 smb10_pins: smb10-pins { 1040 groups = "smb10"; 1041 function = "smb10"; 1042 }; 1043 smb11_pins: smb11-pins { 1044 groups = "smb11"; 1045 function = "smb11"; 1046 }; 1047 sd1_pins: sd1-pins { 1048 groups = "sd1"; 1049 function = "sd1"; 1050 }; 1051 sd1pwr_pins: sd1pwr-pins { 1052 groups = "sd1pwr"; 1053 function = "sd1pwr"; 1054 }; 1055 pwm4_pins: pwm4-pins { 1056 groups = "pwm4"; 1057 function = "pwm4"; 1058 }; 1059 pwm5_pins: pwm5-pins { 1060 groups = "pwm5"; 1061 function = "pwm5"; 1062 }; 1063 pwm6_pins: pwm6-pins { 1064 groups = "pwm6"; 1065 function = "pwm6"; 1066 }; 1067 pwm7_pins: pwm7-pins { 1068 groups = "pwm7"; 1069 function = "pwm7"; 1070 }; 1071 mmc8_pins: mmc8-pins { 1072 groups = "mmc8"; 1073 function = "mmc8"; 1074 }; 1075 mmc_pins: mmc-pins { 1076 groups = "mmc"; 1077 function = "mmc"; 1078 }; 1079 mmcwp_pins: mmcwp-pins { 1080 groups = "mmcwp"; 1081 function = "mmcwp"; 1082 }; 1083 mmccd_pins: mmccd-pins { 1084 groups = "mmccd"; 1085 function = "mmccd"; 1086 }; 1087 mmcrst_pins: mmcrst-pins { 1088 groups = "mmcrst"; 1089 function = "mmcrst"; 1090 }; 1091 clkout_pins: clkout-pins { 1092 groups = "clkout"; 1093 function = "clkout"; 1094 }; 1095 serirq_pins: serirq-pins { 1096 groups = "serirq"; 1097 function = "serirq"; 1098 }; 1099 lpcclk_pins: lpcclk-pins { 1100 groups = "lpcclk"; 1101 function = "lpcclk"; 1102 }; 1103 scipme_pins: scipme-pins { 1104 groups = "scipme"; 1105 function = "scipme"; 1106 }; 1107 sci_pins: sci-pins { 1108 groups = "sci"; 1109 function = "sci"; 1110 }; 1111 smb6_pins: smb6-pins { 1112 groups = "smb6"; 1113 function = "smb6"; 1114 }; 1115 smb7_pins: smb7-pins { 1116 groups = "smb7"; 1117 function = "smb7"; 1118 }; 1119 pspi1_pins: pspi1-pins { 1120 groups = "pspi1"; 1121 function = "pspi1"; 1122 }; 1123 faninx_pins: faninx-pins { 1124 groups = "faninx"; 1125 function = "faninx"; 1126 }; 1127 r1_pins: r1-pins { 1128 groups = "r1"; 1129 function = "r1"; 1130 }; 1131 spi3_pins: spi3-pins { 1132 groups = "spi3"; 1133 function = "spi3"; 1134 }; 1135 spi3cs1_pins: spi3cs1-pins { 1136 groups = "spi3cs1"; 1137 function = "spi3cs1"; 1138 }; 1139 spi3quad_pins: spi3quad-pins { 1140 groups = "spi3quad"; 1141 function = "spi3quad"; 1142 }; 1143 spi3cs2_pins: spi3cs2-pins { 1144 groups = "spi3cs2"; 1145 function = "spi3cs2"; 1146 }; 1147 spi3cs3_pins: spi3cs3-pins { 1148 groups = "spi3cs3"; 1149 function = "spi3cs3"; 1150 }; 1151 nprd_smi_pins: nprd-smi-pins { 1152 groups = "nprd_smi"; 1153 function = "nprd_smi"; 1154 }; 1155 smb0b_pins: smb0b-pins { 1156 groups = "smb0b"; 1157 function = "smb0b"; 1158 }; 1159 smb0c_pins: smb0c-pins { 1160 groups = "smb0c"; 1161 function = "smb0c"; 1162 }; 1163 smb0den_pins: smb0den-pins { 1164 groups = "smb0den"; 1165 function = "smb0den"; 1166 }; 1167 smb0d_pins: smb0d-pins { 1168 groups = "smb0d"; 1169 function = "smb0d"; 1170 }; 1171 ddc_pins: ddc-pins { 1172 groups = "ddc"; 1173 function = "ddc"; 1174 }; 1175 rg2mdio_pins: rg2mdio-pins { 1176 groups = "rg2mdio"; 1177 function = "rg2mdio"; 1178 }; 1179 wdog1_pins: wdog1-pins { 1180 groups = "wdog1"; 1181 function = "wdog1"; 1182 }; 1183 wdog2_pins: wdog2-pins { 1184 groups = "wdog2"; 1185 function = "wdog2"; 1186 }; 1187 smb12_pins: smb12-pins { 1188 groups = "smb12"; 1189 function = "smb12"; 1190 }; 1191 smb13_pins: smb13-pins { 1192 groups = "smb13"; 1193 function = "smb13"; 1194 }; 1195 spix_pins: spix-pins { 1196 groups = "spix"; 1197 function = "spix"; 1198 }; 1199 spixcs1_pins: spixcs1-pins { 1200 groups = "spixcs1"; 1201 function = "spixcs1"; 1202 }; 1203 clkreq_pins: clkreq-pins { 1204 groups = "clkreq"; 1205 function = "clkreq"; 1206 }; 1207 hgpio0_pins: hgpio0-pins { 1208 groups = "hgpio0"; 1209 function = "hgpio0"; 1210 }; 1211 hgpio1_pins: hgpio1-pins { 1212 groups = "hgpio1"; 1213 function = "hgpio1"; 1214 }; 1215 hgpio2_pins: hgpio2-pins { 1216 groups = "hgpio2"; 1217 function = "hgpio2"; 1218 }; 1219 hgpio3_pins: hgpio3-pins { 1220 groups = "hgpio3"; 1221 function = "hgpio3"; 1222 }; 1223 hgpio4_pins: hgpio4-pins { 1224 groups = "hgpio4"; 1225 function = "hgpio4"; 1226 }; 1227 hgpio5_pins: hgpio5-pins { 1228 groups = "hgpio5"; 1229 function = "hgpio5"; 1230 }; 1231 hgpio6_pins: hgpio6-pins { 1232 groups = "hgpio6"; 1233 function = "hgpio6"; 1234 }; 1235 hgpio7_pins: hgpio7-pins { 1236 groups = "hgpio7"; 1237 function = "hgpio7"; 1238 }; 1239 }; 1240};
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