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sama7g5.dtsi
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linux-6.19.14/arch/arm/boot/dts/microchip/sama7g5.dtsi
1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * sama7g5.dtsi - Device Tree Include file for SAMA7G5 family SoC 4 * 5 * Copyright (C) 2020 Microchip Technology, Inc. and its subsidiaries 6 * 7 * Author: Eugen Hristev <eugen.hristev@microchip.com> 8 * Author: Claudiu Beznea <claudiu.beznea@microchip.com> 9 * 10 */ 11 12#include <dt-bindings/iio/adc/at91-sama5d2_adc.h> 13#include <dt-bindings/interrupt-controller/irq.h> 14#include <dt-bindings/interrupt-controller/arm-gic.h> 15#include <dt-bindings/clock/at91.h> 16#include <dt-bindings/dma/at91.h> 17#include <dt-bindings/gpio/gpio.h> 18#include <dt-bindings/mfd/at91-usart.h> 19#include <dt-bindings/nvmem/microchip,sama7g5-otpc.h> 20#include <dt-bindings/thermal/thermal.h> 21 22/ { 23 model = "Microchip SAMA7G5 family SoC"; 24 compatible = "microchip,sama7g5"; 25 #address-cells = <1>; 26 #size-cells = <1>; 27 interrupt-parent = <&gic>; 28 29 cpus { 30 #address-cells = <1>; 31 #size-cells = <0>; 32 33 cpu0: cpu@0 { 34 device_type = "cpu"; 35 compatible = "arm,cortex-a7"; 36 reg = <0x0>; 37 clocks = <&pmc PMC_TYPE_CORE PMC_CPUPLL>; 38 clock-names = "cpu"; 39 operating-points-v2 = <&cpu_opp_table>; 40 #cooling-cells = <2>; /* min followed by max */ 41 d-cache-size = <0x8000>; // L1, 32 KB 42 i-cache-size = <0x8000>; // L1, 32 KB 43 next-level-cache = <&L2>; 44 45 L2: l2-cache { 46 compatible = "cache"; 47 cache-level = <2>; 48 cache-size = <0x40000>; // L2, 256 KB 49 cache-unified; 50 }; 51 }; 52 }; 53 54 cpu_opp_table: opp-table { 55 compatible = "operating-points-v2"; 56 57 opp-90000000 { 58 opp-hz = /bits/ 64 <90000000>; 59 opp-microvolt = <1050000 1050000 1225000>; 60 clock-latency-ns = <320000>; 61 }; 62 63 opp-250000000 { 64 opp-hz = /bits/ 64 <250000000>; 65 opp-microvolt = <1050000 1050000 1225000>; 66 clock-latency-ns = <320000>; 67 }; 68 69 opp-600000000 { 70 opp-hz = /bits/ 64 <600000000>; 71 opp-microvolt = <1050000 1050000 1225000>; 72 clock-latency-ns = <320000>; 73 opp-suspend; 74 }; 75 76 opp-800000000 { 77 opp-hz = /bits/ 64 <800000000>; 78 opp-microvolt = <1150000 1125000 1225000>; 79 clock-latency-ns = <320000>; 80 }; 81 82 opp-1000000002 { 83 opp-hz = /bits/ 64 <1000000002>; 84 opp-microvolt = <1250000 1225000 1300000>; 85 clock-latency-ns = <320000>; 86 }; 87 }; 88 89 thermal-zones { 90 cpu_thermal: cpu-thermal { 91 polling-delay-passive = <1000>; 92 polling-delay = <5000>; 93 thermal-sensors = <&thermal_sensor>; 94 95 trips { 96 cpu_normal: cpu-alert0 { 97 temperature = <90000>; 98 hysteresis = <0>; 99 type = "passive"; 100 }; 101 102 cpu_hot: cpu-alert1 { 103 temperature = <95000>; 104 hysteresis = <0>; 105 type = "passive"; 106 }; 107 108 cpu_critical: cpu-critical { 109 temperature = <100000>; 110 hysteresis = <0>; 111 type = "critical"; 112 }; 113 }; 114 115 cooling-maps { 116 map0 { 117 trip = <&cpu_normal>; 118 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 119 }; 120 121 map1 { 122 trip = <&cpu_hot>; 123 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 124 }; 125 }; 126 }; 127 }; 128 129 clocks { 130 slow_xtal: clock-slowxtal { 131 compatible = "fixed-clock"; 132 clock-output-names = "slow_xtal"; 133 #clock-cells = <0>; 134 }; 135 136 main_xtal: clock-mainxtal { 137 compatible = "fixed-clock"; 138 clock-output-names = "main_xtal"; 139 #clock-cells = <0>; 140 }; 141 142 usb_clk: clock-usbclk { 143 compatible = "fixed-clock"; 144 #clock-cells = <0>; 145 clock-output-names = "usb_clk"; 146 clock-frequency = <48000000>; 147 }; 148 }; 149 150 vddout25: fixed-regulator-vddout25 { 151 compatible = "regulator-fixed"; 152 153 regulator-name = "VDDOUT25"; 154 regulator-min-microvolt = <2500000>; 155 regulator-max-microvolt = <2500000>; 156 regulator-boot-on; 157 status = "disabled"; 158 }; 159 160 ns_sram: sram@100000 { 161 compatible = "mmio-sram"; 162 #address-cells = <1>; 163 #size-cells = <1>; 164 reg = <0x100000 0x20000>; 165 ranges; 166 }; 167 168 thermal_sensor: thermal-sensor { 169 compatible = "generic-adc-thermal"; 170 #thermal-sensor-cells = <0>; 171 io-channels = <&adc AT91_SAMA7G5_ADC_TEMP_CHANNEL>; 172 io-channel-names = "sensor-channel"; 173 }; 174 175 soc { 176 compatible = "simple-bus"; 177 #address-cells = <1>; 178 #size-cells = <1>; 179 ranges; 180 181 nfc_sram: sram@600000 { 182 compatible = "mmio-sram"; 183 no-memory-wc; 184 reg = <0x00600000 0x2400>; 185 #address-cells = <1>; 186 #size-cells = <1>; 187 ranges = <0 0x00600000 0x2400>; 188 }; 189 190 nfc_io: nfc-io@10000000 { 191 compatible = "atmel,sama5d3-nfc-io", "syscon"; 192 reg = <0x10000000 0x8000000>; 193 }; 194 195 ebi: ebi@40000000 { 196 compatible = "atmel,sama5d3-ebi"; 197 #address-cells = <2>; 198 #size-cells = <1>; 199 atmel,smc = <&hsmc>; 200 reg = <0x40000000 0x20000000>; 201 ranges = <0x0 0x0 0x40000000 0x8000000 202 0x1 0x0 0x48000000 0x8000000 203 0x2 0x0 0x50000000 0x8000000 204 0x3 0x0 0x58000000 0x8000000>; 205 clocks = <&pmc PMC_TYPE_CORE PMC_MCK1>; 206 status = "disabled"; 207 208 nand_controller: nand-controller { 209 compatible = "atmel,sama5d3-nand-controller"; 210 atmel,nfc-sram = <&nfc_sram>; 211 atmel,nfc-io = <&nfc_io>; 212 ecc-engine = <&pmecc>; 213 #address-cells = <2>; 214 #size-cells = <1>; 215 ranges; 216 status = "disabled"; 217 }; 218 }; 219 220 securam: sram@e0000000 { 221 compatible = "microchip,sama7g5-securam", "atmel,sama5d2-securam", "mmio-sram"; 222 reg = <0xe0000000 0x4000>; 223 clocks = <&pmc PMC_TYPE_PERIPHERAL 18>; 224 #address-cells = <1>; 225 #size-cells = <1>; 226 ranges = <0 0xe0000000 0x4000>; 227 no-memory-wc; 228 }; 229 230 secumod: secumod@e0004000 { 231 compatible = "microchip,sama7g5-secumod", "atmel,sama5d2-secumod", "syscon"; 232 reg = <0xe0004000 0x4000>; 233 gpio-controller; 234 #gpio-cells = <2>; 235 }; 236 237 sfrbu: sfr@e0008000 { 238 compatible = "microchip,sama7g5-sfrbu", "atmel,sama5d2-sfrbu", "syscon"; 239 reg = <0xe0008000 0x20>; 240 }; 241 242 pioA: pinctrl@e0014000 { 243 compatible = "microchip,sama7g5-pinctrl"; 244 reg = <0xe0014000 0x800>; 245 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, 246 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 247 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, 248 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, 249 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 250 interrupt-controller; 251 #interrupt-cells = <2>; 252 gpio-controller; 253 #gpio-cells = <2>; 254 clocks = <&pmc PMC_TYPE_PERIPHERAL 11>; 255 }; 256 257 pmc: clock-controller@e0018000 { 258 compatible = "microchip,sama7g5-pmc", "syscon"; 259 reg = <0xe0018000 0x200>; 260 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 261 #clock-cells = <2>; 262 clocks = <&clk32k 1>, <&clk32k 0>, <&main_xtal>; 263 clock-names = "td_slck", "md_slck", "main_xtal"; 264 }; 265 266 reset_controller: reset-controller@e001d000 { 267 compatible = "microchip,sama7g5-rstc"; 268 reg = <0xe001d000 0xc>, <0xe001d0e4 0x4>; 269 #reset-cells = <1>; 270 clocks = <&clk32k 0>; 271 }; 272 273 shdwc: poweroff@e001d010 { 274 compatible = "microchip,sama7g5-shdwc", "syscon"; 275 reg = <0xe001d010 0x10>; 276 clocks = <&clk32k 0>; 277 #address-cells = <1>; 278 #size-cells = <0>; 279 atmel,wakeup-rtc-timer; 280 atmel,wakeup-rtt-timer; 281 status = "disabled"; 282 }; 283 284 rtt: rtc@e001d020 { 285 compatible = "microchip,sama7g5-rtt", "microchip,sam9x60-rtt", "atmel,at91sam9260-rtt"; 286 reg = <0xe001d020 0x30>; 287 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 288 clocks = <&clk32k 1>; 289 }; 290 291 clk32k: clock-controller@e001d050 { 292 compatible = "microchip,sama7g5-sckc", "microchip,sam9x60-sckc"; 293 reg = <0xe001d050 0x4>; 294 clocks = <&slow_xtal>; 295 #clock-cells = <1>; 296 }; 297 298 gpbr: gpbr@e001d060 { 299 compatible = "microchip,sama7g5-gpbr", "syscon"; 300 reg = <0xe001d060 0x48>; 301 }; 302 303 rtc: rtc@e001d0a8 { 304 compatible = "microchip,sama7g5-rtc", "microchip,sam9x60-rtc"; 305 reg = <0xe001d0a8 0x30>; 306 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 307 clocks = <&clk32k 1>; 308 }; 309 310 ps_wdt: watchdog@e001d180 { 311 compatible = "microchip,sama7g5-wdt"; 312 reg = <0xe001d180 0x24>; 313 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 314 clocks = <&clk32k 0>; 315 }; 316 317 chipid@e0020000 { 318 compatible = "microchip,sama7g5-chipid"; 319 reg = <0xe0020000 0x8>; 320 }; 321 322 tcb1: timer@e0800000 { 323 compatible = "atmel,sama5d2-tcb", "simple-mfd", "syscon"; 324 #address-cells = <1>; 325 #size-cells = <0>; 326 reg = <0xe0800000 0x100>; 327 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; 328 clocks = <&pmc PMC_TYPE_PERIPHERAL 91>, <&pmc PMC_TYPE_PERIPHERAL 92>, <&pmc PMC_TYPE_PERIPHERAL 93>, <&clk32k 1>; 329 clock-names = "t0_clk", "t1_clk", "t2_clk", "slow_clk"; 330 }; 331 332 hsmc: hsmc@e0808000 { 333 compatible = "atmel,sama5d2-smc", "syscon", "simple-mfd"; 334 reg = <0xe0808000 0x1000>; 335 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 336 clocks = <&pmc PMC_TYPE_PERIPHERAL 21>; 337 #address-cells = <1>; 338 #size-cells = <1>; 339 ranges; 340 341 pmecc: ecc-engine@e0808070 { 342 compatible = "atmel,sama5d2-pmecc"; 343 reg = <0xe0808070 0x490>, 344 <0xe0808500 0x200>; 345 }; 346 }; 347 348 qspi0: spi@e080c000 { 349 compatible = "microchip,sama7g5-ospi"; 350 reg = <0xe080c000 0x400>, <0x20000000 0x10000000>; 351 reg-names = "qspi_base", "qspi_mmap"; 352 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; 353 dmas = <&dma0 AT91_XDMAC_DT_PERID(41)>, 354 <&dma0 AT91_XDMAC_DT_PERID(40)>; 355 dma-names = "tx", "rx"; 356 clocks = <&pmc PMC_TYPE_PERIPHERAL 78>, <&pmc PMC_TYPE_GCK 78>; 357 clock-names = "pclk", "gclk"; 358 #address-cells = <1>; 359 #size-cells = <0>; 360 status = "disabled"; 361 }; 362 363 qspi1: spi@e0810000 { 364 compatible = "microchip,sama7g5-qspi"; 365 reg = <0xe0810000 0x400>, <0x30000000 0x10000000>; 366 reg-names = "qspi_base", "qspi_mmap"; 367 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; 368 dmas = <&dma0 AT91_XDMAC_DT_PERID(43)>, 369 <&dma0 AT91_XDMAC_DT_PERID(42)>; 370 dma-names = "tx", "rx"; 371 clocks = <&pmc PMC_TYPE_PERIPHERAL 79>, <&pmc PMC_TYPE_GCK 79>; 372 clock-names = "pclk", "gclk"; 373 #address-cells = <1>; 374 #size-cells = <0>; 375 status = "disabled"; 376 }; 377 378 can0: can@e0828000 { 379 compatible = "bosch,m_can"; 380 reg = <0xe0828000 0x100>, <0x100000 0x7800>; 381 reg-names = "m_can", "message_ram"; 382 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>, 383 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; 384 interrupt-names = "int0", "int1"; 385 clocks = <&pmc PMC_TYPE_PERIPHERAL 61>, <&pmc PMC_TYPE_GCK 61>; 386 clock-names = "hclk", "cclk"; 387 assigned-clocks = <&pmc PMC_TYPE_GCK 61>; 388 assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_SYSPLL>; 389 assigned-clock-rates = <40000000>; 390 bosch,mram-cfg = <0x3400 0 0 64 0 0 32 32>; 391 status = "disabled"; 392 }; 393 394 can1: can@e082c000 { 395 compatible = "bosch,m_can"; 396 reg = <0xe082c000 0x100>, <0x100000 0xbc00>; 397 reg-names = "m_can", "message_ram"; 398 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>, 399 <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>; 400 interrupt-names = "int0", "int1"; 401 clocks = <&pmc PMC_TYPE_PERIPHERAL 62>, <&pmc PMC_TYPE_GCK 62>; 402 clock-names = "hclk", "cclk"; 403 assigned-clocks = <&pmc PMC_TYPE_GCK 62>; 404 assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_SYSPLL>; 405 assigned-clock-rates = <40000000>; 406 bosch,mram-cfg = <0x7800 0 0 64 0 0 32 32>; 407 status = "disabled"; 408 }; 409 410 can2: can@e0830000 { 411 compatible = "bosch,m_can"; 412 reg = <0xe0830000 0x100>, <0x100000 0x10000>; 413 reg-names = "m_can", "message_ram"; 414 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>, 415 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; 416 interrupt-names = "int0", "int1"; 417 clocks = <&pmc PMC_TYPE_PERIPHERAL 63>, <&pmc PMC_TYPE_GCK 63>; 418 clock-names = "hclk", "cclk"; 419 assigned-clocks = <&pmc PMC_TYPE_GCK 63>; 420 assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_SYSPLL>; 421 assigned-clock-rates = <40000000>; 422 bosch,mram-cfg = <0xbc00 0 0 64 0 0 32 32>; 423 status = "disabled"; 424 }; 425 426 can3: can@e0834000 { 427 compatible = "bosch,m_can"; 428 reg = <0xe0834000 0x100>, <0x110000 0x4400>; 429 reg-names = "m_can", "message_ram"; 430 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>, 431 <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>; 432 interrupt-names = "int0", "int1"; 433 clocks = <&pmc PMC_TYPE_PERIPHERAL 64>, <&pmc PMC_TYPE_GCK 64>; 434 clock-names = "hclk", "cclk"; 435 assigned-clocks = <&pmc PMC_TYPE_GCK 64>; 436 assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_SYSPLL>; 437 assigned-clock-rates = <40000000>; 438 bosch,mram-cfg = <0x0 0 0 64 0 0 32 32>; 439 status = "disabled"; 440 }; 441 442 can4: can@e0838000 { 443 compatible = "bosch,m_can"; 444 reg = <0xe0838000 0x100>, <0x110000 0x8800>; 445 reg-names = "m_can", "message_ram"; 446 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 447 <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; 448 interrupt-names = "int0", "int1"; 449 clocks = <&pmc PMC_TYPE_PERIPHERAL 65>, <&pmc PMC_TYPE_GCK 65>; 450 clock-names = "hclk", "cclk"; 451 assigned-clocks = <&pmc PMC_TYPE_GCK 65>; 452 assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_SYSPLL>; 453 assigned-clock-rates = <40000000>; 454 bosch,mram-cfg = <0x4400 0 0 64 0 0 32 32>; 455 status = "disabled"; 456 }; 457 458 can5: can@e083c000 { 459 compatible = "bosch,m_can"; 460 reg = <0xe083c000 0x100>, <0x110000 0xcc00>; 461 reg-names = "m_can", "message_ram"; 462 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>, 463 <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>; 464 interrupt-names = "int0", "int1"; 465 clocks = <&pmc PMC_TYPE_PERIPHERAL 66>, <&pmc PMC_TYPE_GCK 66>; 466 clock-names = "hclk", "cclk"; 467 assigned-clocks = <&pmc PMC_TYPE_GCK 66>; 468 assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_SYSPLL>; 469 assigned-clock-rates = <40000000>; 470 bosch,mram-cfg = <0x8800 0 0 64 0 0 32 32>; 471 status = "disabled"; 472 }; 473 474 adc: adc@e1000000 { 475 compatible = "microchip,sama7g5-adc"; 476 reg = <0xe1000000 0x200>; 477 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 478 clocks = <&pmc PMC_TYPE_GCK 26>; 479 assigned-clocks = <&pmc PMC_TYPE_GCK 26>; 480 assigned-clock-rates = <100000000>; 481 clock-names = "adc_clk"; 482 dmas = <&dma0 AT91_XDMAC_DT_PERID(0)>; 483 dma-names = "rx"; 484 atmel,min-sample-rate-hz = <200000>; 485 atmel,max-sample-rate-hz = <20000000>; 486 atmel,startup-time-ms = <4>; 487 #io-channel-cells = <1>; 488 nvmem-cells = <&temperature_calib>; 489 nvmem-cell-names = "temperature_calib"; 490 status = "disabled"; 491 }; 492 493 sdmmc0: mmc@e1204000 { 494 compatible = "microchip,sama7g5-sdhci", "microchip,sam9x60-sdhci"; 495 reg = <0xe1204000 0x4000>; 496 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; 497 clocks = <&pmc PMC_TYPE_PERIPHERAL 80>, <&pmc PMC_TYPE_GCK 80>; 498 clock-names = "hclock", "multclk"; 499 assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_SYSPLL>; 500 assigned-clocks = <&pmc PMC_TYPE_GCK 80>; 501 assigned-clock-rates = <200000000>; 502 microchip,sdcal-inverted; 503 status = "disabled"; 504 }; 505 506 sdmmc1: mmc@e1208000 { 507 compatible = "microchip,sama7g5-sdhci", "microchip,sam9x60-sdhci"; 508 reg = <0xe1208000 0x4000>; 509 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 510 clocks = <&pmc PMC_TYPE_PERIPHERAL 81>, <&pmc PMC_TYPE_GCK 81>; 511 clock-names = "hclock", "multclk"; 512 assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_SYSPLL>; 513 assigned-clocks = <&pmc PMC_TYPE_GCK 81>; 514 assigned-clock-rates = <200000000>; 515 microchip,sdcal-inverted; 516 status = "disabled"; 517 }; 518 519 sdmmc2: mmc@e120c000 { 520 compatible = "microchip,sama7g5-sdhci", "microchip,sam9x60-sdhci"; 521 reg = <0xe120c000 0x4000>; 522 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 523 clocks = <&pmc PMC_TYPE_PERIPHERAL 82>, <&pmc PMC_TYPE_GCK 82>; 524 clock-names = "hclock", "multclk"; 525 assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_SYSPLL>; 526 assigned-clocks = <&pmc PMC_TYPE_GCK 82>; 527 assigned-clock-rates = <200000000>; 528 microchip,sdcal-inverted; 529 status = "disabled"; 530 }; 531 532 csi2dc: csi2dc@e1404000 { 533 compatible = "microchip,sama7g5-csi2dc"; 534 reg = <0xe1404000 0x500>; 535 clocks = <&pmc PMC_TYPE_PERIPHERAL 34>, <&xisc>; 536 clock-names = "pclk", "scck"; 537 assigned-clocks = <&xisc>; 538 assigned-clock-rates = <266000000>; 539 status = "disabled"; 540 541 ports { 542 #address-cells = <1>; 543 #size-cells = <0>; 544 port@0 { 545 reg = <0>; 546 csi2dc_in: endpoint { 547 }; 548 }; 549 550 port@1 { 551 reg = <1>; 552 csi2dc_out: endpoint { 553 bus-width = <14>; 554 hsync-active = <1>; 555 vsync-active = <1>; 556 remote-endpoint = <&xisc_in>; 557 }; 558 }; 559 }; 560 }; 561 562 xisc: xisc@e1408000 { 563 compatible = "microchip,sama7g5-isc"; 564 reg = <0xe1408000 0x2000>; 565 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; 566 clocks = <&pmc PMC_TYPE_PERIPHERAL 56>; 567 clock-names = "hclock"; 568 #clock-cells = <0>; 569 clock-output-names = "isc-mck"; 570 status = "disabled"; 571 572 port { 573 xisc_in: endpoint { 574 bus-type = <5>; /* Parallel */ 575 bus-width = <14>; 576 hsync-active = <1>; 577 vsync-active = <1>; 578 remote-endpoint = <&csi2dc_out>; 579 }; 580 }; 581 }; 582 583 pwm: pwm@e1604000 { 584 compatible = "microchip,sama7g5-pwm", "atmel,sama5d2-pwm"; 585 reg = <0xe1604000 0x4000>; 586 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 587 #pwm-cells = <3>; 588 clocks = <&pmc PMC_TYPE_PERIPHERAL 77>; 589 status = "disabled"; 590 }; 591 592 pdmc0: sound@e1608000 { 593 compatible = "microchip,sama7g5-pdmc"; 594 reg = <0xe1608000 0x1000>; 595 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>; 596 #sound-dai-cells = <0>; 597 dmas = <&dma0 AT91_XDMAC_DT_PERID(37)>; 598 dma-names = "rx"; 599 clocks = <&pmc PMC_TYPE_PERIPHERAL 68>, <&pmc PMC_TYPE_GCK 68>; 600 clock-names = "pclk", "gclk"; 601 status = "disabled"; 602 }; 603 604 pdmc1: sound@e160c000 { 605 compatible = "microchip,sama7g5-pdmc"; 606 reg = <0xe160c000 0x1000>; 607 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; 608 #sound-dai-cells = <0>; 609 dmas = <&dma0 AT91_XDMAC_DT_PERID(38)>; 610 dma-names = "rx"; 611 clocks = <&pmc PMC_TYPE_PERIPHERAL 69>, <&pmc PMC_TYPE_GCK 69>; 612 clock-names = "pclk", "gclk"; 613 status = "disabled"; 614 }; 615 616 spdifrx: spdifrx@e1614000 { 617 #sound-dai-cells = <0>; 618 compatible = "microchip,sama7g5-spdifrx"; 619 reg = <0xe1614000 0x4000>; 620 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 621 dmas = <&dma0 AT91_XDMAC_DT_PERID(49)>; 622 dma-names = "rx"; 623 clocks = <&pmc PMC_TYPE_PERIPHERAL 84>, <&pmc PMC_TYPE_GCK 84>; 624 clock-names = "pclk", "gclk"; 625 status = "disabled"; 626 }; 627 628 spdiftx: spdiftx@e1618000 { 629 #sound-dai-cells = <0>; 630 compatible = "microchip,sama7g5-spdiftx"; 631 reg = <0xe1618000 0x4000>; 632 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; 633 dmas = <&dma0 AT91_XDMAC_DT_PERID(50)>; 634 dma-names = "tx"; 635 clocks = <&pmc PMC_TYPE_PERIPHERAL 85>, <&pmc PMC_TYPE_GCK 85>; 636 clock-names = "pclk", "gclk"; 637 }; 638 639 i2s0: i2s@e161c000 { 640 compatible = "microchip,sama7g5-i2smcc"; 641 #sound-dai-cells = <0>; 642 reg = <0xe161c000 0x4000>; 643 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; 644 dmas = <&dma0 AT91_XDMAC_DT_PERID(34)>, <&dma0 AT91_XDMAC_DT_PERID(33)>; 645 dma-names = "tx", "rx"; 646 clocks = <&pmc PMC_TYPE_PERIPHERAL 57>, <&pmc PMC_TYPE_GCK 57>; 647 clock-names = "pclk", "gclk"; 648 status = "disabled"; 649 }; 650 651 i2s1: i2s@e1620000 { 652 compatible = "microchip,sama7g5-i2smcc"; 653 #sound-dai-cells = <0>; 654 reg = <0xe1620000 0x4000>; 655 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>; 656 dmas = <&dma0 AT91_XDMAC_DT_PERID(36)>, <&dma0 AT91_XDMAC_DT_PERID(35)>; 657 dma-names = "tx", "rx"; 658 clocks = <&pmc PMC_TYPE_PERIPHERAL 58>, <&pmc PMC_TYPE_GCK 58>; 659 clock-names = "pclk", "gclk"; 660 status = "disabled"; 661 }; 662 663 eic: interrupt-controller@e1628000 { 664 compatible = "microchip,sama7g5-eic"; 665 reg = <0xe1628000 0xec>; 666 interrupt-parent = <&gic>; 667 interrupt-controller; 668 #interrupt-cells = <2>; 669 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, 670 <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; 671 clocks = <&pmc PMC_TYPE_PERIPHERAL 37>; 672 clock-names = "pclk"; 673 status = "disabled"; 674 }; 675 676 pit64b0: timer@e1800000 { 677 compatible = "microchip,sama7g5-pit64b", "microchip,sam9x60-pit64b"; 678 reg = <0xe1800000 0x4000>; 679 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; 680 clocks = <&pmc PMC_TYPE_PERIPHERAL 70>, <&pmc PMC_TYPE_GCK 70>; 681 clock-names = "pclk", "gclk"; 682 }; 683 684 pit64b1: timer@e1804000 { 685 compatible = "microchip,sama7g5-pit64b", "microchip,sam9x60-pit64b"; 686 reg = <0xe1804000 0x4000>; 687 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 688 clocks = <&pmc PMC_TYPE_PERIPHERAL 71>, <&pmc PMC_TYPE_GCK 71>; 689 clock-names = "pclk", "gclk"; 690 }; 691 692 aes: crypto@e1810000 { 693 compatible = "atmel,at91sam9g46-aes"; 694 reg = <0xe1810000 0x100>; 695 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 696 clocks = <&pmc PMC_TYPE_PERIPHERAL 27>; 697 clock-names = "aes_clk"; 698 dmas = <&dma0 AT91_XDMAC_DT_PERID(1)>, 699 <&dma0 AT91_XDMAC_DT_PERID(2)>; 700 dma-names = "tx", "rx"; 701 }; 702 703 sha: crypto@e1814000 { 704 compatible = "atmel,at91sam9g46-sha"; 705 reg = <0xe1814000 0x100>; 706 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 707 clocks = <&pmc PMC_TYPE_PERIPHERAL 83>; 708 clock-names = "sha_clk"; 709 dmas = <&dma0 AT91_XDMAC_DT_PERID(48)>; 710 dma-names = "tx"; 711 }; 712 713 flx0: flexcom@e1818000 { 714 compatible = "microchip,sama7g5-flexcom", "atmel,sama5d2-flexcom"; 715 reg = <0xe1818000 0x200>; 716 clocks = <&pmc PMC_TYPE_PERIPHERAL 38>; 717 #address-cells = <1>; 718 #size-cells = <1>; 719 ranges = <0x0 0xe1818000 0x800>; 720 status = "disabled"; 721 722 uart0: serial@200 { 723 compatible = "atmel,at91sam9260-usart"; 724 reg = <0x200 0x200>; 725 atmel,usart-mode = <AT91_USART_MODE_SERIAL>; 726 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 727 clocks = <&pmc PMC_TYPE_PERIPHERAL 38>; 728 clock-names = "usart"; 729 dmas = <&dma1 AT91_XDMAC_DT_PERID(6)>, 730 <&dma1 AT91_XDMAC_DT_PERID(5)>; 731 dma-names = "tx", "rx"; 732 atmel,use-dma-rx; 733 atmel,use-dma-tx; 734 status = "disabled"; 735 }; 736 }; 737 738 flx1: flexcom@e181c000 { 739 compatible = "microchip,sama7g5-flexcom", "atmel,sama5d2-flexcom"; 740 reg = <0xe181c000 0x200>; 741 clocks = <&pmc PMC_TYPE_PERIPHERAL 39>; 742 #address-cells = <1>; 743 #size-cells = <1>; 744 ranges = <0x0 0xe181c000 0x800>; 745 status = "disabled"; 746 747 i2c1: i2c@600 { 748 compatible = "microchip,sama7g5-i2c", "microchip,sam9x60-i2c"; 749 reg = <0x600 0x200>; 750 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; 751 #address-cells = <1>; 752 #size-cells = <0>; 753 clocks = <&pmc PMC_TYPE_PERIPHERAL 39>; 754 atmel,fifo-size = <32>; 755 dmas = <&dma0 AT91_XDMAC_DT_PERID(8)>, 756 <&dma0 AT91_XDMAC_DT_PERID(7)>; 757 dma-names = "tx", "rx"; 758 status = "disabled"; 759 }; 760 }; 761 762 flx3: flexcom@e1824000 { 763 compatible = "microchip,sama7g5-flexcom", "atmel,sama5d2-flexcom"; 764 reg = <0xe1824000 0x200>; 765 clocks = <&pmc PMC_TYPE_PERIPHERAL 41>; 766 #address-cells = <1>; 767 #size-cells = <1>; 768 ranges = <0x0 0xe1824000 0x800>; 769 status = "disabled"; 770 771 uart3: serial@200 { 772 compatible = "atmel,at91sam9260-usart"; 773 reg = <0x200 0x200>; 774 atmel,usart-mode = <AT91_USART_MODE_SERIAL>; 775 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; 776 clocks = <&pmc PMC_TYPE_PERIPHERAL 41>; 777 clock-names = "usart"; 778 dmas = <&dma1 AT91_XDMAC_DT_PERID(12)>, 779 <&dma1 AT91_XDMAC_DT_PERID(11)>; 780 dma-names = "tx", "rx"; 781 atmel,use-dma-rx; 782 atmel,use-dma-tx; 783 status = "disabled"; 784 }; 785 }; 786 787 trng: rng@e2010000 { 788 compatible = "microchip,sama7g5-trng", "atmel,at91sam9g45-trng"; 789 reg = <0xe2010000 0x100>; 790 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 791 clocks = <&pmc PMC_TYPE_PERIPHERAL 97>; 792 status = "disabled"; 793 }; 794 795 tdes: crypto@e2014000 { 796 compatible = "atmel,at91sam9g46-tdes"; 797 reg = <0xe2014000 0x100>; 798 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 799 clocks = <&pmc PMC_TYPE_PERIPHERAL 96>; 800 clock-names = "tdes_clk"; 801 dmas = <&dma0 AT91_XDMAC_DT_PERID(54)>, 802 <&dma0 AT91_XDMAC_DT_PERID(53)>; 803 dma-names = "tx", "rx"; 804 }; 805 806 flx4: flexcom@e2018000 { 807 compatible = "microchip,sama7g5-flexcom", "atmel,sama5d2-flexcom"; 808 reg = <0xe2018000 0x200>; 809 clocks = <&pmc PMC_TYPE_PERIPHERAL 42>; 810 #address-cells = <1>; 811 #size-cells = <1>; 812 ranges = <0x0 0xe2018000 0x800>; 813 status = "disabled"; 814 815 uart4: serial@200 { 816 compatible = "atmel,at91sam9260-usart"; 817 reg = <0x200 0x200>; 818 atmel,usart-mode = <AT91_USART_MODE_SERIAL>; 819 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; 820 clocks = <&pmc PMC_TYPE_PERIPHERAL 42>; 821 clock-names = "usart"; 822 dmas = <&dma1 AT91_XDMAC_DT_PERID(14)>, 823 <&dma1 AT91_XDMAC_DT_PERID(13)>; 824 dma-names = "tx", "rx"; 825 atmel,use-dma-rx; 826 atmel,use-dma-tx; 827 atmel,fifo-size = <32>; 828 status = "disabled"; 829 }; 830 }; 831 832 flx7: flexcom@e2024000 { 833 compatible = "microchip,sama7g5-flexcom", "atmel,sama5d2-flexcom"; 834 reg = <0xe2024000 0x200>; 835 clocks = <&pmc PMC_TYPE_PERIPHERAL 45>; 836 #address-cells = <1>; 837 #size-cells = <1>; 838 ranges = <0x0 0xe2024000 0x800>; 839 status = "disabled"; 840 841 uart7: serial@200 { 842 compatible = "atmel,at91sam9260-usart"; 843 reg = <0x200 0x200>; 844 atmel,usart-mode = <AT91_USART_MODE_SERIAL>; 845 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 846 clocks = <&pmc PMC_TYPE_PERIPHERAL 45>; 847 clock-names = "usart"; 848 dmas = <&dma1 AT91_XDMAC_DT_PERID(20)>, 849 <&dma1 AT91_XDMAC_DT_PERID(19)>; 850 dma-names = "tx", "rx"; 851 atmel,use-dma-rx; 852 atmel,use-dma-tx; 853 atmel,fifo-size = <32>; 854 status = "disabled"; 855 }; 856 }; 857 858 gmac0: ethernet@e2800000 { 859 compatible = "microchip,sama7g5-gem"; 860 reg = <0xe2800000 0x1000>; 861 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, 862 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 863 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 864 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 865 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, 866 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; 867 clocks = <&pmc PMC_TYPE_PERIPHERAL 51>, <&pmc PMC_TYPE_PERIPHERAL 51>, <&pmc PMC_TYPE_GCK 51>, <&pmc PMC_TYPE_GCK 53>; 868 clock-names = "pclk", "hclk", "tx_clk", "tsu_clk"; 869 assigned-clocks = <&pmc PMC_TYPE_GCK 51>; 870 assigned-clock-rates = <125000000>; 871 status = "disabled"; 872 }; 873 874 gmac1: ethernet@e2804000 { 875 compatible = "microchip,sama7g5-emac"; 876 reg = <0xe2804000 0x1000>; 877 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>, 878 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; 879 clocks = <&pmc PMC_TYPE_PERIPHERAL 52>, <&pmc PMC_TYPE_PERIPHERAL 52>; 880 clock-names = "pclk", "hclk"; 881 status = "disabled"; 882 }; 883 884 dma0: dma-controller@e2808000 { 885 compatible = "microchip,sama7g5-dma"; 886 reg = <0xe2808000 0x1000>; 887 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 888 #dma-cells = <1>; 889 clocks = <&pmc PMC_TYPE_PERIPHERAL 22>; 890 clock-names = "dma_clk"; 891 status = "disabled"; 892 }; 893 894 dma1: dma-controller@e280c000 { 895 compatible = "microchip,sama7g5-dma"; 896 reg = <0xe280c000 0x1000>; 897 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; 898 #dma-cells = <1>; 899 clocks = <&pmc PMC_TYPE_PERIPHERAL 23>; 900 clock-names = "dma_clk"; 901 status = "disabled"; 902 }; 903 904 /* Place dma2 here despite it's address */ 905 dma2: dma-controller@e1200000 { 906 compatible = "microchip,sama7g5-dma"; 907 reg = <0xe1200000 0x1000>; 908 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 909 #dma-cells = <1>; 910 clocks = <&pmc PMC_TYPE_PERIPHERAL 24>; 911 clock-names = "dma_clk"; 912 dma-requests = <0>; 913 status = "disabled"; 914 }; 915 916 tcb0: timer@e2814000 { 917 compatible = "atmel,sama5d2-tcb", "simple-mfd", "syscon"; 918 #address-cells = <1>; 919 #size-cells = <0>; 920 reg = <0xe2814000 0x100>; 921 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; 922 clocks = <&pmc PMC_TYPE_PERIPHERAL 88>, <&pmc PMC_TYPE_PERIPHERAL 89>, <&pmc PMC_TYPE_PERIPHERAL 90>, <&clk32k 1>; 923 clock-names = "t0_clk", "t1_clk", "t2_clk", "slow_clk"; 924 }; 925 926 flx8: flexcom@e2818000 { 927 compatible = "microchip,sama7g5-flexcom", "atmel,sama5d2-flexcom"; 928 reg = <0xe2818000 0x200>; 929 clocks = <&pmc PMC_TYPE_PERIPHERAL 46>; 930 #address-cells = <1>; 931 #size-cells = <1>; 932 ranges = <0x0 0xe2818000 0x800>; 933 status = "disabled"; 934 935 i2c8: i2c@600 { 936 compatible = "microchip,sama7g5-i2c", "microchip,sam9x60-i2c"; 937 reg = <0x600 0x200>; 938 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; 939 #address-cells = <1>; 940 #size-cells = <0>; 941 clocks = <&pmc PMC_TYPE_PERIPHERAL 46>; 942 atmel,fifo-size = <32>; 943 dmas = <&dma0 AT91_XDMAC_DT_PERID(22)>, 944 <&dma0 AT91_XDMAC_DT_PERID(21)>; 945 dma-names = "tx", "rx"; 946 status = "disabled"; 947 }; 948 }; 949 950 flx9: flexcom@e281c000 { 951 compatible = "microchip,sama7g5-flexcom", "atmel,sama5d2-flexcom"; 952 reg = <0xe281c000 0x200>; 953 clocks = <&pmc PMC_TYPE_PERIPHERAL 47>; 954 #address-cells = <1>; 955 #size-cells = <1>; 956 ranges = <0x0 0xe281c000 0x800>; 957 status = "disabled"; 958 959 i2c9: i2c@600 { 960 compatible = "microchip,sama7g5-i2c", "microchip,sam9x60-i2c"; 961 reg = <0x600 0x200>; 962 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; 963 #address-cells = <1>; 964 #size-cells = <0>; 965 clocks = <&pmc PMC_TYPE_PERIPHERAL 47>; 966 atmel,fifo-size = <32>; 967 dmas = <&dma0 AT91_XDMAC_DT_PERID(24)>, 968 <&dma0 AT91_XDMAC_DT_PERID(23)>; 969 dma-names = "tx", "rx"; 970 status = "disabled"; 971 }; 972 }; 973 974 flx10: flexcom@e2820000 { 975 compatible = "microchip,sama7g5-flexcom", "atmel,sama5d2-flexcom"; 976 reg = <0xe2820000 0x200>; 977 clocks = <&pmc PMC_TYPE_PERIPHERAL 48>; 978 #address-cells = <1>; 979 #size-cells = <1>; 980 ranges = <0x0 0xe2820000 0x800>; 981 status = "disabled"; 982 983 i2c10: i2c@600 { 984 compatible = "microchip,sama7g5-i2c", "microchip,sam9x60-i2c"; 985 reg = <0x600 0x200>; 986 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; 987 #address-cells = <1>; 988 #size-cells = <0>; 989 clocks = <&pmc PMC_TYPE_PERIPHERAL 48>; 990 atmel,fifo-size = <32>; 991 dmas = <&dma0 AT91_XDMAC_DT_PERID(26)>, 992 <&dma0 AT91_XDMAC_DT_PERID(25)>; 993 dma-names = "tx", "rx"; 994 status = "disabled"; 995 }; 996 }; 997 998 flx11: flexcom@e2824000 { 999 compatible = "microchip,sama7g5-flexcom", "atmel,sama5d2-flexcom"; 1000 reg = <0xe2824000 0x200>; 1001 clocks = <&pmc PMC_TYPE_PERIPHERAL 49>; 1002 #address-cells = <1>; 1003 #size-cells = <1>; 1004 ranges = <0x0 0xe2824000 0x800>; 1005 status = "disabled"; 1006 1007 spi11: spi@400 { 1008 compatible = "atmel,at91rm9200-spi"; 1009 reg = <0x400 0x200>; 1010 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; 1011 clocks = <&pmc PMC_TYPE_PERIPHERAL 49>; 1012 clock-names = "spi_clk"; 1013 #address-cells = <1>; 1014 #size-cells = <0>; 1015 atmel,fifo-size = <32>; 1016 dmas = <&dma0 AT91_XDMAC_DT_PERID(28)>, 1017 <&dma0 AT91_XDMAC_DT_PERID(27)>; 1018 dma-names = "tx", "rx"; 1019 status = "disabled"; 1020 }; 1021 }; 1022 1023 uddrc: uddrc@e3800000 { 1024 compatible = "microchip,sama7g5-uddrc"; 1025 reg = <0xe3800000 0x4000>; 1026 }; 1027 1028 ddr3phy: ddr3phy@e3804000 { 1029 compatible = "microchip,sama7g5-ddr3phy"; 1030 reg = <0xe3804000 0x1000>; 1031 }; 1032 1033 otpc: efuse@e8c00000 { 1034 compatible = "microchip,sama7g5-otpc", "syscon"; 1035 reg = <0xe8c00000 0x100>; 1036 #address-cells = <1>; 1037 #size-cells = <1>; 1038 1039 temperature_calib: calib@1 { 1040 reg = <OTP_PKT(1) 76>; 1041 }; 1042 }; 1043 1044 gic: interrupt-controller@e8c11000 { 1045 compatible = "arm,cortex-a7-gic"; 1046 #interrupt-cells = <3>; 1047 #address-cells = <0>; 1048 interrupt-controller; 1049 reg = <0xe8c11000 0x1000>, 1050 <0xe8c12000 0x2000>; 1051 }; 1052 }; 1053};
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