FILE
sama5d4.dtsi
File preview with syntax highlighting.
linux-6.19.14/arch/arm/boot/dts/microchip/sama5d4.dtsi
1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * sama5d4.dtsi - Device Tree Include file for SAMA5D4 family SoC 4 * 5 * Copyright (C) 2014 Atmel, 6 * 2014 Nicolas Ferre <nicolas.ferre@atmel.com> 7 */ 8 9#include <dt-bindings/clock/at91.h> 10#include <dt-bindings/dma/at91.h> 11#include <dt-bindings/mfd/at91-usart.h> 12#include <dt-bindings/pinctrl/at91.h> 13#include <dt-bindings/interrupt-controller/irq.h> 14#include <dt-bindings/gpio/gpio.h> 15 16/ { 17 #address-cells = <1>; 18 #size-cells = <1>; 19 model = "Atmel SAMA5D4 family SoC"; 20 compatible = "atmel,sama5d4"; 21 interrupt-parent = <&aic>; 22 23 aliases { 24 serial0 = &usart3; 25 serial1 = &usart4; 26 serial2 = &usart2; 27 serial3 = &usart0; 28 serial4 = &usart1; 29 serial5 = &uart0; 30 serial6 = &uart1; 31 gpio0 = &pioA; 32 gpio1 = &pioB; 33 gpio2 = &pioC; 34 gpio3 = &pioD; 35 gpio4 = &pioE; 36 pwm0 = &pwm0; 37 ssc0 = &ssc0; 38 ssc1 = &ssc1; 39 tcb0 = &tcb0; 40 tcb1 = &tcb1; 41 i2c0 = &i2c0; 42 i2c1 = &i2c1; 43 i2c2 = &i2c2; 44 }; 45 cpus { 46 #address-cells = <1>; 47 #size-cells = <0>; 48 49 cpu@0 { 50 device_type = "cpu"; 51 compatible = "arm,cortex-a5"; 52 reg = <0>; 53 d-cache-size = <0x8000>; // L1, 32 KB 54 i-cache-size = <0x8000>; // L1, 32 KB 55 next-level-cache = <&L2>; 56 }; 57 }; 58 59 memory@20000000 { 60 device_type = "memory"; 61 reg = <0x20000000 0x20000000>; 62 }; 63 64 clocks { 65 slow_xtal: slow_xtal { 66 compatible = "fixed-clock"; 67 #clock-cells = <0>; 68 clock-frequency = <0>; 69 }; 70 71 main_xtal: main_xtal { 72 compatible = "fixed-clock"; 73 #clock-cells = <0>; 74 clock-frequency = <0>; 75 }; 76 77 adc_op_clk: adc_op_clk { 78 compatible = "fixed-clock"; 79 #clock-cells = <0>; 80 clock-frequency = <1000000>; 81 }; 82 }; 83 84 ns_sram: sram@210000 { 85 compatible = "mmio-sram"; 86 reg = <0x00210000 0x10000>; 87 #address-cells = <1>; 88 #size-cells = <1>; 89 ranges = <0 0x00210000 0x10000>; 90 }; 91 92 ahb { 93 compatible = "simple-bus"; 94 #address-cells = <1>; 95 #size-cells = <1>; 96 ranges; 97 98 nfc_sram: sram@100000 { 99 compatible = "mmio-sram"; 100 no-memory-wc; 101 reg = <0x100000 0x2400>; 102 #address-cells = <1>; 103 #size-cells = <1>; 104 ranges = <0 0x100000 0x2400>; 105 }; 106 107 vdec0: vdec@300000 { 108 compatible = "microchip,sama5d4-vdec"; 109 reg = <0x00300000 0x100000>; 110 interrupts = <19 IRQ_TYPE_LEVEL_HIGH 4>; 111 clocks = <&pmc PMC_TYPE_PERIPHERAL 19>; 112 }; 113 114 usb0: gadget@400000 { 115 compatible = "atmel,sama5d3-udc"; 116 reg = <0x00400000 0x100000 117 0xfc02c000 0x4000>; 118 interrupts = <47 IRQ_TYPE_LEVEL_HIGH 2>; 119 clocks = <&pmc PMC_TYPE_PERIPHERAL 47>, <&pmc PMC_TYPE_CORE PMC_UTMI>; 120 clock-names = "pclk", "hclk"; 121 status = "disabled"; 122 }; 123 124 usb1: usb@500000 { 125 compatible = "atmel,at91rm9200-ohci", "usb-ohci"; 126 reg = <0x00500000 0x100000>; 127 interrupts = <46 IRQ_TYPE_LEVEL_HIGH 2>; 128 clocks = <&pmc PMC_TYPE_PERIPHERAL 46>, <&pmc PMC_TYPE_PERIPHERAL 46>, <&pmc PMC_TYPE_SYSTEM 6>; 129 clock-names = "ohci_clk", "hclk", "uhpck"; 130 status = "disabled"; 131 }; 132 133 usb2: usb@600000 { 134 compatible = "atmel,at91sam9g45-ehci", "usb-ehci"; 135 reg = <0x00600000 0x100000>; 136 interrupts = <46 IRQ_TYPE_LEVEL_HIGH 2>; 137 clocks = <&pmc PMC_TYPE_CORE PMC_UTMI>, <&pmc PMC_TYPE_PERIPHERAL 46>; 138 clock-names = "usb_clk", "ehci_clk"; 139 status = "disabled"; 140 }; 141 142 L2: cache-controller@a00000 { 143 compatible = "arm,pl310-cache"; 144 reg = <0x00a00000 0x1000>; 145 interrupts = <67 IRQ_TYPE_LEVEL_HIGH 4>; 146 cache-unified; 147 cache-level = <2>; 148 cache-size = <0x20000>; // L2, 128 KB 149 }; 150 151 ebi: ebi@10000000 { 152 compatible = "atmel,sama5d3-ebi"; 153 #address-cells = <2>; 154 #size-cells = <1>; 155 atmel,smc = <&hsmc>; 156 reg = <0x10000000 0x10000000 157 0x60000000 0x28000000>; 158 ranges = <0x0 0x0 0x10000000 0x10000000 159 0x1 0x0 0x60000000 0x10000000 160 0x2 0x0 0x70000000 0x10000000 161 0x3 0x0 0x80000000 0x8000000>; 162 clocks = <&pmc PMC_TYPE_CORE PMC_MCK>; 163 status = "disabled"; 164 165 nand_controller: nand-controller { 166 compatible = "atmel,sama5d3-nand-controller"; 167 atmel,nfc-sram = <&nfc_sram>; 168 atmel,nfc-io = <&nfc_io>; 169 ecc-engine = <&pmecc>; 170 #address-cells = <2>; 171 #size-cells = <1>; 172 ranges; 173 status = "disabled"; 174 }; 175 }; 176 177 nfc_io: nfc-io@90000000 { 178 compatible = "atmel,sama5d3-nfc-io", "syscon"; 179 reg = <0x90000000 0x8000000>; 180 }; 181 182 apb { 183 compatible = "simple-bus"; 184 #address-cells = <1>; 185 #size-cells = <1>; 186 ranges; 187 188 hlcdc: hlcdc@f0000000 { 189 compatible = "atmel,sama5d4-hlcdc"; 190 reg = <0xf0000000 0x4000>; 191 interrupts = <51 IRQ_TYPE_LEVEL_HIGH 0>; 192 clocks = <&pmc PMC_TYPE_PERIPHERAL 51>, <&pmc PMC_TYPE_SYSTEM 3>, <&clk32k>; 193 clock-names = "periph_clk","sys_clk", "slow_clk"; 194 status = "disabled"; 195 196 hlcdc-display-controller { 197 compatible = "atmel,hlcdc-display-controller"; 198 #address-cells = <1>; 199 #size-cells = <0>; 200 201 port@0 { 202 #address-cells = <1>; 203 #size-cells = <0>; 204 reg = <0>; 205 }; 206 }; 207 208 hlcdc_pwm: hlcdc-pwm { 209 compatible = "atmel,hlcdc-pwm"; 210 pinctrl-names = "default"; 211 pinctrl-0 = <&pinctrl_lcd_pwm>; 212 #pwm-cells = <3>; 213 }; 214 }; 215 216 dma1: dma-controller@f0004000 { 217 compatible = "atmel,sama5d4-dma"; 218 reg = <0xf0004000 0x200>; 219 interrupts = <50 IRQ_TYPE_LEVEL_HIGH 0>; 220 #dma-cells = <1>; 221 clocks = <&pmc PMC_TYPE_PERIPHERAL 50>; 222 clock-names = "dma_clk"; 223 }; 224 225 isi: isi@f0008000 { 226 compatible = "atmel,at91sam9g45-isi"; 227 reg = <0xf0008000 0x4000>; 228 interrupts = <52 IRQ_TYPE_LEVEL_HIGH 5>; 229 pinctrl-names = "default"; 230 pinctrl-0 = <&pinctrl_isi_data_0_7>; 231 clocks = <&pmc PMC_TYPE_PERIPHERAL 52>; 232 clock-names = "isi_clk"; 233 status = "disabled"; 234 port { 235 #address-cells = <1>; 236 #size-cells = <0>; 237 }; 238 }; 239 240 ramc0: ramc@f0010000 { 241 compatible = "atmel,sama5d3-ddramc"; 242 reg = <0xf0010000 0x200>; 243 clocks = <&pmc PMC_TYPE_SYSTEM 2>, <&pmc PMC_TYPE_PERIPHERAL 16>; 244 clock-names = "ddrck", "mpddr"; 245 }; 246 247 dma0: dma-controller@f0014000 { 248 compatible = "atmel,sama5d4-dma"; 249 reg = <0xf0014000 0x200>; 250 interrupts = <8 IRQ_TYPE_LEVEL_HIGH 0>; 251 #dma-cells = <1>; 252 clocks = <&pmc PMC_TYPE_PERIPHERAL 8>; 253 clock-names = "dma_clk"; 254 }; 255 256 pmc: clock-controller@f0018000 { 257 compatible = "atmel,sama5d4-pmc", "syscon"; 258 reg = <0xf0018000 0x120>; 259 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; 260 #clock-cells = <2>; 261 clocks = <&clk32k>, <&main_xtal>; 262 clock-names = "slow_clk", "main_xtal"; 263 }; 264 265 mmc0: mmc@f8000000 { 266 compatible = "atmel,hsmci"; 267 reg = <0xf8000000 0x600>; 268 interrupts = <35 IRQ_TYPE_LEVEL_HIGH 0>; 269 dmas = <&dma1 270 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) 271 | AT91_XDMAC_DT_PERID(0))>; 272 dma-names = "rxtx"; 273 pinctrl-names = "default"; 274 pinctrl-0 = <&pinctrl_mmc0_clk_cmd_dat0 &pinctrl_mmc0_dat1_3>; 275 status = "disabled"; 276 #address-cells = <1>; 277 #size-cells = <0>; 278 clocks = <&pmc PMC_TYPE_PERIPHERAL 35>; 279 clock-names = "mci_clk"; 280 }; 281 282 uart0: serial@f8004000 { 283 compatible = "atmel,at91sam9260-usart"; 284 reg = <0xf8004000 0x100>; 285 atmel,usart-mode = <AT91_USART_MODE_SERIAL>; 286 interrupts = <27 IRQ_TYPE_LEVEL_HIGH 5>; 287 dmas = <&dma0 288 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) 289 | AT91_XDMAC_DT_PERID(22))>, 290 <&dma0 291 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) 292 | AT91_XDMAC_DT_PERID(23))>; 293 dma-names = "tx", "rx"; 294 pinctrl-names = "default"; 295 pinctrl-0 = <&pinctrl_uart0>; 296 clocks = <&pmc PMC_TYPE_PERIPHERAL 27>; 297 clock-names = "usart"; 298 status = "disabled"; 299 }; 300 301 ssc0: ssc@f8008000 { 302 compatible = "atmel,at91sam9g45-ssc"; 303 reg = <0xf8008000 0x4000>; 304 interrupts = <48 IRQ_TYPE_LEVEL_HIGH 0>; 305 pinctrl-names = "default"; 306 pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>; 307 dmas = <&dma1 308 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) 309 | AT91_XDMAC_DT_PERID(26))>, 310 <&dma1 311 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) 312 | AT91_XDMAC_DT_PERID(27))>; 313 dma-names = "tx", "rx"; 314 clocks = <&pmc PMC_TYPE_PERIPHERAL 48>; 315 clock-names = "pclk"; 316 status = "disabled"; 317 }; 318 319 pwm0: pwm@f800c000 { 320 compatible = "atmel,sama5d3-pwm"; 321 reg = <0xf800c000 0x300>; 322 interrupts = <43 IRQ_TYPE_LEVEL_HIGH 4>; 323 #pwm-cells = <3>; 324 clocks = <&pmc PMC_TYPE_PERIPHERAL 43>; 325 status = "disabled"; 326 }; 327 328 spi0: spi@f8010000 { 329 #address-cells = <1>; 330 #size-cells = <0>; 331 compatible = "atmel,at91rm9200-spi"; 332 reg = <0xf8010000 0x100>; 333 interrupts = <37 IRQ_TYPE_LEVEL_HIGH 3>; 334 dmas = <&dma1 335 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) 336 | AT91_XDMAC_DT_PERID(10))>, 337 <&dma1 338 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) 339 | AT91_XDMAC_DT_PERID(11))>; 340 dma-names = "tx", "rx"; 341 pinctrl-names = "default"; 342 pinctrl-0 = <&pinctrl_spi0>; 343 clocks = <&pmc PMC_TYPE_PERIPHERAL 37>; 344 clock-names = "spi_clk"; 345 status = "disabled"; 346 }; 347 348 i2c0: i2c@f8014000 { 349 compatible = "atmel,sama5d4-i2c"; 350 reg = <0xf8014000 0x4000>; 351 interrupts = <32 IRQ_TYPE_LEVEL_HIGH 6>; 352 dmas = <&dma1 353 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) 354 | AT91_XDMAC_DT_PERID(2))>, 355 <&dma1 356 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) 357 | AT91_XDMAC_DT_PERID(3))>; 358 dma-names = "tx", "rx"; 359 pinctrl-names = "default", "gpio"; 360 pinctrl-0 = <&pinctrl_i2c0>; 361 pinctrl-1 = <&pinctrl_i2c0_gpio>; 362 sda-gpios = <&pioA 30 GPIO_ACTIVE_HIGH>; 363 scl-gpios = <&pioA 31 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 364 #address-cells = <1>; 365 #size-cells = <0>; 366 clocks = <&pmc PMC_TYPE_PERIPHERAL 32>; 367 status = "disabled"; 368 }; 369 370 i2c1: i2c@f8018000 { 371 compatible = "atmel,sama5d4-i2c"; 372 reg = <0xf8018000 0x4000>; 373 interrupts = <33 IRQ_TYPE_LEVEL_HIGH 6>; 374 dmas = <&dma0 375 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) 376 | AT91_XDMAC_DT_PERID(4))>, 377 <&dma0 378 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) 379 | AT91_XDMAC_DT_PERID(5))>; 380 dma-names = "tx", "rx"; 381 pinctrl-names = "default", "gpio"; 382 pinctrl-0 = <&pinctrl_i2c1>; 383 pinctrl-1 = <&pinctrl_i2c1_gpio>; 384 sda-gpios = <&pioE 29 GPIO_ACTIVE_HIGH>; 385 scl-gpios = <&pioE 30 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 386 #address-cells = <1>; 387 #size-cells = <0>; 388 clocks = <&pmc PMC_TYPE_PERIPHERAL 33>; 389 status = "disabled"; 390 }; 391 392 tcb0: timer@f801c000 { 393 compatible = "atmel,at91sam9x5-tcb", "simple-mfd", "syscon"; 394 #address-cells = <1>; 395 #size-cells = <0>; 396 reg = <0xf801c000 0x100>; 397 interrupts = <40 IRQ_TYPE_LEVEL_HIGH 0>; 398 clocks = <&pmc PMC_TYPE_PERIPHERAL 40>, <&clk32k>; 399 clock-names = "t0_clk", "slow_clk"; 400 }; 401 402 macb0: ethernet@f8020000 { 403 compatible = "atmel,sama5d4-gem"; 404 reg = <0xf8020000 0x100>; 405 interrupts = <54 IRQ_TYPE_LEVEL_HIGH 3>; 406 pinctrl-names = "default"; 407 pinctrl-0 = <&pinctrl_macb0_rmii>; 408 #address-cells = <1>; 409 #size-cells = <0>; 410 clocks = <&pmc PMC_TYPE_PERIPHERAL 54>, <&pmc PMC_TYPE_PERIPHERAL 54>; 411 clock-names = "hclk", "pclk"; 412 status = "disabled"; 413 }; 414 415 i2c2: i2c@f8024000 { 416 compatible = "atmel,sama5d4-i2c"; 417 reg = <0xf8024000 0x4000>; 418 interrupts = <34 IRQ_TYPE_LEVEL_HIGH 6>; 419 dmas = <&dma1 420 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) 421 | AT91_XDMAC_DT_PERID(6))>, 422 <&dma1 423 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) 424 | AT91_XDMAC_DT_PERID(7))>; 425 dma-names = "tx", "rx"; 426 pinctrl-names = "default", "gpio"; 427 pinctrl-0 = <&pinctrl_i2c2>; 428 pinctrl-1 = <&pinctrl_i2c2_gpio>; 429 sda-gpios = <&pioB 29 GPIO_ACTIVE_HIGH>; 430 scl-gpios = <&pioB 30 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 431 #address-cells = <1>; 432 #size-cells = <0>; 433 clocks = <&pmc PMC_TYPE_PERIPHERAL 34>; 434 status = "disabled"; 435 }; 436 437 sfr: sfr@f8028000 { 438 compatible = "atmel,sama5d4-sfr", "syscon"; 439 reg = <0xf8028000 0x60>; 440 }; 441 442 usart0: serial@f802c000 { 443 compatible = "atmel,at91sam9260-usart"; 444 reg = <0xf802c000 0x100>; 445 atmel,usart-mode = <AT91_USART_MODE_SERIAL>; 446 interrupts = <6 IRQ_TYPE_LEVEL_HIGH 5>; 447 dmas = <&dma0 448 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) 449 | AT91_XDMAC_DT_PERID(36))>, 450 <&dma0 451 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) 452 | AT91_XDMAC_DT_PERID(37))>; 453 dma-names = "tx", "rx"; 454 pinctrl-names = "default"; 455 pinctrl-0 = <&pinctrl_usart0 &pinctrl_usart0_rts &pinctrl_usart0_cts>; 456 clocks = <&pmc PMC_TYPE_PERIPHERAL 6>; 457 clock-names = "usart"; 458 status = "disabled"; 459 }; 460 461 usart1: serial@f8030000 { 462 compatible = "atmel,at91sam9260-usart"; 463 reg = <0xf8030000 0x100>; 464 atmel,usart-mode = <AT91_USART_MODE_SERIAL>; 465 interrupts = <7 IRQ_TYPE_LEVEL_HIGH 5>; 466 dmas = <&dma0 467 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) 468 | AT91_XDMAC_DT_PERID(38))>, 469 <&dma0 470 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) 471 | AT91_XDMAC_DT_PERID(39))>; 472 dma-names = "tx", "rx"; 473 pinctrl-names = "default"; 474 pinctrl-0 = <&pinctrl_usart1 &pinctrl_usart1_rts &pinctrl_usart1_cts>; 475 clocks = <&pmc PMC_TYPE_PERIPHERAL 7>; 476 clock-names = "usart"; 477 status = "disabled"; 478 }; 479 480 mmc1: mmc@fc000000 { 481 compatible = "atmel,hsmci"; 482 reg = <0xfc000000 0x600>; 483 interrupts = <36 IRQ_TYPE_LEVEL_HIGH 0>; 484 dmas = <&dma1 485 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) 486 | AT91_XDMAC_DT_PERID(1))>; 487 dma-names = "rxtx"; 488 pinctrl-names = "default"; 489 pinctrl-0 = <&pinctrl_mmc1_clk_cmd_dat0 &pinctrl_mmc1_dat1_3>; 490 status = "disabled"; 491 #address-cells = <1>; 492 #size-cells = <0>; 493 clocks = <&pmc PMC_TYPE_PERIPHERAL 36>; 494 clock-names = "mci_clk"; 495 }; 496 497 uart1: serial@fc004000 { 498 compatible = "atmel,at91sam9260-usart"; 499 reg = <0xfc004000 0x100>; 500 atmel,usart-mode = <AT91_USART_MODE_SERIAL>; 501 interrupts = <28 IRQ_TYPE_LEVEL_HIGH 5>; 502 dmas = <&dma0 503 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) 504 | AT91_XDMAC_DT_PERID(24))>, 505 <&dma0 506 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) 507 | AT91_XDMAC_DT_PERID(25))>; 508 dma-names = "tx", "rx"; 509 pinctrl-names = "default"; 510 pinctrl-0 = <&pinctrl_uart1>; 511 clocks = <&pmc PMC_TYPE_PERIPHERAL 28>; 512 clock-names = "usart"; 513 status = "disabled"; 514 }; 515 516 usart2: serial@fc008000 { 517 compatible = "atmel,at91sam9260-usart"; 518 reg = <0xfc008000 0x100>; 519 atmel,usart-mode = <AT91_USART_MODE_SERIAL>; 520 interrupts = <29 IRQ_TYPE_LEVEL_HIGH 5>; 521 dmas = <&dma1 522 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) 523 | AT91_XDMAC_DT_PERID(16))>, 524 <&dma1 525 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) 526 | AT91_XDMAC_DT_PERID(17))>; 527 dma-names = "tx", "rx"; 528 pinctrl-names = "default"; 529 pinctrl-0 = <&pinctrl_usart2 &pinctrl_usart2_rts &pinctrl_usart2_cts>; 530 clocks = <&pmc PMC_TYPE_PERIPHERAL 29>; 531 clock-names = "usart"; 532 status = "disabled"; 533 }; 534 535 usart3: serial@fc00c000 { 536 compatible = "atmel,at91sam9260-usart"; 537 reg = <0xfc00c000 0x100>; 538 atmel,usart-mode = <AT91_USART_MODE_SERIAL>; 539 interrupts = <30 IRQ_TYPE_LEVEL_HIGH 5>; 540 dmas = <&dma1 541 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) 542 | AT91_XDMAC_DT_PERID(18))>, 543 <&dma1 544 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) 545 | AT91_XDMAC_DT_PERID(19))>; 546 dma-names = "tx", "rx"; 547 pinctrl-names = "default"; 548 pinctrl-0 = <&pinctrl_usart3>; 549 clocks = <&pmc PMC_TYPE_PERIPHERAL 30>; 550 clock-names = "usart"; 551 status = "disabled"; 552 }; 553 554 usart4: serial@fc010000 { 555 compatible = "atmel,at91sam9260-usart"; 556 reg = <0xfc010000 0x100>; 557 atmel,usart-mode = <AT91_USART_MODE_SERIAL>; 558 interrupts = <31 IRQ_TYPE_LEVEL_HIGH 5>; 559 dmas = <&dma1 560 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) 561 | AT91_XDMAC_DT_PERID(20))>, 562 <&dma1 563 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) 564 | AT91_XDMAC_DT_PERID(21))>; 565 dma-names = "tx", "rx"; 566 pinctrl-names = "default"; 567 pinctrl-0 = <&pinctrl_usart4>; 568 clocks = <&pmc PMC_TYPE_PERIPHERAL 31>; 569 clock-names = "usart"; 570 status = "disabled"; 571 }; 572 573 ssc1: ssc@fc014000 { 574 compatible = "atmel,at91sam9g45-ssc"; 575 reg = <0xfc014000 0x4000>; 576 interrupts = <49 IRQ_TYPE_LEVEL_HIGH 0>; 577 pinctrl-names = "default"; 578 pinctrl-0 = <&pinctrl_ssc1_tx &pinctrl_ssc1_rx>; 579 dmas = <&dma1 580 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) 581 | AT91_XDMAC_DT_PERID(28))>, 582 <&dma1 583 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) 584 | AT91_XDMAC_DT_PERID(29))>; 585 dma-names = "tx", "rx"; 586 clocks = <&pmc PMC_TYPE_PERIPHERAL 49>; 587 clock-names = "pclk"; 588 status = "disabled"; 589 }; 590 591 spi1: spi@fc018000 { 592 #address-cells = <1>; 593 #size-cells = <0>; 594 compatible = "atmel,at91rm9200-spi"; 595 reg = <0xfc018000 0x100>; 596 interrupts = <38 IRQ_TYPE_LEVEL_HIGH 3>; 597 dmas = <&dma1 598 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) 599 | AT91_XDMAC_DT_PERID(12))>, 600 <&dma1 601 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) 602 | AT91_XDMAC_DT_PERID(13))>; 603 dma-names = "tx", "rx"; 604 pinctrl-names = "default"; 605 pinctrl-0 = <&pinctrl_spi1>; 606 clocks = <&pmc PMC_TYPE_PERIPHERAL 38>; 607 clock-names = "spi_clk"; 608 status = "disabled"; 609 }; 610 611 spi2: spi@fc01c000 { 612 #address-cells = <1>; 613 #size-cells = <0>; 614 compatible = "atmel,at91rm9200-spi"; 615 reg = <0xfc01c000 0x100>; 616 interrupts = <39 IRQ_TYPE_LEVEL_HIGH 3>; 617 dmas = <&dma0 618 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) 619 | AT91_XDMAC_DT_PERID(14))>, 620 <&dma0 621 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) 622 | AT91_XDMAC_DT_PERID(15))>; 623 dma-names = "tx", "rx"; 624 pinctrl-names = "default"; 625 pinctrl-0 = <&pinctrl_spi2>; 626 clocks = <&pmc PMC_TYPE_PERIPHERAL 39>; 627 clock-names = "spi_clk"; 628 status = "disabled"; 629 }; 630 631 tcb1: timer@fc020000 { 632 compatible = "atmel,at91sam9x5-tcb", "simple-mfd", "syscon"; 633 #address-cells = <1>; 634 #size-cells = <0>; 635 reg = <0xfc020000 0x100>; 636 interrupts = <41 IRQ_TYPE_LEVEL_HIGH 0>; 637 clocks = <&pmc PMC_TYPE_PERIPHERAL 41>, <&clk32k>; 638 clock-names = "t0_clk", "slow_clk"; 639 }; 640 641 tcb2: timer@fc024000 { 642 compatible = "atmel,at91sam9x5-tcb", "simple-mfd", "syscon"; 643 #address-cells = <1>; 644 #size-cells = <0>; 645 reg = <0xfc024000 0x100>; 646 interrupts = <42 IRQ_TYPE_LEVEL_HIGH 0>; 647 clocks = <&pmc PMC_TYPE_PERIPHERAL 42>, <&clk32k>; 648 clock-names = "t0_clk", "slow_clk"; 649 }; 650 651 macb1: ethernet@fc028000 { 652 compatible = "atmel,sama5d4-gem"; 653 reg = <0xfc028000 0x100>; 654 interrupts = <55 IRQ_TYPE_LEVEL_HIGH 3>; 655 pinctrl-names = "default"; 656 pinctrl-0 = <&pinctrl_macb1_rmii>; 657 #address-cells = <1>; 658 #size-cells = <0>; 659 clocks = <&pmc PMC_TYPE_PERIPHERAL 55>, <&pmc PMC_TYPE_PERIPHERAL 55>; 660 clock-names = "hclk", "pclk"; 661 status = "disabled"; 662 }; 663 664 trng: rng@fc030000 { 665 compatible = "atmel,at91sam9g45-trng"; 666 reg = <0xfc030000 0x100>; 667 interrupts = <53 IRQ_TYPE_LEVEL_HIGH 0>; 668 clocks = <&pmc PMC_TYPE_PERIPHERAL 53>; 669 }; 670 671 adc0: adc@fc034000 { 672 compatible = "atmel,at91sam9x5-adc"; 673 reg = <0xfc034000 0x100>; 674 interrupts = <44 IRQ_TYPE_LEVEL_HIGH 5>; 675 clocks = <&pmc PMC_TYPE_PERIPHERAL 44>, 676 <&adc_op_clk>; 677 clock-names = "adc_clk", "adc_op_clk"; 678 atmel,adc-channels-used = <0x01f>; 679 atmel,adc-startup-time = <40>; 680 atmel,adc-use-external-triggers; 681 atmel,adc-vref = <3000>; 682 atmel,adc-sample-hold-time = <11>; 683 atmel,adc-ts-pressure-threshold = <10000>; 684 status = "disabled"; 685 }; 686 687 aes: crypto@fc044000 { 688 compatible = "atmel,at91sam9g46-aes"; 689 reg = <0xfc044000 0x100>; 690 interrupts = <12 IRQ_TYPE_LEVEL_HIGH 0>; 691 dmas = <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) 692 | AT91_XDMAC_DT_PERID(41))>, 693 <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) 694 | AT91_XDMAC_DT_PERID(40))>; 695 dma-names = "tx", "rx"; 696 clocks = <&pmc PMC_TYPE_PERIPHERAL 12>; 697 clock-names = "aes_clk"; 698 }; 699 700 tdes: crypto@fc04c000 { 701 compatible = "atmel,at91sam9g46-tdes"; 702 reg = <0xfc04c000 0x100>; 703 interrupts = <14 IRQ_TYPE_LEVEL_HIGH 0>; 704 dmas = <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) 705 | AT91_XDMAC_DT_PERID(42))>, 706 <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) 707 | AT91_XDMAC_DT_PERID(43))>; 708 dma-names = "tx", "rx"; 709 clocks = <&pmc PMC_TYPE_PERIPHERAL 14>; 710 clock-names = "tdes_clk"; 711 }; 712 713 sha: crypto@fc050000 { 714 compatible = "atmel,at91sam9g46-sha"; 715 reg = <0xfc050000 0x100>; 716 interrupts = <15 IRQ_TYPE_LEVEL_HIGH 0>; 717 dmas = <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) 718 | AT91_XDMAC_DT_PERID(44))>; 719 dma-names = "tx"; 720 clocks = <&pmc PMC_TYPE_PERIPHERAL 15>; 721 clock-names = "sha_clk"; 722 }; 723 724 hsmc: smc@fc05c000 { 725 compatible = "atmel,sama5d3-smc", "syscon", "simple-mfd"; 726 reg = <0xfc05c000 0x1000>; 727 interrupts = <22 IRQ_TYPE_LEVEL_HIGH 6>; 728 clocks = <&pmc PMC_TYPE_PERIPHERAL 22>; 729 #address-cells = <1>; 730 #size-cells = <1>; 731 ranges; 732 733 pmecc: ecc-engine@ffffc070 { 734 compatible = "atmel,sama5d4-pmecc"; 735 reg = <0xfc05c070 0x490>, 736 <0xfc05c500 0x100>; 737 }; 738 }; 739 740 reset_controller: reset-controller@fc068600 { 741 compatible = "atmel,sama5d3-rstc", "atmel,at91sam9g45-rstc"; 742 reg = <0xfc068600 0x10>; 743 clocks = <&clk32k>; 744 }; 745 746 shutdown_controller: poweroff@fc068610 { 747 compatible = "atmel,at91sam9x5-shdwc"; 748 reg = <0xfc068610 0x10>; 749 clocks = <&clk32k>; 750 }; 751 752 pit: timer@fc068630 { 753 compatible = "atmel,at91sam9260-pit"; 754 reg = <0xfc068630 0x10>; 755 interrupts = <3 IRQ_TYPE_LEVEL_HIGH 5>; 756 clocks = <&pmc PMC_TYPE_CORE PMC_MCK2>; 757 }; 758 759 watchdog: watchdog@fc068640 { 760 compatible = "atmel,sama5d4-wdt"; 761 reg = <0xfc068640 0x10>; 762 interrupts = <4 IRQ_TYPE_LEVEL_HIGH 7>; 763 clocks = <&clk32k>; 764 status = "disabled"; 765 }; 766 767 clk32k: clock-controller@fc068650 { 768 compatible = "atmel,sama5d4-sckc"; 769 reg = <0xfc068650 0x4>; 770 #clock-cells = <0>; 771 clocks = <&slow_xtal>; 772 }; 773 774 rtc@fc0686b0 { 775 compatible = "atmel,sama5d4-rtc"; 776 reg = <0xfc0686b0 0x30>; 777 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; 778 clocks = <&clk32k>; 779 }; 780 781 dbgu: serial@fc069000 { 782 compatible = "atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart"; 783 reg = <0xfc069000 0x200>; 784 atmel,usart-mode = <AT91_USART_MODE_SERIAL>; 785 interrupts = <45 IRQ_TYPE_LEVEL_HIGH 7>; 786 pinctrl-names = "default"; 787 pinctrl-0 = <&pinctrl_dbgu>; 788 clocks = <&pmc PMC_TYPE_PERIPHERAL 45>; 789 clock-names = "usart"; 790 status = "disabled"; 791 }; 792 793 794 pinctrl: pinctrl@fc06a000 { 795 #address-cells = <1>; 796 #size-cells = <1>; 797 compatible = "atmel,sama5d3-pinctrl", "simple-mfd"; 798 ranges = <0xfc068000 0xfc068000 0x100 799 0xfc06a000 0xfc06a000 0x4000>; 800 /* WARNING: revisit as pin spec has changed */ 801 atmel,mux-mask = < 802 /* A B C */ 803 0xffffffff 0x3ffcfe7c 0x1c010101 /* pioA */ 804 0x7fffffff 0xfffccc3a 0x3f00cc3a /* pioB */ 805 0xffffffff 0x3ff83fff 0xff00ffff /* pioC */ 806 0xb003ff00 0x8002a800 0x00000000 /* pioD */ 807 0xffffffff 0x7fffffff 0x76fff1bf /* pioE */ 808 >; 809 810 pioA: gpio@fc06a000 { 811 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; 812 reg = <0xfc06a000 0x100>; 813 interrupts = <23 IRQ_TYPE_LEVEL_HIGH 1>; 814 #gpio-cells = <2>; 815 gpio-controller; 816 interrupt-controller; 817 #interrupt-cells = <2>; 818 clocks = <&pmc PMC_TYPE_PERIPHERAL 23>; 819 }; 820 821 pioB: gpio@fc06b000 { 822 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; 823 reg = <0xfc06b000 0x100>; 824 interrupts = <24 IRQ_TYPE_LEVEL_HIGH 1>; 825 #gpio-cells = <2>; 826 gpio-controller; 827 interrupt-controller; 828 #interrupt-cells = <2>; 829 clocks = <&pmc PMC_TYPE_PERIPHERAL 24>; 830 }; 831 832 pioC: gpio@fc06c000 { 833 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; 834 reg = <0xfc06c000 0x100>; 835 interrupts = <25 IRQ_TYPE_LEVEL_HIGH 1>; 836 #gpio-cells = <2>; 837 gpio-controller; 838 interrupt-controller; 839 #interrupt-cells = <2>; 840 clocks = <&pmc PMC_TYPE_PERIPHERAL 25>; 841 }; 842 843 pioD: gpio@fc068000 { 844 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; 845 reg = <0xfc068000 0x100>; 846 interrupts = <5 IRQ_TYPE_LEVEL_HIGH 1>; 847 #gpio-cells = <2>; 848 gpio-controller; 849 interrupt-controller; 850 #interrupt-cells = <2>; 851 clocks = <&pmc PMC_TYPE_PERIPHERAL 5>; 852 }; 853 854 pioE: gpio@fc06d000 { 855 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; 856 reg = <0xfc06d000 0x100>; 857 interrupts = <26 IRQ_TYPE_LEVEL_HIGH 1>; 858 #gpio-cells = <2>; 859 gpio-controller; 860 interrupt-controller; 861 #interrupt-cells = <2>; 862 clocks = <&pmc PMC_TYPE_PERIPHERAL 26>; 863 }; 864 865 /* pinctrl pin settings */ 866 adc0 { 867 pinctrl_adc0_adtrg: adc0_adtrg { 868 atmel,pins = 869 <AT91_PIOE 31 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* conflicts with USBA_VBUS */ 870 }; 871 pinctrl_adc0_ad0: adc0_ad0 { 872 atmel,pins = 873 <AT91_PIOC 27 AT91_PERIPH_A AT91_PINCTRL_NONE>; 874 }; 875 pinctrl_adc0_ad1: adc0_ad1 { 876 atmel,pins = 877 <AT91_PIOC 28 AT91_PERIPH_A AT91_PINCTRL_NONE>; 878 }; 879 pinctrl_adc0_ad2: adc0_ad2 { 880 atmel,pins = 881 <AT91_PIOC 29 AT91_PERIPH_A AT91_PINCTRL_NONE>; 882 }; 883 pinctrl_adc0_ad3: adc0_ad3 { 884 atmel,pins = 885 <AT91_PIOC 30 AT91_PERIPH_A AT91_PINCTRL_NONE>; 886 }; 887 pinctrl_adc0_ad4: adc0_ad4 { 888 atmel,pins = 889 <AT91_PIOC 31 AT91_PERIPH_A AT91_PINCTRL_NONE>; 890 }; 891 }; 892 893 dbgu { 894 pinctrl_dbgu: dbgu-0 { 895 atmel,pins = 896 <AT91_PIOB 24 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* conflicts with D14 and TDI */ 897 AT91_PIOB 25 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* conflicts with D15 and TDO */ 898 }; 899 }; 900 901 ebi { 902 pinctrl_ebi_addr: ebi-addr-0 { 903 atmel,pins = 904 <AT91_PIOE 0 AT91_PERIPH_A AT91_PINCTRL_NONE 905 AT91_PIOE 1 AT91_PERIPH_A AT91_PINCTRL_NONE 906 AT91_PIOE 2 AT91_PERIPH_A AT91_PINCTRL_NONE 907 AT91_PIOE 3 AT91_PERIPH_A AT91_PINCTRL_NONE 908 AT91_PIOE 4 AT91_PERIPH_A AT91_PINCTRL_NONE 909 AT91_PIOE 5 AT91_PERIPH_A AT91_PINCTRL_NONE 910 AT91_PIOE 6 AT91_PERIPH_A AT91_PINCTRL_NONE 911 AT91_PIOE 7 AT91_PERIPH_A AT91_PINCTRL_NONE 912 AT91_PIOE 8 AT91_PERIPH_A AT91_PINCTRL_NONE 913 AT91_PIOE 9 AT91_PERIPH_A AT91_PINCTRL_NONE 914 AT91_PIOE 10 AT91_PERIPH_A AT91_PINCTRL_NONE 915 AT91_PIOE 11 AT91_PERIPH_A AT91_PINCTRL_NONE 916 AT91_PIOE 12 AT91_PERIPH_A AT91_PINCTRL_NONE 917 AT91_PIOE 13 AT91_PERIPH_A AT91_PINCTRL_NONE 918 AT91_PIOE 14 AT91_PERIPH_A AT91_PINCTRL_NONE 919 AT91_PIOE 15 AT91_PERIPH_A AT91_PINCTRL_NONE 920 AT91_PIOE 16 AT91_PERIPH_A AT91_PINCTRL_NONE 921 AT91_PIOE 17 AT91_PERIPH_A AT91_PINCTRL_NONE 922 AT91_PIOE 18 AT91_PERIPH_A AT91_PINCTRL_NONE 923 AT91_PIOE 19 AT91_PERIPH_A AT91_PINCTRL_NONE 924 AT91_PIOE 20 AT91_PERIPH_A AT91_PINCTRL_NONE 925 AT91_PIOC 17 AT91_PERIPH_A AT91_PINCTRL_NONE 926 AT91_PIOC 18 AT91_PERIPH_A AT91_PINCTRL_NONE 927 AT91_PIOE 21 AT91_PERIPH_A AT91_PINCTRL_NONE 928 AT91_PIOE 22 AT91_PERIPH_A AT91_PINCTRL_NONE 929 AT91_PIOE 23 AT91_PERIPH_A AT91_PINCTRL_NONE>; 930 }; 931 932 pinctrl_ebi_nand_addr: ebi-addr-1 { 933 atmel,pins = 934 <AT91_PIOC 17 AT91_PERIPH_A AT91_PINCTRL_NONE 935 AT91_PIOC 18 AT91_PERIPH_A AT91_PINCTRL_NONE>; 936 }; 937 938 pinctrl_ebi_cs0: ebi-cs0-0 { 939 atmel,pins = 940 <AT91_PIOE 26 AT91_PERIPH_A AT91_PINCTRL_NONE>; 941 }; 942 943 pinctrl_ebi_cs1: ebi-cs1-0 { 944 atmel,pins = 945 <AT91_PIOE 27 AT91_PERIPH_A AT91_PINCTRL_NONE>; 946 }; 947 948 pinctrl_ebi_cs2: ebi-cs2-0 { 949 atmel,pins = 950 <AT91_PIOE 28 AT91_PERIPH_A AT91_PINCTRL_NONE>; 951 }; 952 953 pinctrl_ebi_cs3: ebi-cs3-0 { 954 atmel,pins = 955 <AT91_PIOC 15 AT91_PERIPH_A AT91_PINCTRL_NONE>; 956 }; 957 958 pinctrl_ebi_data_0_7: ebi-data-lsb-0 { 959 atmel,pins = 960 <AT91_PIOC 5 AT91_PERIPH_A AT91_PINCTRL_NONE 961 AT91_PIOC 6 AT91_PERIPH_A AT91_PINCTRL_NONE 962 AT91_PIOC 7 AT91_PERIPH_A AT91_PINCTRL_NONE 963 AT91_PIOC 8 AT91_PERIPH_A AT91_PINCTRL_NONE 964 AT91_PIOC 9 AT91_PERIPH_A AT91_PINCTRL_NONE 965 AT91_PIOC 10 AT91_PERIPH_A AT91_PINCTRL_NONE 966 AT91_PIOC 11 AT91_PERIPH_A AT91_PINCTRL_NONE 967 AT91_PIOC 12 AT91_PERIPH_A AT91_PINCTRL_NONE>; 968 }; 969 970 pinctrl_ebi_data_8_15: ebi-data-msb-0 { 971 atmel,pins = 972 <AT91_PIOB 18 AT91_PERIPH_B AT91_PINCTRL_NONE 973 AT91_PIOB 19 AT91_PERIPH_B AT91_PINCTRL_NONE 974 AT91_PIOB 20 AT91_PERIPH_B AT91_PINCTRL_NONE 975 AT91_PIOB 21 AT91_PERIPH_B AT91_PINCTRL_NONE 976 AT91_PIOB 22 AT91_PERIPH_B AT91_PINCTRL_NONE 977 AT91_PIOB 23 AT91_PERIPH_B AT91_PINCTRL_NONE 978 AT91_PIOB 24 AT91_PERIPH_B AT91_PINCTRL_NONE 979 AT91_PIOB 25 AT91_PERIPH_B AT91_PINCTRL_NONE>; 980 }; 981 982 pinctrl_ebi_nandrdy: ebi-nandrdy-0 { 983 atmel,pins = 984 <AT91_PIOC 16 AT91_PERIPH_A AT91_PINCTRL_NONE>; 985 }; 986 987 pinctrl_ebi_nrd_nandoe: ebi-nrd-nandoe-0 { 988 atmel,pins = 989 <AT91_PIOC 13 AT91_PERIPH_A AT91_PINCTRL_NONE>; 990 }; 991 992 pinctrl_ebi_nwait: ebi-nwait-0 { 993 atmel,pins = 994 <AT91_PIOE 30 AT91_PERIPH_A AT91_PINCTRL_NONE>; 995 }; 996 997 pinctrl_ebi_nwe_nandwe: ebi-nwe-nandwe-0 { 998 atmel,pins = 999 <AT91_PIOC 14 AT91_PERIPH_A AT91_PINCTRL_NONE>; 1000 }; 1001 1002 pinctrl_ebi_nwr1_nbs1: ebi-nwr1-nbs1-0 { 1003 atmel,pins = 1004 <AT91_PIOE 29 AT91_PERIPH_A AT91_PINCTRL_NONE>; 1005 }; 1006 }; 1007 1008 i2c0 { 1009 pinctrl_i2c0: i2c0-0 { 1010 atmel,pins = 1011 <AT91_PIOA 30 AT91_PERIPH_A AT91_PINCTRL_NONE 1012 AT91_PIOA 31 AT91_PERIPH_A AT91_PINCTRL_NONE>; 1013 }; 1014 1015 pinctrl_i2c0_gpio: i2c0-gpio { 1016 atmel,pins = 1017 <AT91_PIOA 30 AT91_PERIPH_GPIO AT91_PINCTRL_NONE 1018 AT91_PIOA 31 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>; 1019 }; 1020 }; 1021 1022 i2c1 { 1023 pinctrl_i2c1: i2c1-0 { 1024 atmel,pins = 1025 <AT91_PIOE 29 AT91_PERIPH_C AT91_PINCTRL_NONE /* TWD1, conflicts with UART0 RX and DIBP */ 1026 AT91_PIOE 30 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* TWCK1, conflicts with UART0 TX and DIBN */ 1027 }; 1028 1029 pinctrl_i2c1_gpio: i2c1-gpio { 1030 atmel,pins = 1031 <AT91_PIOE 29 AT91_PERIPH_GPIO AT91_PINCTRL_NONE 1032 AT91_PIOE 30 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>; 1033 }; 1034 }; 1035 1036 i2c2 { 1037 pinctrl_i2c2: i2c2-0 { 1038 atmel,pins = 1039 <AT91_PIOB 29 AT91_PERIPH_A AT91_PINCTRL_NONE /* TWD2, conflicts with RD0 and PWML1 */ 1040 AT91_PIOB 30 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* TWCK2, conflicts with RF0 */ 1041 }; 1042 1043 pinctrl_i2c2_gpio: i2c2-gpio { 1044 atmel,pins = 1045 <AT91_PIOB 29 AT91_PERIPH_GPIO AT91_PINCTRL_NONE 1046 AT91_PIOB 30 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>; 1047 }; 1048 }; 1049 1050 isi { 1051 pinctrl_isi_data_0_7: isi-0-data-0-7 { 1052 atmel,pins = 1053 <AT91_PIOC 19 AT91_PERIPH_A AT91_PINCTRL_NONE /* ISI_D0 */ 1054 AT91_PIOC 20 AT91_PERIPH_A AT91_PINCTRL_NONE /* ISI_D1 */ 1055 AT91_PIOC 21 AT91_PERIPH_A AT91_PINCTRL_NONE /* ISI_D2 */ 1056 AT91_PIOC 22 AT91_PERIPH_A AT91_PINCTRL_NONE /* ISI_D3 */ 1057 AT91_PIOC 23 AT91_PERIPH_A AT91_PINCTRL_NONE /* ISI_D4 */ 1058 AT91_PIOC 24 AT91_PERIPH_A AT91_PINCTRL_NONE /* ISI_D5 */ 1059 AT91_PIOC 25 AT91_PERIPH_A AT91_PINCTRL_NONE /* ISI_D6 */ 1060 AT91_PIOC 26 AT91_PERIPH_A AT91_PINCTRL_NONE /* ISI_D7 */ 1061 AT91_PIOB 1 AT91_PERIPH_C AT91_PINCTRL_NONE /* ISI_PCK, conflict with G0_RXCK */ 1062 AT91_PIOB 3 AT91_PERIPH_C AT91_PINCTRL_NONE /* ISI_VSYNC */ 1063 AT91_PIOB 4 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* ISI_HSYNC */ 1064 }; 1065 pinctrl_isi_data_8_9: isi-0-data-8-9 { 1066 atmel,pins = 1067 <AT91_PIOC 0 AT91_PERIPH_C AT91_PINCTRL_NONE /* ISI_D8, conflicts with SPI0_MISO, PWMH2 */ 1068 AT91_PIOC 1 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* ISI_D9, conflicts with SPI0_MOSI, PWML2 */ 1069 }; 1070 pinctrl_isi_data_10_11: isi-0-data-10-11 { 1071 atmel,pins = 1072 <AT91_PIOC 2 AT91_PERIPH_C AT91_PINCTRL_NONE /* ISI_D10, conflicts with SPI0_SPCK, PWMH3 */ 1073 AT91_PIOC 3 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* ISI_D11, conflicts with SPI0_NPCS0, PWML3 */ 1074 }; 1075 }; 1076 1077 lcd { 1078 pinctrl_lcd_base: lcd-base-0 { 1079 atmel,pins = 1080 <AT91_PIOA 26 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDVSYNC */ 1081 AT91_PIOA 27 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDHSYNC */ 1082 AT91_PIOA 29 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDDEN */ 1083 AT91_PIOA 28 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* LCDPCK */ 1084 }; 1085 pinctrl_lcd_pwm: lcd-pwm-0 { 1086 atmel,pins = <AT91_PIOA 24 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* LCDPWM */ 1087 }; 1088 pinctrl_lcd_rgb444: lcd-rgb-0 { 1089 atmel,pins = 1090 <AT91_PIOA 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD0 pin */ 1091 AT91_PIOA 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD1 pin */ 1092 AT91_PIOA 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD2 pin */ 1093 AT91_PIOA 3 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD3 pin */ 1094 AT91_PIOA 4 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD4 pin */ 1095 AT91_PIOA 5 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD5 pin */ 1096 AT91_PIOA 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD6 pin */ 1097 AT91_PIOA 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD7 pin */ 1098 AT91_PIOA 8 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD8 pin */ 1099 AT91_PIOA 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD9 pin */ 1100 AT91_PIOA 10 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD10 pin */ 1101 AT91_PIOA 11 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* LCDD11 pin */ 1102 }; 1103 pinctrl_lcd_rgb565: lcd-rgb-1 { 1104 atmel,pins = 1105 <AT91_PIOA 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD0 pin */ 1106 AT91_PIOA 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD1 pin */ 1107 AT91_PIOA 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD2 pin */ 1108 AT91_PIOA 3 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD3 pin */ 1109 AT91_PIOA 4 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD4 pin */ 1110 AT91_PIOA 5 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD5 pin */ 1111 AT91_PIOA 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD6 pin */ 1112 AT91_PIOA 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD7 pin */ 1113 AT91_PIOA 8 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD8 pin */ 1114 AT91_PIOA 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD9 pin */ 1115 AT91_PIOA 10 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD10 pin */ 1116 AT91_PIOA 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD11 pin */ 1117 AT91_PIOA 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD12 pin */ 1118 AT91_PIOA 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD13 pin */ 1119 AT91_PIOA 14 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD14 pin */ 1120 AT91_PIOA 15 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* LCDD15 pin */ 1121 }; 1122 pinctrl_lcd_rgb666: lcd-rgb-2 { 1123 atmel,pins = 1124 <AT91_PIOA 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD2 pin */ 1125 AT91_PIOA 3 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD3 pin */ 1126 AT91_PIOA 4 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD4 pin */ 1127 AT91_PIOA 5 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD5 pin */ 1128 AT91_PIOA 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD6 pin */ 1129 AT91_PIOA 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD7 pin */ 1130 AT91_PIOA 10 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD10 pin */ 1131 AT91_PIOA 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD11 pin */ 1132 AT91_PIOA 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD12 pin */ 1133 AT91_PIOA 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD13 pin */ 1134 AT91_PIOA 14 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD14 pin */ 1135 AT91_PIOA 15 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD15 pin */ 1136 AT91_PIOA 18 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD18 pin */ 1137 AT91_PIOA 19 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD19 pin */ 1138 AT91_PIOA 20 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD20 pin */ 1139 AT91_PIOA 21 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD21 pin */ 1140 AT91_PIOA 22 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD22 pin */ 1141 AT91_PIOA 23 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* LCDD23 pin */ 1142 }; 1143 pinctrl_lcd_rgb777: lcd-rgb-3 { 1144 atmel,pins = 1145 /* LCDDAT0 conflicts with TMS */ 1146 <AT91_PIOA 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD1 pin */ 1147 AT91_PIOA 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD2 pin */ 1148 AT91_PIOA 3 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD3 pin */ 1149 AT91_PIOA 4 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD4 pin */ 1150 AT91_PIOA 5 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD5 pin */ 1151 AT91_PIOA 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD6 pin */ 1152 AT91_PIOA 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD7 pin */ 1153 /* LCDDAT8 conflicts with TCK */ 1154 AT91_PIOA 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD9 pin */ 1155 AT91_PIOA 10 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD10 pin */ 1156 AT91_PIOA 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD11 pin */ 1157 AT91_PIOA 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD12 pin */ 1158 AT91_PIOA 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD13 pin */ 1159 AT91_PIOA 14 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD14 pin */ 1160 AT91_PIOA 15 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD15 pin */ 1161 /* LCDDAT16 conflicts with NTRST */ 1162 AT91_PIOA 17 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD17 pin */ 1163 AT91_PIOA 18 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD18 pin */ 1164 AT91_PIOA 19 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD19 pin */ 1165 AT91_PIOA 20 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD20 pin */ 1166 AT91_PIOA 21 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD21 pin */ 1167 AT91_PIOA 22 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD22 pin */ 1168 AT91_PIOA 23 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* LCDD23 pin */ 1169 }; 1170 pinctrl_lcd_rgb888: lcd-rgb-4 { 1171 atmel,pins = 1172 <AT91_PIOA 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD0 pin */ 1173 AT91_PIOA 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD1 pin */ 1174 AT91_PIOA 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD2 pin */ 1175 AT91_PIOA 3 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD3 pin */ 1176 AT91_PIOA 4 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD4 pin */ 1177 AT91_PIOA 5 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD5 pin */ 1178 AT91_PIOA 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD6 pin */ 1179 AT91_PIOA 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD7 pin */ 1180 AT91_PIOA 8 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD8 pin */ 1181 AT91_PIOA 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD9 pin */ 1182 AT91_PIOA 10 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD10 pin */ 1183 AT91_PIOA 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD11 pin */ 1184 AT91_PIOA 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD12 pin */ 1185 AT91_PIOA 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD13 pin */ 1186 AT91_PIOA 14 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD14 pin */ 1187 AT91_PIOA 15 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD15 pin */ 1188 AT91_PIOA 16 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD16 pin */ 1189 AT91_PIOA 17 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD17 pin */ 1190 AT91_PIOA 18 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD18 pin */ 1191 AT91_PIOA 19 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD19 pin */ 1192 AT91_PIOA 20 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD20 pin */ 1193 AT91_PIOA 21 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD21 pin */ 1194 AT91_PIOA 22 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD22 pin */ 1195 AT91_PIOA 23 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* LCDD23 pin */ 1196 }; 1197 }; 1198 1199 macb0 { 1200 pinctrl_macb0_rmii: macb0_rmii-0 { 1201 atmel,pins = 1202 <AT91_PIOB 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* G0_TX0 */ 1203 AT91_PIOB 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* G0_TX1 */ 1204 AT91_PIOB 8 AT91_PERIPH_A AT91_PINCTRL_NONE /* G0_RX0 */ 1205 AT91_PIOB 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* G0_RX1 */ 1206 AT91_PIOB 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* G0_RXDV */ 1207 AT91_PIOB 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* G0_RXER */ 1208 AT91_PIOB 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* G0_TXEN */ 1209 AT91_PIOB 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* G0_TXCK */ 1210 AT91_PIOB 16 AT91_PERIPH_A AT91_PINCTRL_NONE /* G0_MDC */ 1211 AT91_PIOB 17 AT91_PERIPH_A AT91_PINCTRL_NONE /* G0_MDIO */ 1212 >; 1213 }; 1214 }; 1215 1216 macb1 { 1217 pinctrl_macb1_rmii: macb1_rmii-0 { 1218 atmel,pins = 1219 <AT91_PIOA 14 AT91_PERIPH_B AT91_PINCTRL_NONE /* G1_TX0 */ 1220 AT91_PIOA 15 AT91_PERIPH_B AT91_PINCTRL_NONE /* G1_TX1 */ 1221 AT91_PIOA 12 AT91_PERIPH_B AT91_PINCTRL_NONE /* G1_RX0 */ 1222 AT91_PIOA 13 AT91_PERIPH_B AT91_PINCTRL_NONE /* G1_RX1 */ 1223 AT91_PIOA 10 AT91_PERIPH_B AT91_PINCTRL_NONE /* G1_RXDV */ 1224 AT91_PIOA 11 AT91_PERIPH_B AT91_PINCTRL_NONE /* G1_RXER */ 1225 AT91_PIOA 4 AT91_PERIPH_B AT91_PINCTRL_NONE /* G1_TXEN */ 1226 AT91_PIOA 2 AT91_PERIPH_B AT91_PINCTRL_NONE /* G1_TXCK */ 1227 AT91_PIOA 22 AT91_PERIPH_B AT91_PINCTRL_NONE /* G1_MDC */ 1228 AT91_PIOA 23 AT91_PERIPH_B AT91_PINCTRL_NONE /* G1_MDIO */ 1229 >; 1230 }; 1231 }; 1232 1233 mmc0 { 1234 pinctrl_mmc0_clk_cmd_dat0: mmc0_clk_cmd_dat0 { 1235 atmel,pins = 1236 <AT91_PIOC 4 AT91_PERIPH_B AT91_PINCTRL_NONE /* MCI0_CK, conflict with PCK1(ISI_MCK) */ 1237 AT91_PIOC 5 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* MCI0_CDA, conflict with NAND_D0 */ 1238 AT91_PIOC 6 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* MCI0_DA0, conflict with NAND_D1 */ 1239 >; 1240 }; 1241 pinctrl_mmc0_dat1_3: mmc0_dat1_3 { 1242 atmel,pins = 1243 <AT91_PIOC 7 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* MCI0_DA1, conflict with NAND_D2 */ 1244 AT91_PIOC 8 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* MCI0_DA2, conflict with NAND_D3 */ 1245 AT91_PIOC 9 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* MCI0_DA3, conflict with NAND_D4 */ 1246 >; 1247 }; 1248 pinctrl_mmc0_dat4_7: mmc0_dat4_7 { 1249 atmel,pins = 1250 <AT91_PIOC 10 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* MCI0_DA4, conflict with NAND_D5 */ 1251 AT91_PIOC 11 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* MCI0_DA5, conflict with NAND_D6 */ 1252 AT91_PIOC 12 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* MCI0_DA6, conflict with NAND_D7 */ 1253 AT91_PIOC 13 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* MCI0_DA7, conflict with NAND_OE */ 1254 >; 1255 }; 1256 }; 1257 1258 mmc1 { 1259 pinctrl_mmc1_clk_cmd_dat0: mmc1_clk_cmd_dat0 { 1260 atmel,pins = 1261 <AT91_PIOE 18 AT91_PERIPH_C AT91_PINCTRL_NONE /* MCI1_CK */ 1262 AT91_PIOE 19 AT91_PERIPH_C AT91_PINCTRL_PULL_UP /* MCI1_CDA */ 1263 AT91_PIOE 20 AT91_PERIPH_C AT91_PINCTRL_PULL_UP /* MCI1_DA0 */ 1264 >; 1265 }; 1266 pinctrl_mmc1_dat1_3: mmc1_dat1_3 { 1267 atmel,pins = 1268 <AT91_PIOE 21 AT91_PERIPH_C AT91_PINCTRL_PULL_UP /* MCI1_DA1 */ 1269 AT91_PIOE 22 AT91_PERIPH_C AT91_PINCTRL_PULL_UP /* MCI1_DA2 */ 1270 AT91_PIOE 23 AT91_PERIPH_C AT91_PINCTRL_PULL_UP /* MCI1_DA3 */ 1271 >; 1272 }; 1273 }; 1274 1275 nand0 { 1276 pinctrl_nand: nand-0 { 1277 atmel,pins = 1278 <AT91_PIOC 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC13 periph A Read Enable */ 1279 AT91_PIOC 14 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC14 periph A Write Enable */ 1280 1281 AT91_PIOC 17 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PC17 ALE */ 1282 AT91_PIOC 18 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PC18 CLE */ 1283 1284 AT91_PIOC 15 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PC15 NCS3/Chip Enable */ 1285 AT91_PIOC 16 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PC16 NANDRDY */ 1286 AT91_PIOC 5 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC5 Data bit 0 */ 1287 AT91_PIOC 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC6 Data bit 1 */ 1288 AT91_PIOC 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC7 Data bit 2 */ 1289 AT91_PIOC 8 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC8 Data bit 3 */ 1290 AT91_PIOC 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC9 Data bit 4 */ 1291 AT91_PIOC 10 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC10 Data bit 5 */ 1292 AT91_PIOC 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC11 periph A Data bit 6 */ 1293 AT91_PIOC 12 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PC12 periph A Data bit 7 */ 1294 }; 1295 }; 1296 1297 spi0 { 1298 pinctrl_spi0: spi0-0 { 1299 atmel,pins = 1300 <AT91_PIOC 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* SPI0_MISO */ 1301 AT91_PIOC 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* SPI0_MOSI */ 1302 AT91_PIOC 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* SPI0_SPCK */ 1303 >; 1304 }; 1305 }; 1306 1307 ssc0 { 1308 pinctrl_ssc0_tx: ssc0_tx { 1309 atmel,pins = 1310 <AT91_PIOB 27 AT91_PERIPH_B AT91_PINCTRL_NONE /* TK0 */ 1311 AT91_PIOB 31 AT91_PERIPH_B AT91_PINCTRL_NONE /* TF0 */ 1312 AT91_PIOB 28 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* TD0 */ 1313 }; 1314 1315 pinctrl_ssc0_rx: ssc0_rx { 1316 atmel,pins = 1317 <AT91_PIOB 26 AT91_PERIPH_B AT91_PINCTRL_NONE /* RK0 */ 1318 AT91_PIOB 30 AT91_PERIPH_B AT91_PINCTRL_NONE /* RF0 */ 1319 AT91_PIOB 29 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* RD0 */ 1320 }; 1321 }; 1322 1323 ssc1 { 1324 pinctrl_ssc1_tx: ssc1_tx { 1325 atmel,pins = 1326 <AT91_PIOC 19 AT91_PERIPH_B AT91_PINCTRL_NONE /* TK1 */ 1327 AT91_PIOC 20 AT91_PERIPH_B AT91_PINCTRL_NONE /* TF1 */ 1328 AT91_PIOC 21 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* TD1 */ 1329 }; 1330 1331 pinctrl_ssc1_rx: ssc1_rx { 1332 atmel,pins = 1333 <AT91_PIOC 24 AT91_PERIPH_B AT91_PINCTRL_NONE /* RK1 */ 1334 AT91_PIOC 22 AT91_PERIPH_B AT91_PINCTRL_NONE /* RF1 */ 1335 AT91_PIOC 23 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* RD1 */ 1336 }; 1337 }; 1338 1339 spi1 { 1340 pinctrl_spi1: spi1-0 { 1341 atmel,pins = 1342 <AT91_PIOB 18 AT91_PERIPH_A AT91_PINCTRL_NONE /* SPI1_MISO */ 1343 AT91_PIOB 19 AT91_PERIPH_A AT91_PINCTRL_NONE /* SPI1_MOSI */ 1344 AT91_PIOB 20 AT91_PERIPH_A AT91_PINCTRL_NONE /* SPI1_SPCK */ 1345 >; 1346 }; 1347 }; 1348 1349 spi2 { 1350 pinctrl_spi2: spi2-0 { 1351 atmel,pins = 1352 <AT91_PIOD 11 AT91_PERIPH_B AT91_PINCTRL_NONE /* SPI2_MISO conflicts with RTS0 */ 1353 AT91_PIOD 13 AT91_PERIPH_B AT91_PINCTRL_NONE /* SPI2_MOSI conflicts with TXD0 */ 1354 AT91_PIOD 15 AT91_PERIPH_B AT91_PINCTRL_NONE /* SPI2_SPCK conflicts with RTS1 */ 1355 >; 1356 }; 1357 }; 1358 1359 uart0 { 1360 pinctrl_uart0: uart0-0 { 1361 atmel,pins = 1362 <AT91_PIOE 29 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* RXD */ 1363 AT91_PIOE 30 AT91_PERIPH_B AT91_PINCTRL_NONE /* TXD */ 1364 >; 1365 }; 1366 }; 1367 1368 uart1 { 1369 pinctrl_uart1: uart1-0 { 1370 atmel,pins = 1371 <AT91_PIOC 25 AT91_PERIPH_C AT91_PINCTRL_PULL_UP /* RXD */ 1372 AT91_PIOC 26 AT91_PERIPH_C AT91_PINCTRL_NONE /* TXD */ 1373 >; 1374 }; 1375 }; 1376 1377 usart0 { 1378 pinctrl_usart0: usart0-0 { 1379 atmel,pins = 1380 <AT91_PIOD 12 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* RXD */ 1381 AT91_PIOD 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* TXD */ 1382 >; 1383 }; 1384 pinctrl_usart0_rts: usart0_rts-0 { 1385 atmel,pins = <AT91_PIOD 11 AT91_PERIPH_A AT91_PINCTRL_NONE>; 1386 }; 1387 pinctrl_usart0_cts: usart0_cts-0 { 1388 atmel,pins = <AT91_PIOD 10 AT91_PERIPH_A AT91_PINCTRL_NONE>; 1389 }; 1390 }; 1391 1392 usart1 { 1393 pinctrl_usart1: usart1-0 { 1394 atmel,pins = 1395 <AT91_PIOD 16 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* RXD */ 1396 AT91_PIOD 17 AT91_PERIPH_A AT91_PINCTRL_NONE /* TXD */ 1397 >; 1398 }; 1399 pinctrl_usart1_rts: usart1_rts-0 { 1400 atmel,pins = <AT91_PIOD 15 AT91_PERIPH_A AT91_PINCTRL_NONE>; 1401 }; 1402 pinctrl_usart1_cts: usart1_cts-0 { 1403 atmel,pins = <AT91_PIOD 14 AT91_PERIPH_A AT91_PINCTRL_NONE>; 1404 }; 1405 }; 1406 1407 usart2 { 1408 pinctrl_usart2: usart2-0 { 1409 atmel,pins = 1410 <AT91_PIOB 4 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* RXD - conflicts with G0_CRS, ISI_HSYNC */ 1411 AT91_PIOB 5 AT91_PERIPH_B AT91_PINCTRL_NONE /* TXD - conflicts with G0_COL, PCK2 */ 1412 >; 1413 }; 1414 pinctrl_usart2_rts: usart2_rts-0 { 1415 atmel,pins = <AT91_PIOB 11 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* conflicts with G0_RX3, PWMH1 */ 1416 }; 1417 pinctrl_usart2_cts: usart2_cts-0 { 1418 atmel,pins = <AT91_PIOB 3 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* conflicts with G0_TXER, ISI_VSYNC */ 1419 }; 1420 }; 1421 1422 usart3 { 1423 pinctrl_usart3: usart3-0 { 1424 atmel,pins = 1425 <AT91_PIOE 16 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* RXD */ 1426 AT91_PIOE 17 AT91_PERIPH_B AT91_PINCTRL_NONE /* TXD */ 1427 >; 1428 }; 1429 }; 1430 1431 usart4 { 1432 pinctrl_usart4: usart4-0 { 1433 atmel,pins = 1434 <AT91_PIOE 26 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* RXD */ 1435 AT91_PIOE 27 AT91_PERIPH_B AT91_PINCTRL_NONE /* TXD */ 1436 >; 1437 }; 1438 pinctrl_usart4_rts: usart4_rts-0 { 1439 atmel,pins = <AT91_PIOE 28 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* conflicts with NWAIT, A19 */ 1440 }; 1441 pinctrl_usart4_cts: usart4_cts-0 { 1442 atmel,pins = <AT91_PIOE 0 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* conflicts with A0/NBS0, MCI0_CDB */ 1443 }; 1444 }; 1445 }; 1446 1447 aic: interrupt-controller@fc06e000 { 1448 #interrupt-cells = <3>; 1449 compatible = "atmel,sama5d4-aic"; 1450 interrupt-controller; 1451 reg = <0xfc06e000 0x200>; 1452 atmel,external-irqs = <56>; 1453 }; 1454 }; 1455 }; 1456};
~/
Read-only file preview.