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sama5d2.dtsi
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linux-6.19.14/arch/arm/boot/dts/microchip/sama5d2.dtsi
1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * sama5d2.dtsi - Device Tree Include file for SAMA5D2 family SoC 4 * 5 * Copyright (C) 2015 Atmel, 6 * 2015 Ludovic Desroches <ludovic.desroches@atmel.com> 7 */ 8 9#include <dt-bindings/dma/at91.h> 10#include <dt-bindings/interrupt-controller/irq.h> 11#include <dt-bindings/clock/at91.h> 12#include <dt-bindings/mfd/at91-usart.h> 13#include <dt-bindings/iio/adc/at91-sama5d2_adc.h> 14 15/ { 16 #address-cells = <1>; 17 #size-cells = <1>; 18 model = "Atmel SAMA5D2 family SoC"; 19 compatible = "atmel,sama5d2"; 20 interrupt-parent = <&aic>; 21 22 aliases { 23 serial0 = &uart1; 24 serial1 = &uart3; 25 }; 26 27 cpus { 28 #address-cells = <1>; 29 #size-cells = <0>; 30 31 cpu@0 { 32 device_type = "cpu"; 33 compatible = "arm,cortex-a5"; 34 reg = <0>; 35 d-cache-size = <0x8000>; // L1, 32 KB 36 i-cache-size = <0x8000>; // L1, 32 KB 37 next-level-cache = <&L2>; 38 }; 39 }; 40 41 pmu { 42 compatible = "arm,cortex-a5-pmu"; 43 interrupts = <2 IRQ_TYPE_LEVEL_HIGH 0>; 44 }; 45 46 etb@740000 { 47 compatible = "arm,coresight-etb10", "arm,primecell"; 48 reg = <0x740000 0x1000>; 49 50 clocks = <&pmc PMC_TYPE_CORE PMC_MCK>; 51 clock-names = "apb_pclk"; 52 53 in-ports { 54 port { 55 etb_in: endpoint { 56 remote-endpoint = <&etm_out>; 57 }; 58 }; 59 }; 60 }; 61 62 etm@73c000 { 63 compatible = "arm,coresight-etm3x", "arm,primecell"; 64 reg = <0x73c000 0x1000>; 65 66 clocks = <&pmc PMC_TYPE_CORE PMC_MCK>; 67 clock-names = "apb_pclk"; 68 69 out-ports { 70 port { 71 etm_out: endpoint { 72 remote-endpoint = <&etb_in>; 73 }; 74 }; 75 }; 76 }; 77 78 memory@20000000 { 79 device_type = "memory"; 80 reg = <0x20000000 0x20000000>; 81 }; 82 83 clocks { 84 slow_xtal: slow_xtal { 85 compatible = "fixed-clock"; 86 #clock-cells = <0>; 87 clock-frequency = <0>; 88 }; 89 90 main_xtal: main_xtal { 91 compatible = "fixed-clock"; 92 #clock-cells = <0>; 93 clock-frequency = <0>; 94 }; 95 }; 96 97 ns_sram: sram@200000 { 98 compatible = "mmio-sram"; 99 reg = <0x00200000 0x20000>; 100 #address-cells = <1>; 101 #size-cells = <1>; 102 ranges = <0 0x00200000 0x20000>; 103 }; 104 105 resistive_touch: resistive-touch { 106 compatible = "resistive-adc-touch"; 107 io-channels = <&adc AT91_SAMA5D2_ADC_X_CHANNEL>, 108 <&adc AT91_SAMA5D2_ADC_Y_CHANNEL>, 109 <&adc AT91_SAMA5D2_ADC_P_CHANNEL>; 110 io-channel-names = "x", "y", "pressure"; 111 touchscreen-min-pressure = <50000>; 112 status = "disabled"; 113 }; 114 115 ahb { 116 compatible = "simple-bus"; 117 #address-cells = <1>; 118 #size-cells = <1>; 119 ranges; 120 121 nfc_sram: sram@100000 { 122 compatible = "mmio-sram"; 123 no-memory-wc; 124 reg = <0x00100000 0x2400>; 125 #address-cells = <1>; 126 #size-cells = <1>; 127 ranges = <0 0x00100000 0x2400>; 128 129 }; 130 131 usb0: gadget@300000 { 132 compatible = "atmel,sama5d3-udc"; 133 reg = <0x00300000 0x100000 134 0xfc02c000 0x400>; 135 interrupts = <42 IRQ_TYPE_LEVEL_HIGH 2>; 136 clocks = <&pmc PMC_TYPE_PERIPHERAL 42>, <&pmc PMC_TYPE_CORE PMC_UTMI>; 137 clock-names = "pclk", "hclk"; 138 status = "disabled"; 139 }; 140 141 usb1: usb@400000 { 142 compatible = "atmel,at91rm9200-ohci", "usb-ohci"; 143 reg = <0x00400000 0x100000>; 144 interrupts = <41 IRQ_TYPE_LEVEL_HIGH 2>; 145 clocks = <&pmc PMC_TYPE_PERIPHERAL 41>, <&pmc PMC_TYPE_PERIPHERAL 41>, <&pmc PMC_TYPE_SYSTEM 6>; 146 clock-names = "ohci_clk", "hclk", "uhpck"; 147 status = "disabled"; 148 }; 149 150 usb2: usb@500000 { 151 compatible = "atmel,at91sam9g45-ehci", "usb-ehci"; 152 reg = <0x00500000 0x100000>; 153 interrupts = <41 IRQ_TYPE_LEVEL_HIGH 2>; 154 clocks = <&pmc PMC_TYPE_CORE PMC_UTMI>, <&pmc PMC_TYPE_PERIPHERAL 41>; 155 clock-names = "usb_clk", "ehci_clk"; 156 status = "disabled"; 157 }; 158 159 L2: cache-controller@a00000 { 160 compatible = "arm,pl310-cache"; 161 reg = <0x00a00000 0x1000>; 162 interrupts = <63 IRQ_TYPE_LEVEL_HIGH 4>; 163 cache-unified; 164 cache-level = <2>; 165 cache-size = <0x20000>; // L2, 128 KB 166 }; 167 168 ebi: ebi@10000000 { 169 compatible = "atmel,sama5d3-ebi"; 170 #address-cells = <2>; 171 #size-cells = <1>; 172 atmel,smc = <&hsmc>; 173 reg = <0x10000000 0x10000000 174 0x60000000 0x30000000>; 175 ranges = <0x0 0x0 0x10000000 0x10000000 176 0x1 0x0 0x60000000 0x10000000 177 0x2 0x0 0x70000000 0x10000000 178 0x3 0x0 0x80000000 0x10000000>; 179 clocks = <&pmc PMC_TYPE_CORE PMC_MCK2>; 180 status = "disabled"; 181 182 nand_controller: nand-controller { 183 compatible = "atmel,sama5d3-nand-controller"; 184 atmel,nfc-sram = <&nfc_sram>; 185 atmel,nfc-io = <&nfc_io>; 186 ecc-engine = <&pmecc>; 187 #address-cells = <2>; 188 #size-cells = <1>; 189 ranges; 190 status = "disabled"; 191 }; 192 }; 193 194 sdmmc0: sdio-host@a0000000 { 195 compatible = "atmel,sama5d2-sdhci"; 196 reg = <0xa0000000 0x300>; 197 interrupts = <31 IRQ_TYPE_LEVEL_HIGH 0>; 198 clocks = <&pmc PMC_TYPE_PERIPHERAL 31>, <&pmc PMC_TYPE_GCK 31>, <&pmc PMC_TYPE_CORE PMC_MAIN>; 199 clock-names = "hclock", "multclk", "baseclk"; 200 assigned-clocks = <&pmc PMC_TYPE_GCK 31>; 201 assigned-clock-rates = <480000000>; 202 status = "disabled"; 203 }; 204 205 sdmmc1: sdio-host@b0000000 { 206 compatible = "atmel,sama5d2-sdhci"; 207 reg = <0xb0000000 0x300>; 208 interrupts = <32 IRQ_TYPE_LEVEL_HIGH 0>; 209 clocks = <&pmc PMC_TYPE_PERIPHERAL 32>, <&pmc PMC_TYPE_GCK 32>, <&pmc PMC_TYPE_CORE PMC_MAIN>; 210 clock-names = "hclock", "multclk", "baseclk"; 211 assigned-clocks = <&pmc PMC_TYPE_GCK 32>; 212 assigned-clock-rates = <480000000>; 213 status = "disabled"; 214 }; 215 216 nfc_io: nfc-io@c0000000 { 217 compatible = "atmel,sama5d3-nfc-io", "syscon"; 218 reg = <0xc0000000 0x8000000>; 219 }; 220 221 apb { 222 compatible = "simple-bus"; 223 #address-cells = <1>; 224 #size-cells = <1>; 225 ranges; 226 227 hlcdc: hlcdc@f0000000 { 228 compatible = "atmel,sama5d2-hlcdc"; 229 reg = <0xf0000000 0x2000>; 230 interrupts = <45 IRQ_TYPE_LEVEL_HIGH 0>; 231 clocks = <&pmc PMC_TYPE_PERIPHERAL 45>, <&pmc PMC_TYPE_SYSTEM 3>, <&clk32k>; 232 clock-names = "periph_clk","sys_clk", "slow_clk"; 233 status = "disabled"; 234 235 hlcdc-display-controller { 236 compatible = "atmel,hlcdc-display-controller"; 237 #address-cells = <1>; 238 #size-cells = <0>; 239 240 port@0 { 241 #address-cells = <1>; 242 #size-cells = <0>; 243 reg = <0>; 244 }; 245 }; 246 247 hlcdc_pwm: hlcdc-pwm { 248 compatible = "atmel,hlcdc-pwm"; 249 #pwm-cells = <3>; 250 }; 251 }; 252 253 isc: isc@f0008000 { 254 compatible = "atmel,sama5d2-isc"; 255 reg = <0xf0008000 0x4000>; 256 interrupts = <46 IRQ_TYPE_LEVEL_HIGH 5>; 257 clocks = <&pmc PMC_TYPE_PERIPHERAL 46>, <&pmc PMC_TYPE_SYSTEM 18>, <&pmc PMC_TYPE_GCK 46>; 258 clock-names = "hclock", "iscck", "gck"; 259 #clock-cells = <0>; 260 clock-output-names = "isc-mck"; 261 status = "disabled"; 262 }; 263 264 ramc0: ramc@f000c000 { 265 compatible = "atmel,sama5d3-ddramc"; 266 reg = <0xf000c000 0x200>; 267 clocks = <&pmc PMC_TYPE_SYSTEM 2>, <&pmc PMC_TYPE_PERIPHERAL 13>; 268 clock-names = "ddrck", "mpddr"; 269 }; 270 271 dma0: dma-controller@f0010000 { 272 compatible = "atmel,sama5d4-dma"; 273 reg = <0xf0010000 0x1000>; 274 interrupts = <6 IRQ_TYPE_LEVEL_HIGH 0>; 275 #dma-cells = <1>; 276 clocks = <&pmc PMC_TYPE_PERIPHERAL 6>; 277 clock-names = "dma_clk"; 278 }; 279 280 /* Place dma1 here despite its address */ 281 dma1: dma-controller@f0004000 { 282 compatible = "atmel,sama5d4-dma"; 283 reg = <0xf0004000 0x1000>; 284 interrupts = <7 IRQ_TYPE_LEVEL_HIGH 0>; 285 #dma-cells = <1>; 286 clocks = <&pmc PMC_TYPE_PERIPHERAL 7>; 287 clock-names = "dma_clk"; 288 }; 289 290 pmc: clock-controller@f0014000 { 291 compatible = "atmel,sama5d2-pmc", "syscon"; 292 reg = <0xf0014000 0x160>; 293 interrupts = <74 IRQ_TYPE_LEVEL_HIGH 7>; 294 #clock-cells = <2>; 295 clocks = <&clk32k>, <&main_xtal>; 296 clock-names = "slow_clk", "main_xtal"; 297 }; 298 299 qspi0: spi@f0020000 { 300 compatible = "atmel,sama5d2-qspi"; 301 reg = <0xf0020000 0x100>, <0xd0000000 0x08000000>; 302 reg-names = "qspi_base", "qspi_mmap"; 303 interrupts = <52 IRQ_TYPE_LEVEL_HIGH 7>; 304 clocks = <&pmc PMC_TYPE_PERIPHERAL 52>; 305 clock-names = "pclk"; 306 #address-cells = <1>; 307 #size-cells = <0>; 308 status = "disabled"; 309 }; 310 311 qspi1: spi@f0024000 { 312 compatible = "atmel,sama5d2-qspi"; 313 reg = <0xf0024000 0x100>, <0xd8000000 0x08000000>; 314 reg-names = "qspi_base", "qspi_mmap"; 315 interrupts = <53 IRQ_TYPE_LEVEL_HIGH 7>; 316 clocks = <&pmc PMC_TYPE_PERIPHERAL 53>; 317 clock-names = "pclk"; 318 #address-cells = <1>; 319 #size-cells = <0>; 320 status = "disabled"; 321 }; 322 323 sha: crypto@f0028000 { 324 compatible = "atmel,at91sam9g46-sha"; 325 reg = <0xf0028000 0x100>; 326 interrupts = <12 IRQ_TYPE_LEVEL_HIGH 0>; 327 dmas = <&dma0 328 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 329 AT91_XDMAC_DT_PERID(30))>; 330 dma-names = "tx"; 331 clocks = <&pmc PMC_TYPE_PERIPHERAL 12>; 332 clock-names = "sha_clk"; 333 }; 334 335 aes: crypto@f002c000 { 336 compatible = "atmel,at91sam9g46-aes"; 337 reg = <0xf002c000 0x100>; 338 interrupts = <9 IRQ_TYPE_LEVEL_HIGH 0>; 339 dmas = <&dma0 340 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 341 AT91_XDMAC_DT_PERID(26))>, 342 <&dma0 343 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 344 AT91_XDMAC_DT_PERID(27))>; 345 dma-names = "tx", "rx"; 346 clocks = <&pmc PMC_TYPE_PERIPHERAL 9>; 347 clock-names = "aes_clk"; 348 }; 349 350 spi0: spi@f8000000 { 351 compatible = "atmel,at91rm9200-spi"; 352 reg = <0xf8000000 0x100>; 353 interrupts = <33 IRQ_TYPE_LEVEL_HIGH 7>; 354 dmas = <&dma0 355 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 356 AT91_XDMAC_DT_PERID(6))>, 357 <&dma0 358 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 359 AT91_XDMAC_DT_PERID(7))>; 360 dma-names = "tx", "rx"; 361 clocks = <&pmc PMC_TYPE_PERIPHERAL 33>; 362 clock-names = "spi_clk"; 363 atmel,fifo-size = <16>; 364 #address-cells = <1>; 365 #size-cells = <0>; 366 status = "disabled"; 367 }; 368 369 ssc0: ssc@f8004000 { 370 compatible = "atmel,at91sam9g45-ssc"; 371 reg = <0xf8004000 0x4000>; 372 interrupts = <43 IRQ_TYPE_LEVEL_HIGH 4>; 373 dmas = <&dma0 374 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 375 AT91_XDMAC_DT_PERID(21))>, 376 <&dma0 377 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 378 AT91_XDMAC_DT_PERID(22))>; 379 dma-names = "tx", "rx"; 380 clocks = <&pmc PMC_TYPE_PERIPHERAL 43>; 381 clock-names = "pclk"; 382 status = "disabled"; 383 }; 384 385 macb0: ethernet@f8008000 { 386 compatible = "atmel,sama5d2-gem"; 387 reg = <0xf8008000 0x1000>; 388 interrupts = <5 IRQ_TYPE_LEVEL_HIGH 3>, /* Queue 0 */ 389 <66 IRQ_TYPE_LEVEL_HIGH 3>, /* Queue 1 */ 390 <67 IRQ_TYPE_LEVEL_HIGH 3>; /* Queue 2 */ 391 clocks = <&pmc PMC_TYPE_PERIPHERAL 5>, <&pmc PMC_TYPE_PERIPHERAL 5>; 392 clock-names = "hclk", "pclk"; 393 status = "disabled"; 394 }; 395 396 tcb0: timer@f800c000 { 397 compatible = "atmel,sama5d2-tcb", "simple-mfd", "syscon"; 398 #address-cells = <1>; 399 #size-cells = <0>; 400 reg = <0xf800c000 0x100>; 401 interrupts = <35 IRQ_TYPE_LEVEL_HIGH 0>; 402 clocks = <&pmc PMC_TYPE_PERIPHERAL 35>, <&pmc PMC_TYPE_GCK 35>, <&clk32k>; 403 clock-names = "t0_clk", "gclk", "slow_clk"; 404 }; 405 406 tcb1: timer@f8010000 { 407 compatible = "atmel,sama5d2-tcb", "simple-mfd", "syscon"; 408 #address-cells = <1>; 409 #size-cells = <0>; 410 reg = <0xf8010000 0x100>; 411 interrupts = <36 IRQ_TYPE_LEVEL_HIGH 0>; 412 clocks = <&pmc PMC_TYPE_PERIPHERAL 36>, <&pmc PMC_TYPE_GCK 36>, <&clk32k>; 413 clock-names = "t0_clk", "gclk", "slow_clk"; 414 }; 415 416 hsmc: hsmc@f8014000 { 417 compatible = "atmel,sama5d2-smc", "syscon", "simple-mfd"; 418 reg = <0xf8014000 0x1000>; 419 interrupts = <17 IRQ_TYPE_LEVEL_HIGH 6>; 420 clocks = <&pmc PMC_TYPE_PERIPHERAL 17>; 421 #address-cells = <1>; 422 #size-cells = <1>; 423 ranges; 424 425 pmecc: ecc-engine@f8014070 { 426 compatible = "atmel,sama5d2-pmecc"; 427 reg = <0xf8014070 0x490>, 428 <0xf8014500 0x200>; 429 }; 430 }; 431 432 pdmic: pdmic@f8018000 { 433 compatible = "atmel,sama5d2-pdmic"; 434 reg = <0xf8018000 0x124>; 435 interrupts = <48 IRQ_TYPE_LEVEL_HIGH 7>; 436 dmas = <&dma0 437 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) 438 | AT91_XDMAC_DT_PERID(50))>; 439 dma-names = "rx"; 440 clocks = <&pmc PMC_TYPE_PERIPHERAL 48>, <&pmc PMC_TYPE_GCK 48>; 441 clock-names = "pclk", "gclk"; 442 status = "disabled"; 443 }; 444 445 uart0: serial@f801c000 { 446 compatible = "atmel,at91sam9260-usart"; 447 reg = <0xf801c000 0x100>; 448 atmel,usart-mode = <AT91_USART_MODE_SERIAL>; 449 interrupts = <24 IRQ_TYPE_LEVEL_HIGH 7>; 450 dmas = <&dma0 451 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 452 AT91_XDMAC_DT_PERID(35))>, 453 <&dma0 454 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 455 AT91_XDMAC_DT_PERID(36))>; 456 dma-names = "tx", "rx"; 457 clocks = <&pmc PMC_TYPE_PERIPHERAL 24>; 458 clock-names = "usart"; 459 status = "disabled"; 460 }; 461 462 uart1: serial@f8020000 { 463 compatible = "atmel,at91sam9260-usart"; 464 reg = <0xf8020000 0x100>; 465 atmel,usart-mode = <AT91_USART_MODE_SERIAL>; 466 interrupts = <25 IRQ_TYPE_LEVEL_HIGH 7>; 467 dmas = <&dma0 468 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 469 AT91_XDMAC_DT_PERID(37))>, 470 <&dma0 471 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 472 AT91_XDMAC_DT_PERID(38))>; 473 dma-names = "tx", "rx"; 474 clocks = <&pmc PMC_TYPE_PERIPHERAL 25>; 475 clock-names = "usart"; 476 status = "disabled"; 477 }; 478 479 uart2: serial@f8024000 { 480 compatible = "atmel,at91sam9260-usart"; 481 reg = <0xf8024000 0x100>; 482 atmel,usart-mode = <AT91_USART_MODE_SERIAL>; 483 interrupts = <26 IRQ_TYPE_LEVEL_HIGH 7>; 484 dmas = <&dma0 485 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 486 AT91_XDMAC_DT_PERID(39))>, 487 <&dma0 488 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 489 AT91_XDMAC_DT_PERID(40))>; 490 dma-names = "tx", "rx"; 491 clocks = <&pmc PMC_TYPE_PERIPHERAL 26>; 492 clock-names = "usart"; 493 status = "disabled"; 494 }; 495 496 i2c0: i2c@f8028000 { 497 compatible = "atmel,sama5d2-i2c"; 498 reg = <0xf8028000 0x100>; 499 interrupts = <29 IRQ_TYPE_LEVEL_HIGH 7>; 500 dmas = <&dma0 501 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 502 AT91_XDMAC_DT_PERID(0))>, 503 <&dma0 504 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 505 AT91_XDMAC_DT_PERID(1))>; 506 dma-names = "tx", "rx"; 507 #address-cells = <1>; 508 #size-cells = <0>; 509 clocks = <&pmc PMC_TYPE_PERIPHERAL 29>; 510 atmel,fifo-size = <16>; 511 status = "disabled"; 512 }; 513 514 pwm0: pwm@f802c000 { 515 compatible = "atmel,sama5d2-pwm"; 516 reg = <0xf802c000 0x4000>; 517 interrupts = <38 IRQ_TYPE_LEVEL_HIGH 7>; 518 #pwm-cells = <3>; 519 clocks = <&pmc PMC_TYPE_PERIPHERAL 38>; 520 status = "disabled"; 521 }; 522 523 sfr: sfr@f8030000 { 524 compatible = "atmel,sama5d2-sfr", "syscon"; 525 reg = <0xf8030000 0x98>; 526 }; 527 528 flx0: flexcom@f8034000 { 529 compatible = "atmel,sama5d2-flexcom"; 530 reg = <0xf8034000 0x200>; 531 clocks = <&pmc PMC_TYPE_PERIPHERAL 19>; 532 #address-cells = <1>; 533 #size-cells = <1>; 534 ranges = <0x0 0xf8034000 0x800>; 535 status = "disabled"; 536 537 uart5: serial@200 { 538 compatible = "atmel,at91sam9260-usart"; 539 reg = <0x200 0x200>; 540 atmel,usart-mode = <AT91_USART_MODE_SERIAL>; 541 interrupts = <19 IRQ_TYPE_LEVEL_HIGH 7>; 542 clocks = <&pmc PMC_TYPE_PERIPHERAL 19>; 543 clock-names = "usart"; 544 dmas = <&dma0 545 (AT91_XDMAC_DT_MEM_IF(0) | 546 AT91_XDMAC_DT_PER_IF(1) | 547 AT91_XDMAC_DT_PERID(11))>, 548 <&dma0 549 (AT91_XDMAC_DT_MEM_IF(0) | 550 AT91_XDMAC_DT_PER_IF(1) | 551 AT91_XDMAC_DT_PERID(12))>; 552 dma-names = "tx", "rx"; 553 atmel,fifo-size = <32>; 554 status = "disabled"; 555 }; 556 557 spi2: spi@400 { 558 compatible = "atmel,at91rm9200-spi"; 559 reg = <0x400 0x200>; 560 interrupts = <19 IRQ_TYPE_LEVEL_HIGH 7>; 561 #address-cells = <1>; 562 #size-cells = <0>; 563 clocks = <&pmc PMC_TYPE_PERIPHERAL 19>; 564 clock-names = "spi_clk"; 565 dmas = <&dma0 566 (AT91_XDMAC_DT_MEM_IF(0) | 567 AT91_XDMAC_DT_PER_IF(1) | 568 AT91_XDMAC_DT_PERID(11))>, 569 <&dma0 570 (AT91_XDMAC_DT_MEM_IF(0) | 571 AT91_XDMAC_DT_PER_IF(1) | 572 AT91_XDMAC_DT_PERID(12))>; 573 dma-names = "tx", "rx"; 574 atmel,fifo-size = <32>; 575 status = "disabled"; 576 }; 577 578 i2c2: i2c@600 { 579 compatible = "atmel,sama5d2-i2c"; 580 reg = <0x600 0x200>; 581 interrupts = <19 IRQ_TYPE_LEVEL_HIGH 7>; 582 #address-cells = <1>; 583 #size-cells = <0>; 584 clocks = <&pmc PMC_TYPE_PERIPHERAL 19>; 585 dmas = <&dma0 586 (AT91_XDMAC_DT_MEM_IF(0) | 587 AT91_XDMAC_DT_PER_IF(1) | 588 AT91_XDMAC_DT_PERID(11))>, 589 <&dma0 590 (AT91_XDMAC_DT_MEM_IF(0) | 591 AT91_XDMAC_DT_PER_IF(1) | 592 AT91_XDMAC_DT_PERID(12))>; 593 dma-names = "tx", "rx"; 594 atmel,fifo-size = <16>; 595 status = "disabled"; 596 }; 597 }; 598 599 flx1: flexcom@f8038000 { 600 compatible = "atmel,sama5d2-flexcom"; 601 reg = <0xf8038000 0x200>; 602 clocks = <&pmc PMC_TYPE_PERIPHERAL 20>; 603 #address-cells = <1>; 604 #size-cells = <1>; 605 ranges = <0x0 0xf8038000 0x800>; 606 status = "disabled"; 607 608 uart6: serial@200 { 609 compatible = "atmel,at91sam9260-usart"; 610 reg = <0x200 0x200>; 611 atmel,usart-mode = <AT91_USART_MODE_SERIAL>; 612 interrupts = <20 IRQ_TYPE_LEVEL_HIGH 7>; 613 clocks = <&pmc PMC_TYPE_PERIPHERAL 20>; 614 clock-names = "usart"; 615 dmas = <&dma0 616 (AT91_XDMAC_DT_MEM_IF(0) | 617 AT91_XDMAC_DT_PER_IF(1) | 618 AT91_XDMAC_DT_PERID(13))>, 619 <&dma0 620 (AT91_XDMAC_DT_MEM_IF(0) | 621 AT91_XDMAC_DT_PER_IF(1) | 622 AT91_XDMAC_DT_PERID(14))>; 623 dma-names = "tx", "rx"; 624 atmel,fifo-size = <32>; 625 status = "disabled"; 626 }; 627 628 spi3: spi@400 { 629 compatible = "atmel,at91rm9200-spi"; 630 reg = <0x400 0x200>; 631 interrupts = <20 IRQ_TYPE_LEVEL_HIGH 7>; 632 #address-cells = <1>; 633 #size-cells = <0>; 634 clocks = <&pmc PMC_TYPE_PERIPHERAL 20>; 635 clock-names = "spi_clk"; 636 dmas = <&dma0 637 (AT91_XDMAC_DT_MEM_IF(0) | 638 AT91_XDMAC_DT_PER_IF(1) | 639 AT91_XDMAC_DT_PERID(13))>, 640 <&dma0 641 (AT91_XDMAC_DT_MEM_IF(0) | 642 AT91_XDMAC_DT_PER_IF(1) | 643 AT91_XDMAC_DT_PERID(14))>; 644 dma-names = "tx", "rx"; 645 atmel,fifo-size = <32>; 646 status = "disabled"; 647 }; 648 649 i2c3: i2c@600 { 650 compatible = "atmel,sama5d2-i2c"; 651 reg = <0x600 0x200>; 652 interrupts = <20 IRQ_TYPE_LEVEL_HIGH 7>; 653 #address-cells = <1>; 654 #size-cells = <0>; 655 clocks = <&pmc PMC_TYPE_PERIPHERAL 20>; 656 dmas = <&dma0 657 (AT91_XDMAC_DT_MEM_IF(0) | 658 AT91_XDMAC_DT_PER_IF(1) | 659 AT91_XDMAC_DT_PERID(13))>, 660 <&dma0 661 (AT91_XDMAC_DT_MEM_IF(0) | 662 AT91_XDMAC_DT_PER_IF(1) | 663 AT91_XDMAC_DT_PERID(14))>; 664 dma-names = "tx", "rx"; 665 atmel,fifo-size = <16>; 666 status = "disabled"; 667 }; 668 }; 669 670 securam: sram@f8044000 { 671 compatible = "atmel,sama5d2-securam", "mmio-sram"; 672 reg = <0xf8044000 0x1420>; 673 clocks = <&pmc PMC_TYPE_PERIPHERAL 51>; 674 #address-cells = <1>; 675 #size-cells = <1>; 676 no-memory-wc; 677 ranges = <0 0xf8044000 0x1420>; 678 }; 679 680 reset_controller: reset-controller@f8048000 { 681 compatible = "atmel,sama5d3-rstc"; 682 reg = <0xf8048000 0x10>; 683 clocks = <&clk32k>; 684 }; 685 686 shutdown_controller: poweroff@f8048010 { 687 compatible = "atmel,sama5d2-shdwc"; 688 reg = <0xf8048010 0x10>; 689 clocks = <&clk32k>; 690 #address-cells = <1>; 691 #size-cells = <0>; 692 atmel,wakeup-rtc-timer; 693 }; 694 695 pit: timer@f8048030 { 696 compatible = "atmel,at91sam9260-pit"; 697 reg = <0xf8048030 0x10>; 698 interrupts = <3 IRQ_TYPE_LEVEL_HIGH 5>; 699 clocks = <&pmc PMC_TYPE_CORE PMC_MCK2>; 700 }; 701 702 watchdog: watchdog@f8048040 { 703 compatible = "atmel,sama5d4-wdt"; 704 reg = <0xf8048040 0x10>; 705 interrupts = <4 IRQ_TYPE_LEVEL_HIGH 7>; 706 clocks = <&clk32k>; 707 status = "disabled"; 708 }; 709 710 clk32k: clock-controller@f8048050 { 711 compatible = "atmel,sama5d4-sckc"; 712 reg = <0xf8048050 0x4>; 713 clocks = <&slow_xtal>; 714 #clock-cells = <0>; 715 }; 716 717 rtc: rtc@f80480b0 { 718 compatible = "atmel,sama5d2-rtc"; 719 reg = <0xf80480b0 0x30>; 720 interrupts = <74 IRQ_TYPE_LEVEL_HIGH 7>; 721 clocks = <&clk32k>; 722 }; 723 724 i2s0: i2s@f8050000 { 725 compatible = "atmel,sama5d2-i2s"; 726 reg = <0xf8050000 0x100>; 727 interrupts = <54 IRQ_TYPE_LEVEL_HIGH 7>; 728 dmas = <&dma0 729 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 730 AT91_XDMAC_DT_PERID(31))>, 731 <&dma0 732 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 733 AT91_XDMAC_DT_PERID(32))>; 734 dma-names = "tx", "rx"; 735 clocks = <&pmc PMC_TYPE_PERIPHERAL 54>, <&pmc PMC_TYPE_GCK 54>; 736 clock-names = "pclk", "gclk"; 737 assigned-clocks = <&pmc PMC_TYPE_CORE PMC_I2S0_MUX>; 738 assigned-clock-parents = <&pmc PMC_TYPE_GCK 54>; 739 status = "disabled"; 740 }; 741 742 can0: can@f8054000 { 743 compatible = "bosch,m_can"; 744 reg = <0xf8054000 0x4000>, <0x210000 0x1c00>; 745 reg-names = "m_can", "message_ram"; 746 interrupts = <56 IRQ_TYPE_LEVEL_HIGH 7>, 747 <64 IRQ_TYPE_LEVEL_HIGH 7>; 748 interrupt-names = "int0", "int1"; 749 clocks = <&pmc PMC_TYPE_PERIPHERAL 56>, <&pmc PMC_TYPE_GCK 56>; 750 clock-names = "hclk", "cclk"; 751 assigned-clocks = <&pmc PMC_TYPE_GCK 56>; 752 assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_UTMI>; 753 assigned-clock-rates = <40000000>; 754 bosch,mram-cfg = <0x0 0 0 64 0 0 32 32>; 755 status = "disabled"; 756 }; 757 758 spi1: spi@fc000000 { 759 compatible = "atmel,at91rm9200-spi"; 760 reg = <0xfc000000 0x100>; 761 interrupts = <34 IRQ_TYPE_LEVEL_HIGH 7>; 762 dmas = <&dma0 763 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 764 AT91_XDMAC_DT_PERID(8))>, 765 <&dma0 766 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 767 AT91_XDMAC_DT_PERID(9))>; 768 dma-names = "tx", "rx"; 769 clocks = <&pmc PMC_TYPE_PERIPHERAL 34>; 770 clock-names = "spi_clk"; 771 atmel,fifo-size = <16>; 772 #address-cells = <1>; 773 #size-cells = <0>; 774 status = "disabled"; 775 }; 776 777 uart3: serial@fc008000 { 778 compatible = "atmel,at91sam9260-usart"; 779 reg = <0xfc008000 0x100>; 780 atmel,usart-mode = <AT91_USART_MODE_SERIAL>; 781 interrupts = <27 IRQ_TYPE_LEVEL_HIGH 7>; 782 dmas = <&dma1 783 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 784 AT91_XDMAC_DT_PERID(41))>, 785 <&dma1 786 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 787 AT91_XDMAC_DT_PERID(42))>; 788 dma-names = "tx", "rx"; 789 clocks = <&pmc PMC_TYPE_PERIPHERAL 27>; 790 clock-names = "usart"; 791 status = "disabled"; 792 }; 793 794 uart4: serial@fc00c000 { 795 compatible = "atmel,at91sam9260-usart"; 796 reg = <0xfc00c000 0x100>; 797 atmel,usart-mode = <AT91_USART_MODE_SERIAL>; 798 dmas = <&dma0 799 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 800 AT91_XDMAC_DT_PERID(43))>, 801 <&dma0 802 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 803 AT91_XDMAC_DT_PERID(44))>; 804 dma-names = "tx", "rx"; 805 interrupts = <28 IRQ_TYPE_LEVEL_HIGH 7>; 806 clocks = <&pmc PMC_TYPE_PERIPHERAL 28>; 807 clock-names = "usart"; 808 status = "disabled"; 809 }; 810 811 flx2: flexcom@fc010000 { 812 compatible = "atmel,sama5d2-flexcom"; 813 reg = <0xfc010000 0x200>; 814 clocks = <&pmc PMC_TYPE_PERIPHERAL 21>; 815 #address-cells = <1>; 816 #size-cells = <1>; 817 ranges = <0x0 0xfc010000 0x800>; 818 status = "disabled"; 819 820 uart7: serial@200 { 821 compatible = "atmel,at91sam9260-usart"; 822 reg = <0x200 0x200>; 823 atmel,usart-mode = <AT91_USART_MODE_SERIAL>; 824 interrupts = <21 IRQ_TYPE_LEVEL_HIGH 7>; 825 clocks = <&pmc PMC_TYPE_PERIPHERAL 21>; 826 clock-names = "usart"; 827 dmas = <&dma0 828 (AT91_XDMAC_DT_MEM_IF(0) | 829 AT91_XDMAC_DT_PER_IF(1) | 830 AT91_XDMAC_DT_PERID(15))>, 831 <&dma0 832 (AT91_XDMAC_DT_MEM_IF(0) | 833 AT91_XDMAC_DT_PER_IF(1) | 834 AT91_XDMAC_DT_PERID(16))>; 835 dma-names = "tx", "rx"; 836 atmel,fifo-size = <32>; 837 status = "disabled"; 838 }; 839 840 spi4: spi@400 { 841 compatible = "atmel,at91rm9200-spi"; 842 reg = <0x400 0x200>; 843 interrupts = <21 IRQ_TYPE_LEVEL_HIGH 7>; 844 #address-cells = <1>; 845 #size-cells = <0>; 846 clocks = <&pmc PMC_TYPE_PERIPHERAL 21>; 847 clock-names = "spi_clk"; 848 dmas = <&dma0 849 (AT91_XDMAC_DT_MEM_IF(0) | 850 AT91_XDMAC_DT_PER_IF(1) | 851 AT91_XDMAC_DT_PERID(15))>, 852 <&dma0 853 (AT91_XDMAC_DT_MEM_IF(0) | 854 AT91_XDMAC_DT_PER_IF(1) | 855 AT91_XDMAC_DT_PERID(16))>; 856 dma-names = "tx", "rx"; 857 atmel,fifo-size = <32>; 858 status = "disabled"; 859 }; 860 861 i2c4: i2c@600 { 862 compatible = "atmel,sama5d2-i2c"; 863 reg = <0x600 0x200>; 864 interrupts = <21 IRQ_TYPE_LEVEL_HIGH 7>; 865 #address-cells = <1>; 866 #size-cells = <0>; 867 clocks = <&pmc PMC_TYPE_PERIPHERAL 21>; 868 dmas = <&dma0 869 (AT91_XDMAC_DT_MEM_IF(0) | 870 AT91_XDMAC_DT_PER_IF(1) | 871 AT91_XDMAC_DT_PERID(15))>, 872 <&dma0 873 (AT91_XDMAC_DT_MEM_IF(0) | 874 AT91_XDMAC_DT_PER_IF(1) | 875 AT91_XDMAC_DT_PERID(16))>; 876 dma-names = "tx", "rx"; 877 atmel,fifo-size = <16>; 878 status = "disabled"; 879 }; 880 }; 881 882 flx3: flexcom@fc014000 { 883 compatible = "atmel,sama5d2-flexcom"; 884 reg = <0xfc014000 0x200>; 885 clocks = <&pmc PMC_TYPE_PERIPHERAL 22>; 886 #address-cells = <1>; 887 #size-cells = <1>; 888 ranges = <0x0 0xfc014000 0x800>; 889 status = "disabled"; 890 891 uart8: serial@200 { 892 compatible = "atmel,at91sam9260-usart"; 893 reg = <0x200 0x200>; 894 atmel,usart-mode = <AT91_USART_MODE_SERIAL>; 895 interrupts = <22 IRQ_TYPE_LEVEL_HIGH 7>; 896 clocks = <&pmc PMC_TYPE_PERIPHERAL 22>; 897 clock-names = "usart"; 898 dmas = <&dma0 899 (AT91_XDMAC_DT_MEM_IF(0) | 900 AT91_XDMAC_DT_PER_IF(1) | 901 AT91_XDMAC_DT_PERID(17))>, 902 <&dma0 903 (AT91_XDMAC_DT_MEM_IF(0) | 904 AT91_XDMAC_DT_PER_IF(1) | 905 AT91_XDMAC_DT_PERID(18))>; 906 dma-names = "tx", "rx"; 907 atmel,fifo-size = <32>; 908 status = "disabled"; 909 }; 910 911 spi5: spi@400 { 912 compatible = "atmel,at91rm9200-spi"; 913 reg = <0x400 0x200>; 914 interrupts = <22 IRQ_TYPE_LEVEL_HIGH 7>; 915 #address-cells = <1>; 916 #size-cells = <0>; 917 clocks = <&pmc PMC_TYPE_PERIPHERAL 22>; 918 clock-names = "spi_clk"; 919 dmas = <&dma0 920 (AT91_XDMAC_DT_MEM_IF(0) | 921 AT91_XDMAC_DT_PER_IF(1) | 922 AT91_XDMAC_DT_PERID(17))>, 923 <&dma0 924 (AT91_XDMAC_DT_MEM_IF(0) | 925 AT91_XDMAC_DT_PER_IF(1) | 926 AT91_XDMAC_DT_PERID(18))>; 927 dma-names = "tx", "rx"; 928 atmel,fifo-size = <32>; 929 status = "disabled"; 930 }; 931 932 i2c5: i2c@600 { 933 compatible = "atmel,sama5d2-i2c"; 934 reg = <0x600 0x200>; 935 interrupts = <22 IRQ_TYPE_LEVEL_HIGH 7>; 936 #address-cells = <1>; 937 #size-cells = <0>; 938 clocks = <&pmc PMC_TYPE_PERIPHERAL 22>; 939 dmas = <&dma0 940 (AT91_XDMAC_DT_MEM_IF(0) | 941 AT91_XDMAC_DT_PER_IF(1) | 942 AT91_XDMAC_DT_PERID(17))>, 943 <&dma0 944 (AT91_XDMAC_DT_MEM_IF(0) | 945 AT91_XDMAC_DT_PER_IF(1) | 946 AT91_XDMAC_DT_PERID(18))>; 947 dma-names = "tx", "rx"; 948 atmel,fifo-size = <16>; 949 status = "disabled"; 950 }; 951 952 }; 953 954 flx4: flexcom@fc018000 { 955 compatible = "atmel,sama5d2-flexcom"; 956 reg = <0xfc018000 0x200>; 957 clocks = <&pmc PMC_TYPE_PERIPHERAL 23>; 958 #address-cells = <1>; 959 #size-cells = <1>; 960 ranges = <0x0 0xfc018000 0x800>; 961 status = "disabled"; 962 963 uart9: serial@200 { 964 compatible = "atmel,at91sam9260-usart"; 965 reg = <0x200 0x200>; 966 atmel,usart-mode = <AT91_USART_MODE_SERIAL>; 967 interrupts = <23 IRQ_TYPE_LEVEL_HIGH 7>; 968 clocks = <&pmc PMC_TYPE_PERIPHERAL 23>; 969 clock-names = "usart"; 970 dmas = <&dma0 971 (AT91_XDMAC_DT_MEM_IF(0) | 972 AT91_XDMAC_DT_PER_IF(1) | 973 AT91_XDMAC_DT_PERID(19))>, 974 <&dma0 975 (AT91_XDMAC_DT_MEM_IF(0) | 976 AT91_XDMAC_DT_PER_IF(1) | 977 AT91_XDMAC_DT_PERID(20))>; 978 dma-names = "tx", "rx"; 979 atmel,fifo-size = <32>; 980 status = "disabled"; 981 }; 982 983 spi6: spi@400 { 984 compatible = "atmel,at91rm9200-spi"; 985 reg = <0x400 0x200>; 986 interrupts = <23 IRQ_TYPE_LEVEL_HIGH 7>; 987 #address-cells = <1>; 988 #size-cells = <0>; 989 clocks = <&pmc PMC_TYPE_PERIPHERAL 23>; 990 clock-names = "spi_clk"; 991 dmas = <&dma0 992 (AT91_XDMAC_DT_MEM_IF(0) | 993 AT91_XDMAC_DT_PER_IF(1) | 994 AT91_XDMAC_DT_PERID(19))>, 995 <&dma0 996 (AT91_XDMAC_DT_MEM_IF(0) | 997 AT91_XDMAC_DT_PER_IF(1) | 998 AT91_XDMAC_DT_PERID(20))>; 999 dma-names = "tx", "rx"; 1000 atmel,fifo-size = <32>; 1001 status = "disabled"; 1002 }; 1003 1004 i2c6: i2c@600 { 1005 compatible = "atmel,sama5d2-i2c"; 1006 reg = <0x600 0x200>; 1007 interrupts = <23 IRQ_TYPE_LEVEL_HIGH 7>; 1008 #address-cells = <1>; 1009 #size-cells = <0>; 1010 clocks = <&pmc PMC_TYPE_PERIPHERAL 23>; 1011 dmas = <&dma0 1012 (AT91_XDMAC_DT_MEM_IF(0) | 1013 AT91_XDMAC_DT_PER_IF(1) | 1014 AT91_XDMAC_DT_PERID(19))>, 1015 <&dma0 1016 (AT91_XDMAC_DT_MEM_IF(0) | 1017 AT91_XDMAC_DT_PER_IF(1) | 1018 AT91_XDMAC_DT_PERID(20))>; 1019 dma-names = "tx", "rx"; 1020 atmel,fifo-size = <16>; 1021 status = "disabled"; 1022 }; 1023 }; 1024 1025 trng: rng@fc01c000 { 1026 compatible = "atmel,at91sam9g45-trng"; 1027 reg = <0xfc01c000 0x100>; 1028 interrupts = <47 IRQ_TYPE_LEVEL_HIGH 0>; 1029 clocks = <&pmc PMC_TYPE_PERIPHERAL 47>; 1030 }; 1031 1032 aic: interrupt-controller@fc020000 { 1033 #interrupt-cells = <3>; 1034 compatible = "atmel,sama5d2-aic"; 1035 interrupt-controller; 1036 reg = <0xfc020000 0x200>; 1037 atmel,external-irqs = <49>; 1038 }; 1039 1040 i2c1: i2c@fc028000 { 1041 compatible = "atmel,sama5d2-i2c"; 1042 reg = <0xfc028000 0x100>; 1043 interrupts = <30 IRQ_TYPE_LEVEL_HIGH 7>; 1044 dmas = <&dma0 1045 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 1046 AT91_XDMAC_DT_PERID(2))>, 1047 <&dma0 1048 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 1049 AT91_XDMAC_DT_PERID(3))>; 1050 dma-names = "tx", "rx"; 1051 #address-cells = <1>; 1052 #size-cells = <0>; 1053 clocks = <&pmc PMC_TYPE_PERIPHERAL 30>; 1054 atmel,fifo-size = <16>; 1055 status = "disabled"; 1056 }; 1057 1058 adc: adc@fc030000 { 1059 compatible = "atmel,sama5d2-adc"; 1060 reg = <0xfc030000 0x100>; 1061 interrupts = <40 IRQ_TYPE_LEVEL_HIGH 7>; 1062 clocks = <&pmc PMC_TYPE_PERIPHERAL 40>; 1063 clock-names = "adc_clk"; 1064 dmas = <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | AT91_XDMAC_DT_PERID(25))>; 1065 dma-names = "rx"; 1066 atmel,min-sample-rate-hz = <200000>; 1067 atmel,max-sample-rate-hz = <20000000>; 1068 atmel,startup-time-ms = <4>; 1069 atmel,trigger-edge-type = <IRQ_TYPE_EDGE_RISING>; 1070 #io-channel-cells = <1>; 1071 status = "disabled"; 1072 }; 1073 1074 pioA: pinctrl@fc038000 { 1075 compatible = "atmel,sama5d2-pinctrl"; 1076 reg = <0xfc038000 0x600>; 1077 interrupts = <18 IRQ_TYPE_LEVEL_HIGH 7>, 1078 <68 IRQ_TYPE_LEVEL_HIGH 7>, 1079 <69 IRQ_TYPE_LEVEL_HIGH 7>, 1080 <70 IRQ_TYPE_LEVEL_HIGH 7>; 1081 interrupt-controller; 1082 #interrupt-cells = <2>; 1083 gpio-controller; 1084 #gpio-cells = <2>; 1085 clocks = <&pmc PMC_TYPE_PERIPHERAL 18>; 1086 }; 1087 1088 pioBU: secumod@fc040000 { 1089 compatible = "atmel,sama5d2-secumod", "syscon"; 1090 reg = <0xfc040000 0x100>; 1091 1092 gpio-controller; 1093 #gpio-cells = <2>; 1094 }; 1095 1096 tdes: crypto@fc044000 { 1097 compatible = "atmel,at91sam9g46-tdes"; 1098 reg = <0xfc044000 0x100>; 1099 interrupts = <11 IRQ_TYPE_LEVEL_HIGH 0>; 1100 dmas = <&dma0 1101 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 1102 AT91_XDMAC_DT_PERID(28))>, 1103 <&dma0 1104 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 1105 AT91_XDMAC_DT_PERID(29))>; 1106 dma-names = "tx", "rx"; 1107 clocks = <&pmc PMC_TYPE_PERIPHERAL 11>; 1108 clock-names = "tdes_clk"; 1109 }; 1110 1111 classd: classd@fc048000 { 1112 compatible = "atmel,sama5d2-classd"; 1113 reg = <0xfc048000 0x100>; 1114 interrupts = <59 IRQ_TYPE_LEVEL_HIGH 7>; 1115 dmas = <&dma0 1116 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 1117 AT91_XDMAC_DT_PERID(47))>; 1118 dma-names = "tx"; 1119 clocks = <&pmc PMC_TYPE_PERIPHERAL 59>, <&pmc PMC_TYPE_GCK 59>; 1120 clock-names = "pclk", "gclk"; 1121 status = "disabled"; 1122 }; 1123 1124 i2s1: i2s@fc04c000 { 1125 compatible = "atmel,sama5d2-i2s"; 1126 reg = <0xfc04c000 0x100>; 1127 interrupts = <55 IRQ_TYPE_LEVEL_HIGH 7>; 1128 dmas = <&dma0 1129 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 1130 AT91_XDMAC_DT_PERID(33))>, 1131 <&dma0 1132 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 1133 AT91_XDMAC_DT_PERID(34))>; 1134 dma-names = "tx", "rx"; 1135 clocks = <&pmc PMC_TYPE_PERIPHERAL 55>, <&pmc PMC_TYPE_GCK 55>; 1136 clock-names = "pclk", "gclk"; 1137 assigned-clocks = <&pmc PMC_TYPE_CORE PMC_I2S1_MUX>; 1138 assigned-clock-parents = <&pmc PMC_TYPE_GCK 55>; 1139 status = "disabled"; 1140 }; 1141 1142 can1: can@fc050000 { 1143 compatible = "bosch,m_can"; 1144 reg = <0xfc050000 0x4000>, <0x210000 0x3800>; 1145 reg-names = "m_can", "message_ram"; 1146 interrupts = <57 IRQ_TYPE_LEVEL_HIGH 7>, 1147 <65 IRQ_TYPE_LEVEL_HIGH 7>; 1148 interrupt-names = "int0", "int1"; 1149 clocks = <&pmc PMC_TYPE_PERIPHERAL 57>, <&pmc PMC_TYPE_GCK 57>; 1150 clock-names = "hclk", "cclk"; 1151 assigned-clocks = <&pmc PMC_TYPE_GCK 57>; 1152 assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_UTMI>; 1153 assigned-clock-rates = <40000000>; 1154 bosch,mram-cfg = <0x1c00 0 0 64 0 0 32 32>; 1155 status = "disabled"; 1156 }; 1157 1158 sfrbu: sfr@fc05c000 { 1159 compatible = "atmel,sama5d2-sfrbu", "syscon"; 1160 reg = <0xfc05c000 0x20>; 1161 }; 1162 1163 chipid@fc069000 { 1164 compatible = "atmel,sama5d2-chipid"; 1165 reg = <0xfc069000 0x8>; 1166 }; 1167 }; 1168 }; 1169};
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