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sam9x7.dtsi
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linux-6.19.14/arch/arm/boot/dts/microchip/sam9x7.dtsi
1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * sam9x7.dtsi - Device Tree Include file for Microchip SAM9X7 SoC family 4 * 5 * Copyright (C) 2023 Microchip Technology Inc. and its subsidiaries 6 * 7 * Author: Varshini Rajendran <varshini.rajendran@microchip.com> 8 */ 9 10#include <dt-bindings/clock/at91.h> 11#include <dt-bindings/dma/at91.h> 12#include <dt-bindings/gpio/gpio.h> 13#include <dt-bindings/interrupt-controller/arm-gic.h> 14#include <dt-bindings/interrupt-controller/irq.h> 15#include <dt-bindings/mfd/at91-usart.h> 16#include <dt-bindings/mfd/atmel-flexcom.h> 17#include <dt-bindings/pinctrl/at91.h> 18 19/ { 20 model = "Microchip SAM9X7 SoC"; 21 compatible = "microchip,sam9x7"; 22 #address-cells = <1>; 23 #size-cells = <1>; 24 interrupt-parent = <&aic>; 25 26 aliases { 27 serial0 = &dbgu; 28 gpio0 = &pioA; 29 gpio1 = &pioB; 30 gpio2 = &pioC; 31 gpio3 = &pioD; 32 }; 33 34 cpus { 35 #address-cells = <1>; 36 #size-cells = <0>; 37 38 cpu@0 { 39 compatible = "arm,arm926ej-s"; 40 reg = <0>; 41 device_type = "cpu"; 42 }; 43 }; 44 45 clocks { 46 slow_xtal: clock-slowxtal { 47 compatible = "fixed-clock"; 48 clock-output-names = "slow_xtal"; 49 #clock-cells = <0>; 50 }; 51 52 main_xtal: clock-mainxtal { 53 compatible = "fixed-clock"; 54 clock-output-names = "main_xtal"; 55 #clock-cells = <0>; 56 }; 57 }; 58 59 sram: sram@300000 { 60 compatible = "mmio-sram"; 61 reg = <0x300000 0x10000>; 62 ranges = <0 0x300000 0x10000>; 63 #address-cells = <1>; 64 #size-cells = <1>; 65 }; 66 67 ahb { 68 compatible = "simple-bus"; 69 ranges; 70 #address-cells = <1>; 71 #size-cells = <1>; 72 73 sdmmc0: mmc@80000000 { 74 compatible = "microchip,sam9x7-sdhci", "microchip,sam9x60-sdhci"; 75 reg = <0x80000000 0x300>; 76 interrupts = <12 IRQ_TYPE_LEVEL_HIGH 0>; 77 clocks = <&pmc PMC_TYPE_PERIPHERAL 12>, <&pmc PMC_TYPE_GCK 12>; 78 clock-names = "hclock", "multclk"; 79 assigned-clocks = <&pmc PMC_TYPE_GCK 12>; 80 assigned-clock-rates = <100000000>; 81 status = "disabled"; 82 }; 83 84 sdmmc1: mmc@90000000 { 85 compatible = "microchip,sam9x7-sdhci", "microchip,sam9x60-sdhci"; 86 reg = <0x90000000 0x300>; 87 interrupts = <26 IRQ_TYPE_LEVEL_HIGH 0>; 88 clocks = <&pmc PMC_TYPE_PERIPHERAL 26>, <&pmc PMC_TYPE_GCK 26>; 89 clock-names = "hclock", "multclk"; 90 assigned-clocks = <&pmc PMC_TYPE_GCK 26>; 91 assigned-clock-rates = <100000000>; 92 status = "disabled"; 93 }; 94 }; 95 96 apb { 97 compatible = "simple-bus"; 98 ranges; 99 #address-cells = <1>; 100 #size-cells = <1>; 101 102 flx4: flexcom@f0000000 { 103 compatible = "microchip,sam9x7-flexcom", "atmel,sama5d2-flexcom"; 104 reg = <0xf0000000 0x200>; 105 ranges = <0x0 0xf0000000 0x800>; 106 #address-cells = <1>; 107 #size-cells = <1>; 108 clocks = <&pmc PMC_TYPE_PERIPHERAL 13>; 109 status = "disabled"; 110 111 uart4: serial@200 { 112 compatible = "microchip,sam9x7-usart", "atmel,at91sam9260-usart"; 113 reg = <0x200 0x200>; 114 interrupts = <13 IRQ_TYPE_LEVEL_HIGH 7>; 115 clocks = <&pmc PMC_TYPE_PERIPHERAL 13>; 116 clock-names = "usart"; 117 dmas = <&dma0 118 (AT91_XDMAC_DT_MEM_IF(0) | 119 AT91_XDMAC_DT_PER_IF(1) | 120 AT91_XDMAC_DT_PERID(8))>, 121 <&dma0 122 (AT91_XDMAC_DT_MEM_IF(0) | 123 AT91_XDMAC_DT_PER_IF(1) | 124 AT91_XDMAC_DT_PERID(9))>; 125 dma-names = "tx", "rx"; 126 atmel,use-dma-rx; 127 atmel,use-dma-tx; 128 atmel,fifo-size = <16>; 129 atmel,usart-mode = <AT91_USART_MODE_SERIAL>; 130 status = "disabled"; 131 }; 132 133 spi4: spi@400 { 134 compatible = "microchip,sam9x7-spi", "atmel,at91rm9200-spi"; 135 reg = <0x400 0x200>; 136 interrupts = <13 IRQ_TYPE_LEVEL_HIGH 7>; 137 #address-cells = <1>; 138 #size-cells = <0>; 139 clocks = <&pmc PMC_TYPE_PERIPHERAL 13>; 140 clock-names = "spi_clk"; 141 dmas = <&dma0 142 (AT91_XDMAC_DT_MEM_IF(0) | 143 AT91_XDMAC_DT_PER_IF(1) | 144 AT91_XDMAC_DT_PERID(8))>, 145 <&dma0 146 (AT91_XDMAC_DT_MEM_IF(0) | 147 AT91_XDMAC_DT_PER_IF(1) | 148 AT91_XDMAC_DT_PERID(9))>; 149 dma-names = "tx", "rx"; 150 atmel,fifo-size = <16>; 151 status = "disabled"; 152 }; 153 154 i2c4: i2c@600 { 155 compatible = "microchip,sam9x7-i2c", "microchip,sam9x60-i2c"; 156 reg = <0x600 0x200>; 157 interrupts = <13 IRQ_TYPE_LEVEL_HIGH 7>; 158 #address-cells = <1>; 159 #size-cells = <0>; 160 clocks = <&pmc PMC_TYPE_PERIPHERAL 13>; 161 dmas = <&dma0 162 (AT91_XDMAC_DT_MEM_IF(0) | 163 AT91_XDMAC_DT_PER_IF(1) | 164 AT91_XDMAC_DT_PERID(8))>, 165 <&dma0 166 (AT91_XDMAC_DT_MEM_IF(0) | 167 AT91_XDMAC_DT_PER_IF(1) | 168 AT91_XDMAC_DT_PERID(9))>; 169 dma-names = "tx", "rx"; 170 atmel,fifo-size = <16>; 171 status = "disabled"; 172 }; 173 }; 174 175 flx5: flexcom@f0004000 { 176 compatible = "microchip,sam9x7-flexcom", "atmel,sama5d2-flexcom"; 177 reg = <0xf0004000 0x200>; 178 ranges = <0x0 0xf0004000 0x800>; 179 #address-cells = <1>; 180 #size-cells = <1>; 181 clocks = <&pmc PMC_TYPE_PERIPHERAL 14>; 182 status = "disabled"; 183 184 uart5: serial@200 { 185 compatible = "microchip,sam9x7-usart", "atmel,at91sam9260-usart"; 186 reg = <0x200 0x200>; 187 interrupts = <14 IRQ_TYPE_LEVEL_HIGH 7>; 188 clocks = <&pmc PMC_TYPE_PERIPHERAL 14>; 189 clock-names = "usart"; 190 dmas = <&dma0 191 (AT91_XDMAC_DT_MEM_IF(0) | 192 AT91_XDMAC_DT_PER_IF(1) | 193 AT91_XDMAC_DT_PERID(10))>, 194 <&dma0 195 (AT91_XDMAC_DT_MEM_IF(0) | 196 AT91_XDMAC_DT_PER_IF(1) | 197 AT91_XDMAC_DT_PERID(11))>; 198 dma-names = "tx", "rx"; 199 atmel,use-dma-rx; 200 atmel,use-dma-tx; 201 atmel,fifo-size = <16>; 202 atmel,usart-mode = <AT91_USART_MODE_SERIAL>; 203 status = "disabled"; 204 }; 205 206 spi5: spi@400 { 207 compatible = "microchip,sam9x7-spi", "atmel,at91rm9200-spi"; 208 reg = <0x400 0x200>; 209 interrupts = <14 IRQ_TYPE_LEVEL_HIGH 7>; 210 #address-cells = <1>; 211 #size-cells = <0>; 212 clocks = <&pmc PMC_TYPE_PERIPHERAL 14>; 213 clock-names = "spi_clk"; 214 dmas = <&dma0 215 (AT91_XDMAC_DT_MEM_IF(0) | 216 AT91_XDMAC_DT_PER_IF(1) | 217 AT91_XDMAC_DT_PERID(10))>, 218 <&dma0 219 (AT91_XDMAC_DT_MEM_IF(0) | 220 AT91_XDMAC_DT_PER_IF(1) | 221 AT91_XDMAC_DT_PERID(11))>; 222 dma-names = "tx", "rx"; 223 atmel,fifo-size = <16>; 224 status = "disabled"; 225 }; 226 227 i2c5: i2c@600 { 228 compatible = "microchip,sam9x7-i2c", "microchip,sam9x60-i2c"; 229 reg = <0x600 0x200>; 230 interrupts = <14 IRQ_TYPE_LEVEL_HIGH 7>; 231 #address-cells = <1>; 232 #size-cells = <0>; 233 clocks = <&pmc PMC_TYPE_PERIPHERAL 14>; 234 dmas = <&dma0 235 (AT91_XDMAC_DT_MEM_IF(0) | 236 AT91_XDMAC_DT_PER_IF(1) | 237 AT91_XDMAC_DT_PERID(10))>, 238 <&dma0 239 (AT91_XDMAC_DT_MEM_IF(0) | 240 AT91_XDMAC_DT_PER_IF(1) | 241 AT91_XDMAC_DT_PERID(11))>; 242 dma-names = "tx", "rx"; 243 atmel,fifo-size = <16>; 244 status = "disabled"; 245 }; 246 }; 247 248 dma0: dma-controller@f0008000 { 249 compatible = "microchip,sam9x7-dma", "atmel,sama5d4-dma"; 250 reg = <0xf0008000 0x1000>; 251 interrupts = <20 IRQ_TYPE_LEVEL_HIGH 0>; 252 #dma-cells = <1>; 253 clocks = <&pmc PMC_TYPE_PERIPHERAL 20>; 254 clock-names = "dma_clk"; 255 status = "disabled"; 256 }; 257 258 ssc: ssc@f0010000 { 259 compatible = "microchip,sam9x7-ssc", "atmel,at91sam9g45-ssc"; 260 reg = <0xf0010000 0x4000>; 261 interrupts = <28 IRQ_TYPE_LEVEL_HIGH 5>; 262 clocks = <&pmc PMC_TYPE_PERIPHERAL 28>; 263 clock-names = "pclk"; 264 dmas = <&dma0 265 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 266 AT91_XDMAC_DT_PERID(38))>, 267 <&dma0 268 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 269 AT91_XDMAC_DT_PERID(39))>; 270 dma-names = "tx", "rx"; 271 status = "disabled"; 272 }; 273 274 qspi: spi@f0014000 { 275 compatible = "microchip,sam9x7-ospi"; 276 #address-cells = <1>; 277 #size-cells = <0>; 278 reg = <0xf0014000 0x100>, <0x60000000 0x20000000>; 279 reg-names = "qspi_base", "qspi_mmap"; 280 interrupts = <35 IRQ_TYPE_LEVEL_HIGH 7>; 281 dmas = <&dma0 282 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 283 AT91_XDMAC_DT_PERID(26))>, 284 <&dma0 285 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 286 AT91_XDMAC_DT_PERID(27))>; 287 dma-names = "tx", "rx"; 288 clocks = <&pmc PMC_TYPE_PERIPHERAL 35>, <&pmc PMC_TYPE_GCK 35>; 289 clock-names = "pclk", "gclk"; 290 assigned-clocks = <&pmc PMC_TYPE_GCK 35>; 291 assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_PLLADIV2>; 292 status = "disabled"; 293 }; 294 295 i2s: i2s@f001c000 { 296 compatible = "microchip,sam9x7-i2smcc", "microchip,sam9x60-i2smcc"; 297 reg = <0xf001c000 0x100>; 298 interrupts = <34 IRQ_TYPE_LEVEL_HIGH 7>; 299 clocks = <&pmc PMC_TYPE_PERIPHERAL 34>, <&pmc PMC_TYPE_GCK 34>; 300 clock-names = "pclk", "gclk"; 301 dmas = <&dma0 302 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 303 AT91_XDMAC_DT_PERID(36))>, 304 <&dma0 305 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 306 AT91_XDMAC_DT_PERID(37))>; 307 dma-names = "tx", "rx"; 308 status = "disabled"; 309 }; 310 311 flx11: flexcom@f0020000 { 312 compatible = "microchip,sam9x7-flexcom", "atmel,sama5d2-flexcom"; 313 reg = <0xf0020000 0x200>; 314 ranges = <0x0 0xf0020000 0x800>; 315 #address-cells = <1>; 316 #size-cells = <1>; 317 clocks = <&pmc PMC_TYPE_PERIPHERAL 32>; 318 status = "disabled"; 319 320 uart11: serial@200 { 321 compatible = "microchip,sam9x7-usart", "atmel,at91sam9260-usart"; 322 reg = <0x200 0x200>; 323 interrupts = <32 IRQ_TYPE_LEVEL_HIGH 7>; 324 clocks = <&pmc PMC_TYPE_PERIPHERAL 32>; 325 clock-names = "usart"; 326 dmas = <&dma0 327 (AT91_XDMAC_DT_MEM_IF(0) | 328 AT91_XDMAC_DT_PER_IF(1) | 329 AT91_XDMAC_DT_PERID(22))>, 330 <&dma0 331 (AT91_XDMAC_DT_MEM_IF(0) | 332 AT91_XDMAC_DT_PER_IF(1) | 333 AT91_XDMAC_DT_PERID(23))>; 334 dma-names = "tx", "rx"; 335 atmel,use-dma-rx; 336 atmel,use-dma-tx; 337 atmel,fifo-size = <16>; 338 atmel,usart-mode = <AT91_USART_MODE_SERIAL>; 339 status = "disabled"; 340 }; 341 342 i2c11: i2c@600 { 343 compatible = "microchip,sam9x7-i2c", "microchip,sam9x60-i2c"; 344 reg = <0x600 0x200>; 345 interrupts = <32 IRQ_TYPE_LEVEL_HIGH 7>; 346 #address-cells = <1>; 347 #size-cells = <0>; 348 clocks = <&pmc PMC_TYPE_PERIPHERAL 32>; 349 dmas = <&dma0 350 (AT91_XDMAC_DT_MEM_IF(0) | 351 AT91_XDMAC_DT_PER_IF(1) | 352 AT91_XDMAC_DT_PERID(22))>, 353 <&dma0 354 (AT91_XDMAC_DT_MEM_IF(0) | 355 AT91_XDMAC_DT_PER_IF(1) | 356 AT91_XDMAC_DT_PERID(23))>; 357 dma-names = "tx", "rx"; 358 atmel,fifo-size = <16>; 359 status = "disabled"; 360 }; 361 }; 362 363 flx12: flexcom@f0024000 { 364 compatible = "microchip,sam9x7-flexcom", "atmel,sama5d2-flexcom"; 365 reg = <0xf0024000 0x200>; 366 ranges = <0x0 0xf0024000 0x800>; 367 #address-cells = <1>; 368 #size-cells = <1>; 369 clocks = <&pmc PMC_TYPE_PERIPHERAL 33>; 370 status = "disabled"; 371 372 uart12: serial@200 { 373 compatible = "microchip,sam9x7-usart", "atmel,at91sam9260-usart"; 374 reg = <0x200 0x200>; 375 interrupts = <33 IRQ_TYPE_LEVEL_HIGH 7>; 376 clocks = <&pmc PMC_TYPE_PERIPHERAL 33>; 377 clock-names = "usart"; 378 dmas = <&dma0 379 (AT91_XDMAC_DT_MEM_IF(0) | 380 AT91_XDMAC_DT_PER_IF(1) | 381 AT91_XDMAC_DT_PERID(24))>, 382 <&dma0 383 (AT91_XDMAC_DT_MEM_IF(0) | 384 AT91_XDMAC_DT_PER_IF(1) | 385 AT91_XDMAC_DT_PERID(25))>; 386 dma-names = "tx", "rx"; 387 atmel,use-dma-rx; 388 atmel,use-dma-tx; 389 atmel,fifo-size = <16>; 390 atmel,usart-mode = <AT91_USART_MODE_SERIAL>; 391 status = "disabled"; 392 }; 393 394 i2c12: i2c@600 { 395 compatible = "microchip,sam9x7-i2c", "microchip,sam9x60-i2c"; 396 reg = <0x600 0x200>; 397 interrupts = <33 IRQ_TYPE_LEVEL_HIGH 7>; 398 #address-cells = <1>; 399 #size-cells = <0>; 400 clocks = <&pmc PMC_TYPE_PERIPHERAL 33>; 401 dmas = <&dma0 402 (AT91_XDMAC_DT_MEM_IF(0) | 403 AT91_XDMAC_DT_PER_IF(1) | 404 AT91_XDMAC_DT_PERID(24))>, 405 <&dma0 406 (AT91_XDMAC_DT_MEM_IF(0) | 407 AT91_XDMAC_DT_PER_IF(1) | 408 AT91_XDMAC_DT_PERID(25))>; 409 dma-names = "tx", "rx"; 410 atmel,fifo-size = <16>; 411 status = "disabled"; 412 }; 413 }; 414 415 pit64b0: timer@f0028000 { 416 compatible = "microchip,sam9x7-pit64b", "microchip,sam9x60-pit64b"; 417 reg = <0xf0028000 0x100>; 418 interrupts = <37 IRQ_TYPE_LEVEL_HIGH 7>; 419 clocks = <&pmc PMC_TYPE_PERIPHERAL 37>, <&pmc PMC_TYPE_GCK 37>; 420 clock-names = "pclk", "gclk"; 421 }; 422 423 sha: crypto@f002c000 { 424 compatible = "microchip,sam9x7-sha", "atmel,at91sam9g46-sha"; 425 reg = <0xf002c000 0x100>; 426 interrupts = <41 IRQ_TYPE_LEVEL_HIGH 0>; 427 clocks = <&pmc PMC_TYPE_PERIPHERAL 41>; 428 clock-names = "sha_clk"; 429 dmas = <&dma0 430 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 431 AT91_XDMAC_DT_PERID(34))>; 432 dma-names = "tx"; 433 }; 434 435 trng: rng@f0030000 { 436 compatible = "microchip,sam9x7-trng", "microchip,sam9x60-trng"; 437 reg = <0xf0030000 0x100>; 438 interrupts = <38 IRQ_TYPE_LEVEL_HIGH 0>; 439 clocks = <&pmc PMC_TYPE_PERIPHERAL 38>; 440 status = "disabled"; 441 }; 442 443 aes: crypto@f0034000 { 444 compatible = "microchip,sam9x7-aes", "atmel,at91sam9g46-aes"; 445 reg = <0xf0034000 0x100>; 446 interrupts = <39 IRQ_TYPE_LEVEL_HIGH 0>; 447 clocks = <&pmc PMC_TYPE_PERIPHERAL 39>; 448 clock-names = "aes_clk"; 449 dmas = <&dma0 450 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 451 AT91_XDMAC_DT_PERID(32))>, 452 <&dma0 453 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 454 AT91_XDMAC_DT_PERID(33))>; 455 dma-names = "tx", "rx"; 456 }; 457 458 tdes: crypto@f0038000 { 459 compatible = "microchip,sam9x7-tdes", "atmel,at91sam9g46-tdes"; 460 reg = <0xf0038000 0x100>; 461 interrupts = <40 IRQ_TYPE_LEVEL_HIGH 0>; 462 clocks = <&pmc PMC_TYPE_PERIPHERAL 40>; 463 clock-names = "tdes_clk"; 464 dmas = <&dma0 465 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 466 AT91_XDMAC_DT_PERID(31))>, 467 <&dma0 468 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 469 AT91_XDMAC_DT_PERID(30))>; 470 dma-names = "tx", "rx"; 471 }; 472 473 classd: sound@f003c000 { 474 compatible = "microchip,sam9x7-classd", "atmel,sama5d2-classd"; 475 reg = <0xf003c000 0x100>; 476 interrupts = <42 IRQ_TYPE_LEVEL_HIGH 7>; 477 clocks = <&pmc PMC_TYPE_PERIPHERAL 42>, <&pmc PMC_TYPE_GCK 42>; 478 clock-names = "pclk", "gclk"; 479 dmas = <&dma0 480 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 481 AT91_XDMAC_DT_PERID(35))>; 482 dma-names = "tx"; 483 status = "disabled"; 484 }; 485 486 pit64b1: timer@f0040000 { 487 compatible = "microchip,sam9x7-pit64b", "microchip,sam9x60-pit64b"; 488 reg = <0xf0040000 0x100>; 489 interrupts = <58 IRQ_TYPE_LEVEL_HIGH 7>; 490 clocks = <&pmc PMC_TYPE_PERIPHERAL 58>, <&pmc PMC_TYPE_GCK 58>; 491 clock-names = "pclk", "gclk"; 492 }; 493 494 can0: can@f8000000 { 495 compatible = "bosch,m_can"; 496 reg = <0xf8000000 0x100>, <0x300000 0x7800>; 497 reg-names = "m_can", "message_ram"; 498 interrupts = <29 IRQ_TYPE_LEVEL_HIGH 0>, 499 <68 IRQ_TYPE_LEVEL_HIGH 0>; 500 interrupt-names = "int0", "int1"; 501 clocks = <&pmc PMC_TYPE_PERIPHERAL 29>, <&pmc PMC_TYPE_GCK 29>; 502 clock-names = "hclk", "cclk"; 503 assigned-clocks = <&pmc PMC_TYPE_CORE PMC_UTMI>, <&pmc PMC_TYPE_GCK 29>; 504 assigned-clock-rates = <480000000>, <40000000>; 505 assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_UTMI>, <&pmc PMC_TYPE_CORE PMC_UTMI>; 506 bosch,mram-cfg = <0x3400 0 0 64 0 0 32 32>; 507 status = "disabled"; 508 }; 509 510 can1: can@f8004000 { 511 compatible = "bosch,m_can"; 512 reg = <0xf8004000 0x100>, <0x300000 0xbc00>; 513 reg-names = "m_can", "message_ram"; 514 interrupts = <30 IRQ_TYPE_LEVEL_HIGH 0>, 515 <69 IRQ_TYPE_LEVEL_HIGH 0>; 516 interrupt-names = "int0", "int1"; 517 clocks = <&pmc PMC_TYPE_PERIPHERAL 30>, <&pmc PMC_TYPE_GCK 30>; 518 clock-names = "hclk", "cclk"; 519 assigned-clocks = <&pmc PMC_TYPE_CORE PMC_UTMI>, <&pmc PMC_TYPE_GCK 30>; 520 assigned-clock-rates = <480000000>, <40000000>; 521 assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_UTMI>, <&pmc PMC_TYPE_CORE PMC_UTMI>; 522 bosch,mram-cfg = <0x7800 0 0 64 0 0 32 32>; 523 status = "disabled"; 524 }; 525 526 tcb: timer@f8008000 { 527 compatible = "microchip,sam9x7-tcb","atmel,sama5d2-tcb", "simple-mfd", "syscon"; 528 reg = <0xf8008000 0x100>; 529 #address-cells = <1>; 530 #size-cells = <0>; 531 interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0>; 532 clocks = <&pmc PMC_TYPE_PERIPHERAL 17>, <&pmc PMC_TYPE_GCK 17>, <&clk32k 0>; 533 clock-names = "t0_clk", "gclk", "slow_clk"; 534 }; 535 536 flx6: flexcom@f8010000 { 537 compatible = "microchip,sam9x7-flexcom", "atmel,sama5d2-flexcom"; 538 reg = <0xf8010000 0x200>; 539 ranges = <0x0 0xf8010000 0x800>; 540 #address-cells = <1>; 541 #size-cells = <1>; 542 clocks = <&pmc PMC_TYPE_PERIPHERAL 9>; 543 status = "disabled"; 544 545 uart6: serial@200 { 546 compatible = "microchip,sam9x7-usart", "atmel,at91sam9260-usart"; 547 reg = <0x200 0x200>; 548 interrupts = <9 IRQ_TYPE_LEVEL_HIGH 7>; 549 clocks = <&pmc PMC_TYPE_PERIPHERAL 9>; 550 clock-names = "usart"; 551 dmas = <&dma0 552 (AT91_XDMAC_DT_MEM_IF(0) | 553 AT91_XDMAC_DT_PER_IF(1) | 554 AT91_XDMAC_DT_PERID(12))>, 555 <&dma0 556 (AT91_XDMAC_DT_MEM_IF(0) | 557 AT91_XDMAC_DT_PER_IF(1) | 558 AT91_XDMAC_DT_PERID(13))>; 559 dma-names = "tx", "rx"; 560 atmel,use-dma-rx; 561 atmel,use-dma-tx; 562 atmel,fifo-size = <16>; 563 atmel,usart-mode = <AT91_USART_MODE_SERIAL>; 564 status = "disabled"; 565 }; 566 567 i2c6: i2c@600 { 568 compatible = "microchip,sam9x7-i2c", "microchip,sam9x60-i2c"; 569 reg = <0x600 0x200>; 570 interrupts = <9 IRQ_TYPE_LEVEL_HIGH 7>; 571 #address-cells = <1>; 572 #size-cells = <0>; 573 clocks = <&pmc PMC_TYPE_PERIPHERAL 9>; 574 dmas = <&dma0 575 (AT91_XDMAC_DT_MEM_IF(0) | 576 AT91_XDMAC_DT_PER_IF(1) | 577 AT91_XDMAC_DT_PERID(12))>, 578 <&dma0 579 (AT91_XDMAC_DT_MEM_IF(0) | 580 AT91_XDMAC_DT_PER_IF(1) | 581 AT91_XDMAC_DT_PERID(13))>; 582 dma-names = "tx", "rx"; 583 atmel,fifo-size = <16>; 584 status = "disabled"; 585 }; 586 }; 587 588 flx7: flexcom@f8014000 { 589 compatible = "microchip,sam9x7-flexcom", "atmel,sama5d2-flexcom"; 590 reg = <0xf8014000 0x200>; 591 ranges = <0x0 0xf8014000 0x800>; 592 #address-cells = <1>; 593 #size-cells = <1>; 594 clocks = <&pmc PMC_TYPE_PERIPHERAL 10>; 595 status = "disabled"; 596 597 uart7: serial@200 { 598 compatible = "microchip,sam9x7-usart", "atmel,at91sam9260-usart"; 599 reg = <0x200 0x200>; 600 interrupts = <10 IRQ_TYPE_LEVEL_HIGH 7>; 601 clocks = <&pmc PMC_TYPE_PERIPHERAL 10>; 602 clock-names = "usart"; 603 dmas = <&dma0 604 (AT91_XDMAC_DT_MEM_IF(0) | 605 AT91_XDMAC_DT_PER_IF(1) | 606 AT91_XDMAC_DT_PERID(14))>, 607 <&dma0 608 (AT91_XDMAC_DT_MEM_IF(0) | 609 AT91_XDMAC_DT_PER_IF(1) | 610 AT91_XDMAC_DT_PERID(15))>; 611 dma-names = "tx", "rx"; 612 atmel,use-dma-rx; 613 atmel,use-dma-tx; 614 atmel,fifo-size = <16>; 615 atmel,usart-mode = <AT91_USART_MODE_SERIAL>; 616 status = "disabled"; 617 }; 618 619 i2c7: i2c@600 { 620 compatible = "microchip,sam9x7-i2c", "microchip,sam9x60-i2c"; 621 reg = <0x600 0x200>; 622 interrupts = <10 IRQ_TYPE_LEVEL_HIGH 7>; 623 #address-cells = <1>; 624 #size-cells = <0>; 625 clocks = <&pmc PMC_TYPE_PERIPHERAL 10>; 626 dmas = <&dma0 627 (AT91_XDMAC_DT_MEM_IF(0) | 628 AT91_XDMAC_DT_PER_IF(1) | 629 AT91_XDMAC_DT_PERID(14))>, 630 <&dma0 631 (AT91_XDMAC_DT_MEM_IF(0) | 632 AT91_XDMAC_DT_PER_IF(1) | 633 AT91_XDMAC_DT_PERID(15))>; 634 dma-names = "tx", "rx"; 635 atmel,fifo-size = <16>; 636 status = "disabled"; 637 }; 638 }; 639 640 flx8: flexcom@f8018000 { 641 compatible = "microchip,sam9x7-flexcom", "atmel,sama5d2-flexcom"; 642 reg = <0xf8018000 0x200>; 643 ranges = <0x0 0xf8018000 0x800>; 644 #address-cells = <1>; 645 #size-cells = <1>; 646 clocks = <&pmc PMC_TYPE_PERIPHERAL 11>; 647 status = "disabled"; 648 649 uart8: serial@200 { 650 compatible = "microchip,sam9x7-usart", "atmel,at91sam9260-usart"; 651 reg = <0x200 0x200>; 652 interrupts = <11 IRQ_TYPE_LEVEL_HIGH 7>; 653 clocks = <&pmc PMC_TYPE_PERIPHERAL 11>; 654 clock-names = "usart"; 655 dmas = <&dma0 656 (AT91_XDMAC_DT_MEM_IF(0) | 657 AT91_XDMAC_DT_PER_IF(1) | 658 AT91_XDMAC_DT_PERID(16))>, 659 <&dma0 660 (AT91_XDMAC_DT_MEM_IF(0) | 661 AT91_XDMAC_DT_PER_IF(1) | 662 AT91_XDMAC_DT_PERID(17))>; 663 dma-names = "tx", "rx"; 664 atmel,use-dma-rx; 665 atmel,use-dma-tx; 666 atmel,fifo-size = <16>; 667 atmel,usart-mode = <AT91_USART_MODE_SERIAL>; 668 status = "disabled"; 669 }; 670 671 i2c8: i2c@600 { 672 compatible = "microchip,sam9x7-i2c", "microchip,sam9x60-i2c"; 673 reg = <0x600 0x200>; 674 interrupts = <11 IRQ_TYPE_LEVEL_HIGH 7>; 675 #address-cells = <1>; 676 #size-cells = <0>; 677 clocks = <&pmc PMC_TYPE_PERIPHERAL 11>; 678 dmas = <&dma0 679 (AT91_XDMAC_DT_MEM_IF(0) | 680 AT91_XDMAC_DT_PER_IF(1) | 681 AT91_XDMAC_DT_PERID(16))>, 682 <&dma0 683 (AT91_XDMAC_DT_MEM_IF(0) | 684 AT91_XDMAC_DT_PER_IF(1) | 685 AT91_XDMAC_DT_PERID(17))>; 686 dma-names = "tx", "rx"; 687 atmel,fifo-size = <16>; 688 status = "disabled"; 689 }; 690 }; 691 692 flx0: flexcom@f801c000 { 693 compatible = "microchip,sam9x7-flexcom", "atmel,sama5d2-flexcom"; 694 reg = <0xf801c000 0x200>; 695 ranges = <0x0 0xf801c000 0x800>; 696 #address-cells = <1>; 697 #size-cells = <1>; 698 clocks = <&pmc PMC_TYPE_PERIPHERAL 5>; 699 status = "disabled"; 700 701 uart0: serial@200 { 702 compatible = "microchip,sam9x7-usart", "atmel,at91sam9260-usart"; 703 reg = <0x200 0x200>; 704 interrupts = <5 IRQ_TYPE_LEVEL_HIGH 7>; 705 clocks = <&pmc PMC_TYPE_PERIPHERAL 5>; 706 clock-names = "usart"; 707 dmas = <&dma0 708 (AT91_XDMAC_DT_MEM_IF(0) | 709 AT91_XDMAC_DT_PER_IF(1) | 710 AT91_XDMAC_DT_PERID(0))>, 711 <&dma0 712 (AT91_XDMAC_DT_MEM_IF(0) | 713 AT91_XDMAC_DT_PER_IF(1) | 714 AT91_XDMAC_DT_PERID(1))>; 715 dma-names = "tx", "rx"; 716 atmel,use-dma-rx; 717 atmel,use-dma-tx; 718 atmel,fifo-size = <16>; 719 atmel,usart-mode = <AT91_USART_MODE_SERIAL>; 720 status = "disabled"; 721 }; 722 723 spi0: spi@400 { 724 compatible = "microchip,sam9x7-spi", "atmel,at91rm9200-spi"; 725 reg = <0x400 0x200>; 726 interrupts = <5 IRQ_TYPE_LEVEL_HIGH 7>; 727 #address-cells = <1>; 728 #size-cells = <0>; 729 clocks = <&pmc PMC_TYPE_PERIPHERAL 5>; 730 clock-names = "spi_clk"; 731 dmas = <&dma0 732 (AT91_XDMAC_DT_MEM_IF(0) | 733 AT91_XDMAC_DT_PER_IF(1) | 734 AT91_XDMAC_DT_PERID(0))>, 735 <&dma0 736 (AT91_XDMAC_DT_MEM_IF(0) | 737 AT91_XDMAC_DT_PER_IF(1) | 738 AT91_XDMAC_DT_PERID(1))>; 739 dma-names = "tx", "rx"; 740 atmel,fifo-size = <16>; 741 status = "disabled"; 742 }; 743 744 i2c0: i2c@600 { 745 compatible = "microchip,sam9x7-i2c", "microchip,sam9x60-i2c"; 746 reg = <0x600 0x200>; 747 interrupts = <5 IRQ_TYPE_LEVEL_HIGH 7>; 748 #address-cells = <1>; 749 #size-cells = <0>; 750 clocks = <&pmc PMC_TYPE_PERIPHERAL 5>; 751 dmas = <&dma0 752 (AT91_XDMAC_DT_MEM_IF(0) | 753 AT91_XDMAC_DT_PER_IF(1) | 754 AT91_XDMAC_DT_PERID(0))>, 755 <&dma0 756 (AT91_XDMAC_DT_MEM_IF(0) | 757 AT91_XDMAC_DT_PER_IF(1) | 758 AT91_XDMAC_DT_PERID(1))>; 759 dma-names = "tx", "rx"; 760 atmel,fifo-size = <16>; 761 status = "disabled"; 762 }; 763 }; 764 765 flx1: flexcom@f8020000 { 766 compatible = "microchip,sam9x7-flexcom", "atmel,sama5d2-flexcom"; 767 reg = <0xf8020000 0x200>; 768 ranges = <0x0 0xf8020000 0x800>; 769 #address-cells = <1>; 770 #size-cells = <1>; 771 clocks = <&pmc PMC_TYPE_PERIPHERAL 6>; 772 status = "disabled"; 773 774 uart1: serial@200 { 775 compatible = "microchip,sam9x7-usart", "atmel,at91sam9260-usart"; 776 reg = <0x200 0x200>; 777 interrupts = <6 IRQ_TYPE_LEVEL_HIGH 7>; 778 clocks = <&pmc PMC_TYPE_PERIPHERAL 6>; 779 clock-names = "usart"; 780 dmas = <&dma0 781 (AT91_XDMAC_DT_MEM_IF(0) | 782 AT91_XDMAC_DT_PER_IF(1) | 783 AT91_XDMAC_DT_PERID(2))>, 784 <&dma0 785 (AT91_XDMAC_DT_MEM_IF(0) | 786 AT91_XDMAC_DT_PER_IF(1) | 787 AT91_XDMAC_DT_PERID(3))>; 788 dma-names = "tx", "rx"; 789 atmel,use-dma-rx; 790 atmel,use-dma-tx; 791 atmel,fifo-size = <16>; 792 atmel,usart-mode = <AT91_USART_MODE_SERIAL>; 793 status = "disabled"; 794 }; 795 796 spi1: spi@400 { 797 compatible = "microchip,sam9x7-spi", "atmel,at91rm9200-spi"; 798 reg = <0x400 0x200>; 799 interrupts = <6 IRQ_TYPE_LEVEL_HIGH 7>; 800 #address-cells = <1>; 801 #size-cells = <0>; 802 clocks = <&pmc PMC_TYPE_PERIPHERAL 6>; 803 clock-names = "spi_clk"; 804 dmas = <&dma0 805 (AT91_XDMAC_DT_MEM_IF(0) | 806 AT91_XDMAC_DT_PER_IF(1) | 807 AT91_XDMAC_DT_PERID(2))>, 808 <&dma0 809 (AT91_XDMAC_DT_MEM_IF(0) | 810 AT91_XDMAC_DT_PER_IF(1) | 811 AT91_XDMAC_DT_PERID(3))>; 812 dma-names = "tx", "rx"; 813 atmel,fifo-size = <16>; 814 status = "disabled"; 815 }; 816 817 i2c1: i2c@600 { 818 compatible = "microchip,sam9x7-i2c", "microchip,sam9x60-i2c"; 819 reg = <0x600 0x200>; 820 interrupts = <6 IRQ_TYPE_LEVEL_HIGH 7>; 821 #address-cells = <1>; 822 #size-cells = <0>; 823 clocks = <&pmc PMC_TYPE_PERIPHERAL 6>; 824 dmas = <&dma0 825 (AT91_XDMAC_DT_MEM_IF(0) | 826 AT91_XDMAC_DT_PER_IF(1) | 827 AT91_XDMAC_DT_PERID(2))>, 828 <&dma0 829 (AT91_XDMAC_DT_MEM_IF(0) | 830 AT91_XDMAC_DT_PER_IF(1) | 831 AT91_XDMAC_DT_PERID(3))>; 832 dma-names = "tx", "rx"; 833 atmel,fifo-size = <16>; 834 status = "disabled"; 835 }; 836 }; 837 838 flx2: flexcom@f8024000 { 839 compatible = "microchip,sam9x7-flexcom", "atmel,sama5d2-flexcom"; 840 reg = <0xf8024000 0x200>; 841 ranges = <0x0 0xf8024000 0x800>; 842 #address-cells = <1>; 843 #size-cells = <1>; 844 clocks = <&pmc PMC_TYPE_PERIPHERAL 7>; 845 status = "disabled"; 846 847 uart2: serial@200 { 848 compatible = "microchip,sam9x7-usart", "atmel,at91sam9260-usart"; 849 reg = <0x200 0x200>; 850 interrupts = <7 IRQ_TYPE_LEVEL_HIGH 7>; 851 clocks = <&pmc PMC_TYPE_PERIPHERAL 7>; 852 clock-names = "usart"; 853 dmas = <&dma0 854 (AT91_XDMAC_DT_MEM_IF(0) | 855 AT91_XDMAC_DT_PER_IF(1) | 856 AT91_XDMAC_DT_PERID(4))>, 857 <&dma0 858 (AT91_XDMAC_DT_MEM_IF(0) | 859 AT91_XDMAC_DT_PER_IF(1) | 860 AT91_XDMAC_DT_PERID(5))>; 861 dma-names = "tx", "rx"; 862 atmel,use-dma-rx; 863 atmel,use-dma-tx; 864 atmel,fifo-size = <16>; 865 atmel,usart-mode = <AT91_USART_MODE_SERIAL>; 866 status = "disabled"; 867 }; 868 869 spi2: spi@400 { 870 compatible = "microchip,sam9x7-spi", "atmel,at91rm9200-spi"; 871 reg = <0x400 0x200>; 872 interrupts = <7 IRQ_TYPE_LEVEL_HIGH 7>; 873 #address-cells = <1>; 874 #size-cells = <0>; 875 clocks = <&pmc PMC_TYPE_PERIPHERAL 7>; 876 clock-names = "spi_clk"; 877 dmas = <&dma0 878 (AT91_XDMAC_DT_MEM_IF(0) | 879 AT91_XDMAC_DT_PER_IF(1) | 880 AT91_XDMAC_DT_PERID(4))>, 881 <&dma0 882 (AT91_XDMAC_DT_MEM_IF(0) | 883 AT91_XDMAC_DT_PER_IF(1) | 884 AT91_XDMAC_DT_PERID(5))>; 885 dma-names = "tx", "rx"; 886 atmel,fifo-size = <16>; 887 status = "disabled"; 888 }; 889 890 i2c2: i2c@600 { 891 compatible = "microchip,sam9x7-i2c", "microchip,sam9x60-i2c"; 892 reg = <0x600 0x200>; 893 interrupts = <7 IRQ_TYPE_LEVEL_HIGH 7>; 894 #address-cells = <1>; 895 #size-cells = <0>; 896 clocks = <&pmc PMC_TYPE_PERIPHERAL 7>; 897 dmas = <&dma0 898 (AT91_XDMAC_DT_MEM_IF(0) | 899 AT91_XDMAC_DT_PER_IF(1) | 900 AT91_XDMAC_DT_PERID(4))>, 901 <&dma0 902 (AT91_XDMAC_DT_MEM_IF(0) | 903 AT91_XDMAC_DT_PER_IF(1) | 904 AT91_XDMAC_DT_PERID(5))>; 905 dma-names = "tx", "rx"; 906 atmel,fifo-size = <16>; 907 status = "disabled"; 908 }; 909 }; 910 911 flx3: flexcom@f8028000 { 912 compatible = "microchip,sam9x7-flexcom", "atmel,sama5d2-flexcom"; 913 reg = <0xf8028000 0x200>; 914 ranges = <0x0 0xf8028000 0x800>; 915 #address-cells = <1>; 916 #size-cells = <1>; 917 clocks = <&pmc PMC_TYPE_PERIPHERAL 8>; 918 status = "disabled"; 919 920 uart3: serial@200 { 921 compatible = "microchip,sam9x7-usart", "atmel,at91sam9260-usart"; 922 reg = <0x200 0x200>; 923 interrupts = <8 IRQ_TYPE_LEVEL_HIGH 7>; 924 clocks = <&pmc PMC_TYPE_PERIPHERAL 8>; 925 clock-names = "usart"; 926 dmas = <&dma0 927 (AT91_XDMAC_DT_MEM_IF(0) | 928 AT91_XDMAC_DT_PER_IF(1) | 929 AT91_XDMAC_DT_PERID(6))>, 930 <&dma0 931 (AT91_XDMAC_DT_MEM_IF(0) | 932 AT91_XDMAC_DT_PER_IF(1) | 933 AT91_XDMAC_DT_PERID(7))>; 934 dma-names = "tx", "rx"; 935 atmel,use-dma-rx; 936 atmel,use-dma-tx; 937 atmel,fifo-size = <16>; 938 atmel,usart-mode = <AT91_USART_MODE_SERIAL>; 939 status = "disabled"; 940 }; 941 942 spi3: spi@400 { 943 compatible = "microchip,sam9x7-spi", "atmel,at91rm9200-spi"; 944 reg = <0x400 0x200>; 945 interrupts = <8 IRQ_TYPE_LEVEL_HIGH 7>; 946 #address-cells = <1>; 947 #size-cells = <0>; 948 clocks = <&pmc PMC_TYPE_PERIPHERAL 8>; 949 clock-names = "spi_clk"; 950 dmas = <&dma0 951 (AT91_XDMAC_DT_MEM_IF(0) | 952 AT91_XDMAC_DT_PER_IF(1) | 953 AT91_XDMAC_DT_PERID(6))>, 954 <&dma0 955 (AT91_XDMAC_DT_MEM_IF(0) | 956 AT91_XDMAC_DT_PER_IF(1) | 957 AT91_XDMAC_DT_PERID(7))>; 958 dma-names = "tx", "rx"; 959 atmel,fifo-size = <16>; 960 status = "disabled"; 961 }; 962 963 i2c3: i2c@600 { 964 compatible = "microchip,sam9x7-i2c", "microchip,sam9x60-i2c"; 965 reg = <0x600 0x200>; 966 interrupts = <8 IRQ_TYPE_LEVEL_HIGH 7>; 967 #address-cells = <1>; 968 #size-cells = <0>; 969 clocks = <&pmc PMC_TYPE_PERIPHERAL 8>; 970 dmas = <&dma0 971 (AT91_XDMAC_DT_MEM_IF(0) | 972 AT91_XDMAC_DT_PER_IF(1) | 973 AT91_XDMAC_DT_PERID(6))>, 974 <&dma0 975 (AT91_XDMAC_DT_MEM_IF(0) | 976 AT91_XDMAC_DT_PER_IF(1) | 977 AT91_XDMAC_DT_PERID(7))>; 978 dma-names = "tx", "rx"; 979 atmel,fifo-size = <16>; 980 status = "disabled"; 981 }; 982 }; 983 984 gmac: ethernet@f802c000 { 985 compatible = "microchip,sam9x7-gem", "microchip,sama7g5-gem"; 986 reg = <0xf802c000 0x1000>; 987 interrupts = <24 IRQ_TYPE_LEVEL_HIGH 3>, /* Queue 0 */ 988 <60 IRQ_TYPE_LEVEL_HIGH 3>, /* Queue 1 */ 989 <61 IRQ_TYPE_LEVEL_HIGH 3>, /* Queue 2 */ 990 <62 IRQ_TYPE_LEVEL_HIGH 3>, /* Queue 3 */ 991 <63 IRQ_TYPE_LEVEL_HIGH 3>, /* Queue 4 */ 992 <64 IRQ_TYPE_LEVEL_HIGH 3>; /* Queue 5 */ 993 clocks = <&pmc PMC_TYPE_PERIPHERAL 24>, <&pmc PMC_TYPE_PERIPHERAL 24>, <&pmc PMC_TYPE_GCK 24>, <&pmc PMC_TYPE_GCK 67>; 994 clock-names = "hclk", "pclk", "tx_clk", "tsu_clk"; 995 assigned-clocks = <&pmc PMC_TYPE_GCK 67>; 996 assigned-clock-rates = <266666666>; 997 status = "disabled"; 998 }; 999 1000 pwm0: pwm@f8034000 { 1001 compatible = "microchip,sam9x7-pwm", "microchip,sam9x60-pwm"; 1002 reg = <0xf8034000 0x300>; 1003 interrupts = <18 IRQ_TYPE_LEVEL_HIGH 4>; 1004 clocks = <&pmc PMC_TYPE_PERIPHERAL 18>; 1005 #pwm-cells = <3>; 1006 status = "disabled"; 1007 }; 1008 1009 hlcdc: hlcdc@f8038000 { 1010 compatible = "microchip,sam9x75-xlcdc"; 1011 reg = <0xf8038000 0x4000>; 1012 interrupts = <25 IRQ_TYPE_LEVEL_HIGH 0>; 1013 clocks = <&pmc PMC_TYPE_PERIPHERAL 25>, <&pmc PMC_TYPE_GCK 25>, <&clk32k 1>; 1014 clock-names = "periph_clk", "sys_clk", "slow_clk"; 1015 status = "disabled"; 1016 1017 display-controller { 1018 compatible = "atmel,hlcdc-display-controller"; 1019 #address-cells = <1>; 1020 #size-cells = <0>; 1021 1022 port@0 { 1023 reg = <0>; 1024 #address-cells = <1>; 1025 #size-cells = <0>; 1026 }; 1027 }; 1028 1029 pwm { 1030 compatible = "atmel,hlcdc-pwm"; 1031 #pwm-cells = <3>; 1032 }; 1033 }; 1034 1035 flx9: flexcom@f8040000 { 1036 compatible = "microchip,sam9x7-flexcom", "atmel,sama5d2-flexcom"; 1037 reg = <0xf8040000 0x200>; 1038 ranges = <0x0 0xf8040000 0x800>; 1039 #address-cells = <1>; 1040 #size-cells = <1>; 1041 clocks = <&pmc PMC_TYPE_PERIPHERAL 15>; 1042 status = "disabled"; 1043 1044 uart9: serial@200 { 1045 compatible = "microchip,sam9x7-usart", "atmel,at91sam9260-usart"; 1046 reg = <0x200 0x200>; 1047 interrupts = <15 IRQ_TYPE_LEVEL_HIGH 7>; 1048 clocks = <&pmc PMC_TYPE_PERIPHERAL 15>; 1049 clock-names = "usart"; 1050 dmas = <&dma0 1051 (AT91_XDMAC_DT_MEM_IF(0) | 1052 AT91_XDMAC_DT_PER_IF(1) | 1053 AT91_XDMAC_DT_PERID(18))>, 1054 <&dma0 1055 (AT91_XDMAC_DT_MEM_IF(0) | 1056 AT91_XDMAC_DT_PER_IF(1) | 1057 AT91_XDMAC_DT_PERID(19))>; 1058 dma-names = "tx", "rx"; 1059 atmel,use-dma-rx; 1060 atmel,use-dma-tx; 1061 atmel,fifo-size = <16>; 1062 atmel,usart-mode = <AT91_USART_MODE_SERIAL>; 1063 status = "disabled"; 1064 }; 1065 1066 i2c9: i2c@600 { 1067 compatible = "microchip,sam9x7-i2c", "microchip,sam9x60-i2c"; 1068 reg = <0x600 0x200>; 1069 interrupts = <15 IRQ_TYPE_LEVEL_HIGH 7>; 1070 #address-cells = <1>; 1071 #size-cells = <0>; 1072 clocks = <&pmc PMC_TYPE_PERIPHERAL 15>; 1073 dmas = <&dma0 1074 (AT91_XDMAC_DT_MEM_IF(0) | 1075 AT91_XDMAC_DT_PER_IF(1) | 1076 AT91_XDMAC_DT_PERID(18))>, 1077 <&dma0 1078 (AT91_XDMAC_DT_MEM_IF(0) | 1079 AT91_XDMAC_DT_PER_IF(1) | 1080 AT91_XDMAC_DT_PERID(19))>; 1081 dma-names = "tx", "rx"; 1082 atmel,fifo-size = <16>; 1083 status = "disabled"; 1084 }; 1085 }; 1086 1087 flx10: flexcom@f8044000 { 1088 compatible = "microchip,sam9x7-flexcom", "atmel,sama5d2-flexcom"; 1089 reg = <0xf8044000 0x200>; 1090 ranges = <0x0 0xf8044000 0x800>; 1091 #address-cells = <1>; 1092 #size-cells = <1>; 1093 clocks = <&pmc PMC_TYPE_PERIPHERAL 16>; 1094 status = "disabled"; 1095 1096 uart10: serial@200 { 1097 compatible = "microchip,sam9x7-usart", "atmel,at91sam9260-usart"; 1098 reg = <0x200 0x200>; 1099 interrupts = <16 IRQ_TYPE_LEVEL_HIGH 7>; 1100 clocks = <&pmc PMC_TYPE_PERIPHERAL 16>; 1101 clock-names = "usart"; 1102 dmas = <&dma0 1103 (AT91_XDMAC_DT_MEM_IF(0) | 1104 AT91_XDMAC_DT_PER_IF(1) | 1105 AT91_XDMAC_DT_PERID(20))>, 1106 <&dma0 1107 (AT91_XDMAC_DT_MEM_IF(0) | 1108 AT91_XDMAC_DT_PER_IF(1) | 1109 AT91_XDMAC_DT_PERID(21))>; 1110 dma-names = "tx", "rx"; 1111 atmel,use-dma-rx; 1112 atmel,use-dma-tx; 1113 atmel,fifo-size = <16>; 1114 atmel,usart-mode = <AT91_USART_MODE_SERIAL>; 1115 status = "disabled"; 1116 }; 1117 1118 i2c10: i2c@600 { 1119 compatible = "microchip,sam9x7-i2c", "microchip,sam9x60-i2c"; 1120 reg = <0x600 0x200>; 1121 interrupts = <16 IRQ_TYPE_LEVEL_HIGH 7>; 1122 #address-cells = <1>; 1123 #size-cells = <0>; 1124 clocks = <&pmc PMC_TYPE_PERIPHERAL 16>; 1125 dmas = <&dma0 1126 (AT91_XDMAC_DT_MEM_IF(0) | 1127 AT91_XDMAC_DT_PER_IF(1) | 1128 AT91_XDMAC_DT_PERID(20))>, 1129 <&dma0 1130 (AT91_XDMAC_DT_MEM_IF(0) | 1131 AT91_XDMAC_DT_PER_IF(1) | 1132 AT91_XDMAC_DT_PERID(21))>; 1133 dma-names = "tx", "rx"; 1134 atmel,fifo-size = <16>; 1135 status = "disabled"; 1136 }; 1137 }; 1138 1139 lvds_controller: lvds-controller@f8060000 { 1140 compatible = "microchip,sam9x75-lvds"; 1141 reg = <0xf8060000 0x100>; 1142 interrupts = <56 IRQ_TYPE_LEVEL_HIGH 0>; 1143 clocks = <&pmc PMC_TYPE_PERIPHERAL 56>; 1144 clock-names = "pclk"; 1145 status = "disabled"; 1146 }; 1147 1148 matrix: matrix@ffffde00 { 1149 compatible = "microchip,sam9x7-matrix", "atmel,at91sam9x5-matrix", "syscon"; 1150 reg = <0xffffde00 0x200>; 1151 }; 1152 1153 pmecc: ecc-engine@ffffe000 { 1154 compatible = "microchip,sam9x7-pmecc", "atmel,at91sam9g45-pmecc"; 1155 reg = <0xffffe000 0x300>, <0xffffe600 0x100>; 1156 }; 1157 1158 mpddrc: mpddrc@ffffe800 { 1159 compatible = "microchip,sam9x7-ddramc", "atmel,sama5d3-ddramc"; 1160 reg = <0xffffe800 0x200>; 1161 clocks = <&pmc PMC_TYPE_SYSTEM 2>, <&pmc PMC_TYPE_CORE PMC_MCK>; 1162 clock-names = "ddrck", "mpddr"; 1163 }; 1164 1165 smc: smc@ffffea00 { 1166 compatible = "microchip,sam9x7-smc", "atmel,at91sam9260-smc", "syscon"; 1167 reg = <0xffffea00 0x100>; 1168 }; 1169 1170 aic: interrupt-controller@fffff100 { 1171 compatible = "microchip,sam9x7-aic"; 1172 reg = <0xfffff100 0x100>; 1173 #interrupt-cells = <3>; 1174 interrupt-controller; 1175 atmel,external-irqs = <31>; 1176 }; 1177 1178 dbgu: serial@fffff200 { 1179 compatible = "microchip,sam9x7-dbgu", "atmel,at91sam9260-dbgu", "microchip,sam9x7-usart", "atmel,at91sam9260-usart"; 1180 reg = <0xfffff200 0x200>; 1181 interrupts = <47 IRQ_TYPE_LEVEL_HIGH 7>; 1182 clocks = <&pmc PMC_TYPE_PERIPHERAL 47>; 1183 clock-names = "usart"; 1184 dmas = <&dma0 1185 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 1186 AT91_XDMAC_DT_PERID(28))>, 1187 <&dma0 1188 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 1189 AT91_XDMAC_DT_PERID(29))>; 1190 dma-names = "tx", "rx"; 1191 atmel,usart-mode = <AT91_USART_MODE_SERIAL>; 1192 status = "disabled"; 1193 }; 1194 1195 pinctrl: pinctrl@fffff400 { 1196 compatible = "microchip,sam9x7-pinctrl", "microchip,sam9x60-pinctrl", "simple-mfd"; 1197 ranges = <0xfffff400 0xfffff400 0x800>; 1198 #address-cells = <1>; 1199 #size-cells = <1>; 1200 1201 /* mux-mask corresponding to sam9x7 SoC in TFBGA228L package */ 1202 atmel,mux-mask = < 1203 /* A B C D */ 1204 0xffffffff 0xffffefc0 0xc0ffd000 0x00000000 /* pioA */ 1205 0x07ffffff 0x0805fe7f 0x01ff9f81 0x06078000 /* pioB */ 1206 0xffffffff 0x07dfffff 0xfa3fffff 0x00000000 /* pioC */ 1207 0x00003fff 0x00003fe0 0x0000003f 0x00000000 /* pioD */ 1208 >; 1209 1210 pioA: gpio@fffff400 { 1211 compatible = "microchip,sam9x7-gpio", "microchip,sam9x60-gpio", "atmel,at91rm9200-gpio"; 1212 reg = <0xfffff400 0x200>; 1213 interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>; 1214 #interrupt-cells = <2>; 1215 interrupt-controller; 1216 #gpio-cells = <2>; 1217 gpio-controller; 1218 clocks = <&pmc PMC_TYPE_PERIPHERAL 2>; 1219 }; 1220 1221 pioB: gpio@fffff600 { 1222 compatible = "microchip,sam9x7-gpio", "microchip,sam9x60-gpio", "atmel,at91rm9200-gpio"; 1223 reg = <0xfffff600 0x200>; 1224 interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>; 1225 #interrupt-cells = <2>; 1226 interrupt-controller; 1227 #gpio-cells = <2>; 1228 gpio-controller; 1229 #gpio-lines = <27>; 1230 clocks = <&pmc PMC_TYPE_PERIPHERAL 3>; 1231 }; 1232 1233 pioC: gpio@fffff800 { 1234 compatible = "microchip,sam9x7-gpio", "microchip,sam9x60-gpio", "atmel,at91rm9200-gpio"; 1235 reg = <0xfffff800 0x200>; 1236 interrupts = <4 IRQ_TYPE_LEVEL_HIGH 1>; 1237 #interrupt-cells = <2>; 1238 interrupt-controller; 1239 #gpio-cells = <2>; 1240 gpio-controller; 1241 clocks = <&pmc PMC_TYPE_PERIPHERAL 4>; 1242 }; 1243 1244 pioD: gpio@fffffa00 { 1245 compatible = "microchip,sam9x7-gpio", "microchip,sam9x60-gpio", "atmel,at91rm9200-gpio"; 1246 reg = <0xfffffa00 0x200>; 1247 interrupts = <44 IRQ_TYPE_LEVEL_HIGH 1>; 1248 #interrupt-cells = <2>; 1249 interrupt-controller; 1250 #gpio-cells = <2>; 1251 gpio-controller; 1252 #gpio-lines = <22>; 1253 clocks = <&pmc PMC_TYPE_PERIPHERAL 44>; 1254 }; 1255 }; 1256 1257 pmc: clock-controller@fffffc00 { 1258 compatible = "microchip,sam9x7-pmc", "syscon"; 1259 reg = <0xfffffc00 0x200>; 1260 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; 1261 #clock-cells = <2>; 1262 clocks = <&clk32k 1>, <&clk32k 0>, <&main_xtal>; 1263 clock-names = "td_slck", "md_slck", "main_xtal"; 1264 }; 1265 1266 reset_controller: reset-controller@fffffe00 { 1267 compatible = "microchip,sam9x7-rstc", "microchip,sam9x60-rstc"; 1268 reg = <0xfffffe00 0x10>; 1269 clocks = <&clk32k 0>; 1270 }; 1271 1272 poweroff: poweroff@fffffe10 { 1273 compatible = "microchip,sam9x7-shdwc", "microchip,sam9x60-shdwc"; 1274 reg = <0xfffffe10 0x10>; 1275 #address-cells = <1>; 1276 #size-cells = <0>; 1277 clocks = <&clk32k 0>; 1278 atmel,wakeup-rtc-timer; 1279 atmel,wakeup-rtt-timer; 1280 status = "disabled"; 1281 }; 1282 1283 rtt: rtc@fffffe20 { 1284 compatible = "microchip,sam9x7-rtt", "atmel,at91sam9260-rtt"; 1285 reg = <0xfffffe20 0x20>; 1286 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; 1287 clocks = <&clk32k 0>; 1288 }; 1289 1290 clk32k: clock-controller@fffffe50 { 1291 compatible = "microchip,sam9x7-sckc", "microchip,sam9x60-sckc"; 1292 reg = <0xfffffe50 0x4>; 1293 clocks = <&slow_xtal>; 1294 #clock-cells = <1>; 1295 }; 1296 1297 gpbr: syscon@fffffe60 { 1298 compatible = "microchip,sam9x7-gpbr", "atmel,at91sam9260-gpbr", "syscon"; 1299 reg = <0xfffffe60 0x10>; 1300 }; 1301 1302 rtc: rtc@fffffea8 { 1303 compatible = "microchip,sam9x7-rtc", "microchip,sam9x60-rtc"; 1304 reg = <0xfffffea8 0x100>; 1305 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; 1306 clocks = <&clk32k 0>; 1307 }; 1308 1309 watchdog: watchdog@ffffff80 { 1310 compatible = "microchip,sam9x7-wdt", "microchip,sam9x60-wdt"; 1311 reg = <0xffffff80 0x24>; 1312 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; 1313 status = "disabled"; 1314 }; 1315 }; 1316};
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