mt7623.dtsi

   1// SPDX-License-Identifier: GPL-2.0
   2/*
   3 * Copyright (c) 2017-2018 MediaTek Inc.
   4 * Author: John Crispin <john@phrozen.org>
   5 *	   Sean Wang <sean.wang@mediatek.com>
   6 *	   Ryder Lee <ryder.lee@mediatek.com>
   7 *
   8 */
   9
  10#include <dt-bindings/interrupt-controller/irq.h>
  11#include <dt-bindings/interrupt-controller/arm-gic.h>
  12#include <dt-bindings/clock/mt2701-clk.h>
  13#include <dt-bindings/pinctrl/mt7623-pinfunc.h>
  14#include <dt-bindings/power/mt2701-power.h>
  15#include <dt-bindings/gpio/gpio.h>
  16#include <dt-bindings/phy/phy.h>
  17#include <dt-bindings/reset/mt2701-resets.h>
  18#include <dt-bindings/thermal/thermal.h>
  19
  20/ {
  21	compatible = "mediatek,mt7623";
  22	interrupt-parent = <&sysirq>;
  23	#address-cells = <2>;
  24	#size-cells = <2>;
  25
  26	cpu_opp_table: opp-table {
  27		compatible = "operating-points-v2";
  28		opp-shared;
  29
  30		opp-98000000 {
  31			opp-hz = /bits/ 64 <98000000>;
  32			opp-microvolt = <1050000>;
  33		};
  34
  35		opp-198000000 {
  36			opp-hz = /bits/ 64 <198000000>;
  37			opp-microvolt = <1050000>;
  38		};
  39
  40		opp-398000000 {
  41			opp-hz = /bits/ 64 <398000000>;
  42			opp-microvolt = <1050000>;
  43		};
  44
  45		opp-598000000 {
  46			opp-hz = /bits/ 64 <598000000>;
  47			opp-microvolt = <1050000>;
  48		};
  49
  50		opp-747500000 {
  51			opp-hz = /bits/ 64 <747500000>;
  52			opp-microvolt = <1050000>;
  53		};
  54
  55		opp-1040000000 {
  56			opp-hz = /bits/ 64 <1040000000>;
  57			opp-microvolt = <1150000>;
  58		};
  59
  60		opp-1196000000 {
  61			opp-hz = /bits/ 64 <1196000000>;
  62			opp-microvolt = <1200000>;
  63		};
  64
  65		opp-1300000000 {
  66			opp-hz = /bits/ 64 <1300000000>;
  67			opp-microvolt = <1300000>;
  68		};
  69	};
  70
  71	cpus {
  72		#address-cells = <1>;
  73		#size-cells = <0>;
  74		enable-method = "mediatek,mt6589-smp";
  75
  76		cpu0: cpu@0 {
  77			device_type = "cpu";
  78			compatible = "arm,cortex-a7";
  79			reg = <0x0>;
  80			clocks = <&infracfg CLK_INFRA_CPUSEL>,
  81				 <&apmixedsys CLK_APMIXED_MAINPLL>;
  82			clock-names = "cpu", "intermediate";
  83			operating-points-v2 = <&cpu_opp_table>;
  84			#cooling-cells = <2>;
  85			clock-frequency = <1300000000>;
  86		};
  87
  88		cpu1: cpu@1 {
  89			device_type = "cpu";
  90			compatible = "arm,cortex-a7";
  91			reg = <0x1>;
  92			clocks = <&infracfg CLK_INFRA_CPUSEL>,
  93				 <&apmixedsys CLK_APMIXED_MAINPLL>;
  94			clock-names = "cpu", "intermediate";
  95			operating-points-v2 = <&cpu_opp_table>;
  96			#cooling-cells = <2>;
  97			clock-frequency = <1300000000>;
  98		};
  99
 100		cpu2: cpu@2 {
 101			device_type = "cpu";
 102			compatible = "arm,cortex-a7";
 103			reg = <0x2>;
 104			clocks = <&infracfg CLK_INFRA_CPUSEL>,
 105				 <&apmixedsys CLK_APMIXED_MAINPLL>;
 106			clock-names = "cpu", "intermediate";
 107			operating-points-v2 = <&cpu_opp_table>;
 108			#cooling-cells = <2>;
 109			clock-frequency = <1300000000>;
 110		};
 111
 112		cpu3: cpu@3 {
 113			device_type = "cpu";
 114			compatible = "arm,cortex-a7";
 115			reg = <0x3>;
 116			clocks = <&infracfg CLK_INFRA_CPUSEL>,
 117				 <&apmixedsys CLK_APMIXED_MAINPLL>;
 118			clock-names = "cpu", "intermediate";
 119			operating-points-v2 = <&cpu_opp_table>;
 120			#cooling-cells = <2>;
 121			clock-frequency = <1300000000>;
 122		};
 123	};
 124
 125	pmu {
 126		compatible = "arm,cortex-a7-pmu";
 127		interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_LOW>,
 128			     <GIC_SPI 5 IRQ_TYPE_LEVEL_LOW>,
 129			     <GIC_SPI 6 IRQ_TYPE_LEVEL_LOW>,
 130			     <GIC_SPI 7 IRQ_TYPE_LEVEL_LOW>;
 131		interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
 132	};
 133
 134	system_clk: dummy13m {
 135		compatible = "fixed-clock";
 136		clock-frequency = <13000000>;
 137		#clock-cells = <0>;
 138	};
 139
 140	rtc32k: oscillator-1 {
 141		compatible = "fixed-clock";
 142		#clock-cells = <0>;
 143		clock-frequency = <32000>;
 144		clock-output-names = "rtc32k";
 145	};
 146
 147	clk26m: oscillator-0 {
 148		compatible = "fixed-clock";
 149		#clock-cells = <0>;
 150		clock-frequency = <26000000>;
 151		clock-output-names = "clk26m";
 152	};
 153
 154	thermal-zones {
 155			cpu_thermal: cpu-thermal {
 156				polling-delay-passive = <1000>;
 157				polling-delay = <1000>;
 158
 159				thermal-sensors = <&thermal 0>;
 160
 161				trips {
 162					cpu_passive: cpu-passive {
 163						temperature = <57000>;
 164						hysteresis = <2000>;
 165						type = "passive";
 166					};
 167
 168					cpu_active: cpu-active {
 169						temperature = <67000>;
 170						hysteresis = <2000>;
 171						type = "active";
 172					};
 173
 174					cpu_hot: cpu-hot {
 175						temperature = <87000>;
 176						hysteresis = <2000>;
 177						type = "hot";
 178					};
 179
 180					cpu-crit {
 181						temperature = <107000>;
 182						hysteresis = <2000>;
 183						type = "critical";
 184					};
 185				};
 186
 187			cooling-maps {
 188				map0 {
 189					trip = <&cpu_passive>;
 190					cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 191							 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 192							 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 193							 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 194				};
 195
 196				map1 {
 197					trip = <&cpu_active>;
 198					cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 199							 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 200							 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 201							 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 202				};
 203
 204				map2 {
 205					trip = <&cpu_hot>;
 206					cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 207							 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 208							 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 209							 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 210				};
 211			};
 212		};
 213	};
 214
 215	timer {
 216		compatible = "arm,armv7-timer";
 217		interrupt-parent = <&gic>;
 218		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 219			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 220			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 221			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 222		clock-frequency = <13000000>;
 223		arm,cpu-registers-not-fw-configured;
 224	};
 225
 226	topckgen: syscon@10000000 {
 227		compatible = "mediatek,mt7623-topckgen",
 228			     "mediatek,mt2701-topckgen",
 229			     "syscon";
 230		reg = <0 0x10000000 0 0x1000>;
 231		#clock-cells = <1>;
 232	};
 233
 234	infracfg: syscon@10001000 {
 235		compatible = "mediatek,mt7623-infracfg",
 236			     "mediatek,mt2701-infracfg",
 237			     "syscon";
 238		reg = <0 0x10001000 0 0x1000>;
 239		#clock-cells = <1>;
 240		#reset-cells = <1>;
 241	};
 242
 243	pericfg: syscon@10003000 {
 244		compatible = "mediatek,mt7623-pericfg",
 245			      "mediatek,mt2701-pericfg",
 246			      "syscon";
 247		reg = <0 0x10003000 0 0x1000>;
 248		#clock-cells = <1>;
 249		#reset-cells = <1>;
 250	};
 251
 252	pio: pinctrl@10005000 {
 253		compatible = "mediatek,mt7623-pinctrl";
 254		reg = <0 0x1000b000 0 0x1000>;
 255		mediatek,pctl-regmap = <&syscfg_pctl_a>;
 256		gpio-controller;
 257		#gpio-cells = <2>;
 258		interrupt-controller;
 259		interrupt-parent = <&gic>;
 260		#interrupt-cells = <2>;
 261		interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
 262			     <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
 263	};
 264
 265	syscfg_pctl_a: syscfg@10005000 {
 266		compatible = "mediatek,mt7623-pctl-a-syscfg", "syscon";
 267		reg = <0 0x10005000 0 0x1000>;
 268	};
 269
 270	scpsys: power-controller@10006000 {
 271		compatible = "mediatek,mt7623-scpsys",
 272			     "mediatek,mt2701-scpsys",
 273			     "syscon";
 274		#power-domain-cells = <1>;
 275		reg = <0 0x10006000 0 0x1000>;
 276		infracfg = <&infracfg>;
 277		clocks = <&topckgen CLK_TOP_MM_SEL>,
 278			 <&topckgen CLK_TOP_MFG_SEL>,
 279			 <&topckgen CLK_TOP_ETHIF_SEL>;
 280		clock-names = "mm", "mfg", "ethif";
 281	};
 282
 283	watchdog: watchdog@10007000 {
 284		compatible = "mediatek,mt7623-wdt",
 285			     "mediatek,mt6589-wdt";
 286		reg = <0 0x10007000 0 0x100>;
 287	};
 288
 289	timer: timer@10008000 {
 290		compatible = "mediatek,mt7623-timer",
 291			     "mediatek,mt6577-timer";
 292		reg = <0 0x10008000 0 0x80>;
 293		interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_LOW>;
 294		clocks = <&system_clk>, <&rtc32k>;
 295		clock-names = "system-clk", "rtc-clk";
 296	};
 297
 298	pwrap: pwrap@1000d000 {
 299		compatible = "mediatek,mt7623-pwrap",
 300			     "mediatek,mt2701-pwrap";
 301		reg = <0 0x1000d000 0 0x1000>;
 302		reg-names = "pwrap";
 303		interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
 304		resets = <&infracfg MT2701_INFRA_PMIC_WRAP_RST>;
 305		reset-names = "pwrap";
 306		clocks = <&infracfg CLK_INFRA_PMICSPI>,
 307			 <&infracfg CLK_INFRA_PMICWRAP>;
 308		clock-names = "spi", "wrap";
 309	};
 310
 311	cir: ir-receiver@10013000 {
 312		compatible = "mediatek,mt7623-cir";
 313		reg = <0 0x10013000 0 0x1000>;
 314		interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_LOW>;
 315		clocks = <&infracfg CLK_INFRA_IRRX>;
 316		clock-names = "clk";
 317		status = "disabled";
 318	};
 319
 320	sysirq: interrupt-controller@10200100 {
 321		compatible = "mediatek,mt7623-sysirq",
 322			     "mediatek,mt6577-sysirq";
 323		interrupt-controller;
 324		#interrupt-cells = <3>;
 325		interrupt-parent = <&gic>;
 326		reg = <0 0x10200100 0 0x1c>;
 327	};
 328
 329	efuse: efuse@10206000 {
 330		compatible = "mediatek,mt7623-efuse",
 331			     "mediatek,mt8173-efuse";
 332		reg = <0 0x10206000 0 0x1000>;
 333		#address-cells = <1>;
 334		#size-cells = <1>;
 335		thermal_calibration_data: calib@424 {
 336			reg = <0x424 0xc>;
 337		};
 338	};
 339
 340	apmixedsys: syscon@10209000 {
 341		compatible = "mediatek,mt7623-apmixedsys",
 342			     "mediatek,mt2701-apmixedsys",
 343			     "syscon";
 344		reg = <0 0x10209000 0 0x1000>;
 345		#clock-cells = <1>;
 346	};
 347
 348	rng: rng@1020f000 {
 349		compatible = "mediatek,mt7623-rng";
 350		reg = <0 0x1020f000 0 0x1000>;
 351		clocks = <&infracfg CLK_INFRA_TRNG>;
 352		clock-names = "rng";
 353	};
 354
 355	gic: interrupt-controller@10211000 {
 356		compatible = "arm,cortex-a7-gic";
 357		interrupt-controller;
 358		#interrupt-cells = <3>;
 359		interrupt-parent = <&gic>;
 360		reg = <0 0x10211000 0 0x1000>,
 361		      <0 0x10212000 0 0x2000>,
 362		      <0 0x10214000 0 0x2000>,
 363		      <0 0x10216000 0 0x2000>;
 364	};
 365
 366	auxadc: adc@11001000 {
 367		compatible = "mediatek,mt7623-auxadc",
 368			     "mediatek,mt2701-auxadc";
 369		reg = <0 0x11001000 0 0x1000>;
 370		clocks = <&pericfg CLK_PERI_AUXADC>;
 371		clock-names = "main";
 372		#io-channel-cells = <1>;
 373	};
 374
 375	uart0: serial@11002000 {
 376		compatible = "mediatek,mt7623-uart",
 377			     "mediatek,mt6577-uart";
 378		reg = <0 0x11002000 0 0x400>;
 379		interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_LOW>;
 380		clocks = <&pericfg CLK_PERI_UART0_SEL>,
 381			 <&pericfg CLK_PERI_UART0>;
 382		clock-names = "baud", "bus";
 383		status = "disabled";
 384	};
 385
 386	uart1: serial@11003000 {
 387		compatible = "mediatek,mt7623-uart",
 388			     "mediatek,mt6577-uart";
 389		reg = <0 0x11003000 0 0x400>;
 390		interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_LOW>;
 391		clocks = <&pericfg CLK_PERI_UART1_SEL>,
 392			 <&pericfg CLK_PERI_UART1>;
 393		clock-names = "baud", "bus";
 394		status = "disabled";
 395	};
 396
 397	uart2: serial@11004000 {
 398		compatible = "mediatek,mt7623-uart",
 399			     "mediatek,mt6577-uart";
 400		reg = <0 0x11004000 0 0x400>;
 401		interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_LOW>;
 402		clocks = <&pericfg CLK_PERI_UART2_SEL>,
 403			 <&pericfg CLK_PERI_UART2>;
 404		clock-names = "baud", "bus";
 405		status = "disabled";
 406	};
 407
 408	uart3: serial@11005000 {
 409		compatible = "mediatek,mt7623-uart",
 410			     "mediatek,mt6577-uart";
 411		reg = <0 0x11005000 0 0x400>;
 412		interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_LOW>;
 413		clocks = <&pericfg CLK_PERI_UART3_SEL>,
 414			 <&pericfg CLK_PERI_UART3>;
 415		clock-names = "baud", "bus";
 416		status = "disabled";
 417	};
 418
 419	pwm: pwm@11006000 {
 420		compatible = "mediatek,mt7623-pwm";
 421		reg = <0 0x11006000 0 0x1000>;
 422		#pwm-cells = <2>;
 423		clocks = <&topckgen CLK_TOP_PWM_SEL>,
 424			 <&pericfg CLK_PERI_PWM>,
 425			 <&pericfg CLK_PERI_PWM1>,
 426			 <&pericfg CLK_PERI_PWM2>,
 427			 <&pericfg CLK_PERI_PWM3>,
 428			 <&pericfg CLK_PERI_PWM4>,
 429			 <&pericfg CLK_PERI_PWM5>;
 430		clock-names = "top", "main", "pwm1", "pwm2",
 431			      "pwm3", "pwm4", "pwm5";
 432		status = "disabled";
 433	};
 434
 435	i2c0: i2c@11007000 {
 436		compatible = "mediatek,mt7623-i2c",
 437			     "mediatek,mt6577-i2c";
 438		reg = <0 0x11007000 0 0x70>,
 439		      <0 0x11000200 0 0x80>;
 440		interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_LOW>;
 441		clock-div = <16>;
 442		clocks = <&pericfg CLK_PERI_I2C0>,
 443			 <&pericfg CLK_PERI_AP_DMA>;
 444		clock-names = "main", "dma";
 445		#address-cells = <1>;
 446		#size-cells = <0>;
 447		status = "disabled";
 448	};
 449
 450	i2c1: i2c@11008000 {
 451		compatible = "mediatek,mt7623-i2c",
 452			     "mediatek,mt6577-i2c";
 453		reg = <0 0x11008000 0 0x70>,
 454		      <0 0x11000280 0 0x80>;
 455		interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_LOW>;
 456		clock-div = <16>;
 457		clocks = <&pericfg CLK_PERI_I2C1>,
 458			 <&pericfg CLK_PERI_AP_DMA>;
 459		clock-names = "main", "dma";
 460		#address-cells = <1>;
 461		#size-cells = <0>;
 462		status = "disabled";
 463	};
 464
 465	i2c2: i2c@11009000 {
 466		compatible = "mediatek,mt7623-i2c",
 467			     "mediatek,mt6577-i2c";
 468		reg = <0 0x11009000 0 0x70>,
 469		      <0 0x11000300 0 0x80>;
 470		interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_LOW>;
 471		clock-div = <16>;
 472		clocks = <&pericfg CLK_PERI_I2C2>,
 473			 <&pericfg CLK_PERI_AP_DMA>;
 474		clock-names = "main", "dma";
 475		#address-cells = <1>;
 476		#size-cells = <0>;
 477		status = "disabled";
 478	};
 479
 480	spi0: spi@1100a000 {
 481		compatible = "mediatek,mt7623-spi",
 482			     "mediatek,mt2701-spi";
 483		#address-cells = <1>;
 484		#size-cells = <0>;
 485		reg = <0 0x1100a000 0 0x100>;
 486		interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_LOW>;
 487		clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
 488			 <&topckgen CLK_TOP_SPI0_SEL>,
 489			 <&pericfg CLK_PERI_SPI0>;
 490		clock-names = "parent-clk", "sel-clk", "spi-clk";
 491		status = "disabled";
 492	};
 493
 494	thermal: thermal@1100b000 {
 495		#thermal-sensor-cells = <1>;
 496		compatible = "mediatek,mt7623-thermal",
 497			     "mediatek,mt2701-thermal";
 498		reg = <0 0x1100b000 0 0x1000>;
 499		interrupts = <0 70 IRQ_TYPE_LEVEL_LOW>;
 500		clocks = <&pericfg CLK_PERI_THERM>, <&pericfg CLK_PERI_AUXADC>;
 501		clock-names = "therm", "auxadc";
 502		resets = <&pericfg MT2701_PERI_THERM_SW_RST>;
 503		reset-names = "therm";
 504		mediatek,auxadc = <&auxadc>;
 505		mediatek,apmixedsys = <&apmixedsys>;
 506		nvmem-cells = <&thermal_calibration_data>;
 507		nvmem-cell-names = "calibration-data";
 508	};
 509
 510	btif: serial@1100c000 {
 511		compatible = "mediatek,mt7623-btif",
 512			     "mediatek,mtk-btif";
 513		reg = <0 0x1100c000 0 0x1000>;
 514		interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_LOW>;
 515		clocks = <&pericfg CLK_PERI_BTIF>;
 516		clock-names = "main";
 517		reg-shift = <2>;
 518		reg-io-width = <4>;
 519		status = "disabled";
 520	};
 521
 522	nandc: nfi@1100d000 {
 523		compatible = "mediatek,mt7623-nfc",
 524			     "mediatek,mt2701-nfc";
 525		reg = <0 0x1100d000 0 0x1000>;
 526		interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_LOW>;
 527		power-domains = <&scpsys MT2701_POWER_DOMAIN_IFR_MSC>;
 528		clocks = <&pericfg CLK_PERI_NFI>,
 529			 <&pericfg CLK_PERI_NFI_PAD>;
 530		clock-names = "nfi_clk", "pad_clk";
 531		status = "disabled";
 532		ecc-engine = <&bch>;
 533		#address-cells = <1>;
 534		#size-cells = <0>;
 535	};
 536
 537	bch: ecc@1100e000 {
 538		compatible = "mediatek,mt7623-ecc",
 539			     "mediatek,mt2701-ecc";
 540		reg = <0 0x1100e000 0 0x1000>;
 541		interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_LOW>;
 542		clocks = <&pericfg CLK_PERI_NFI_ECC>;
 543		clock-names = "nfiecc_clk";
 544		status = "disabled";
 545	};
 546
 547	nor_flash: spi@11014000 {
 548		compatible = "mediatek,mt7623-nor",
 549			     "mediatek,mt8173-nor";
 550		reg = <0 0x11014000 0 0x1000>;
 551		clocks = <&pericfg CLK_PERI_FLASH>,
 552			 <&topckgen CLK_TOP_FLASH_SEL>;
 553		clock-names = "spi", "sf";
 554		#address-cells = <1>;
 555		#size-cells = <0>;
 556		status = "disabled";
 557	};
 558
 559	spi1: spi@11016000 {
 560		compatible = "mediatek,mt7623-spi",
 561			     "mediatek,mt2701-spi";
 562		#address-cells = <1>;
 563		#size-cells = <0>;
 564		reg = <0 0x11016000 0 0x100>;
 565		interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_LOW>;
 566		clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
 567			 <&topckgen CLK_TOP_SPI1_SEL>,
 568			 <&pericfg CLK_PERI_SPI1>;
 569		clock-names = "parent-clk", "sel-clk", "spi-clk";
 570		status = "disabled";
 571	};
 572
 573	spi2: spi@11017000 {
 574		compatible = "mediatek,mt7623-spi",
 575			     "mediatek,mt2701-spi";
 576		#address-cells = <1>;
 577		#size-cells = <0>;
 578		reg = <0 0x11017000 0 0x1000>;
 579		interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_LOW>;
 580		clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
 581			 <&topckgen CLK_TOP_SPI2_SEL>,
 582			 <&pericfg CLK_PERI_SPI2>;
 583		clock-names = "parent-clk", "sel-clk", "spi-clk";
 584		status = "disabled";
 585	};
 586
 587	usb0: usb@11200000 {
 588		compatible = "mediatek,mt7623-musb",
 589			     "mediatek,mtk-musb";
 590		reg = <0 0x11200000 0 0x1000>;
 591		interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_LOW>;
 592		interrupt-names = "mc";
 593		phys = <&u2port2 PHY_TYPE_USB2>;
 594		dr_mode = "otg";
 595		clocks = <&pericfg CLK_PERI_USB0>,
 596			 <&pericfg CLK_PERI_USB0_MCU>,
 597			 <&pericfg CLK_PERI_USB_SLV>;
 598		clock-names = "main","mcu","univpll";
 599		power-domains = <&scpsys MT2701_POWER_DOMAIN_IFR_MSC>;
 600		status = "disabled";
 601	};
 602
 603	u2phy1: t-phy@11210000 {
 604		compatible = "mediatek,mt7623-tphy",
 605			     "mediatek,generic-tphy-v1";
 606		reg = <0 0x11210000 0 0x0800>;
 607		#address-cells = <2>;
 608		#size-cells = <2>;
 609		ranges;
 610		status = "disabled";
 611
 612		u2port2: usb-phy@11210800 {
 613			reg = <0 0x11210800 0 0x0100>;
 614			clocks = <&topckgen CLK_TOP_USB_PHY48M>;
 615			clock-names = "ref";
 616			#phy-cells = <1>;
 617		};
 618	};
 619
 620	audsys: clock-controller@11220000 {
 621		compatible = "mediatek,mt7623-audsys",
 622			     "mediatek,mt2701-audsys",
 623			     "syscon";
 624		reg = <0 0x11220000 0 0x2000>;
 625		#clock-cells = <1>;
 626
 627		afe: audio-controller {
 628			compatible = "mediatek,mt7623-audio",
 629				     "mediatek,mt2701-audio";
 630			interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_LOW>,
 631				      <GIC_SPI 132 IRQ_TYPE_LEVEL_LOW>;
 632			interrupt-names = "afe", "asys";
 633			power-domains = <&scpsys MT2701_POWER_DOMAIN_IFR_MSC>;
 634
 635			clocks = <&infracfg CLK_INFRA_AUDIO>,
 636				 <&topckgen CLK_TOP_AUD_MUX1_SEL>,
 637				 <&topckgen CLK_TOP_AUD_MUX2_SEL>,
 638				 <&topckgen CLK_TOP_AUD_48K_TIMING>,
 639				 <&topckgen CLK_TOP_AUD_44K_TIMING>,
 640				 <&topckgen CLK_TOP_AUD_K1_SRC_SEL>,
 641				 <&topckgen CLK_TOP_AUD_K2_SRC_SEL>,
 642				 <&topckgen CLK_TOP_AUD_K3_SRC_SEL>,
 643				 <&topckgen CLK_TOP_AUD_K4_SRC_SEL>,
 644				 <&topckgen CLK_TOP_AUD_K1_SRC_DIV>,
 645				 <&topckgen CLK_TOP_AUD_K2_SRC_DIV>,
 646				 <&topckgen CLK_TOP_AUD_K3_SRC_DIV>,
 647				 <&topckgen CLK_TOP_AUD_K4_SRC_DIV>,
 648				 <&topckgen CLK_TOP_AUD_I2S1_MCLK>,
 649				 <&topckgen CLK_TOP_AUD_I2S2_MCLK>,
 650				 <&topckgen CLK_TOP_AUD_I2S3_MCLK>,
 651				 <&topckgen CLK_TOP_AUD_I2S4_MCLK>,
 652				 <&audsys CLK_AUD_I2SO1>,
 653				 <&audsys CLK_AUD_I2SO2>,
 654				 <&audsys CLK_AUD_I2SO3>,
 655				 <&audsys CLK_AUD_I2SO4>,
 656				 <&audsys CLK_AUD_I2SIN1>,
 657				 <&audsys CLK_AUD_I2SIN2>,
 658				 <&audsys CLK_AUD_I2SIN3>,
 659				 <&audsys CLK_AUD_I2SIN4>,
 660				 <&audsys CLK_AUD_ASRCO1>,
 661				 <&audsys CLK_AUD_ASRCO2>,
 662				 <&audsys CLK_AUD_ASRCO3>,
 663				 <&audsys CLK_AUD_ASRCO4>,
 664				 <&audsys CLK_AUD_AFE>,
 665				 <&audsys CLK_AUD_AFE_CONN>,
 666				 <&audsys CLK_AUD_A1SYS>,
 667				 <&audsys CLK_AUD_A2SYS>,
 668				 <&audsys CLK_AUD_AFE_MRGIF>;
 669
 670			clock-names = "infra_sys_audio_clk",
 671				      "top_audio_mux1_sel",
 672				      "top_audio_mux2_sel",
 673				      "top_audio_a1sys_hp",
 674				      "top_audio_a2sys_hp",
 675				      "i2s0_src_sel",
 676				      "i2s1_src_sel",
 677				      "i2s2_src_sel",
 678				      "i2s3_src_sel",
 679				      "i2s0_src_div",
 680				      "i2s1_src_div",
 681				      "i2s2_src_div",
 682				      "i2s3_src_div",
 683				      "i2s0_mclk_en",
 684				      "i2s1_mclk_en",
 685				      "i2s2_mclk_en",
 686				      "i2s3_mclk_en",
 687				      "i2so0_hop_ck",
 688				      "i2so1_hop_ck",
 689				      "i2so2_hop_ck",
 690				      "i2so3_hop_ck",
 691				      "i2si0_hop_ck",
 692				      "i2si1_hop_ck",
 693				      "i2si2_hop_ck",
 694				      "i2si3_hop_ck",
 695				      "asrc0_out_ck",
 696				      "asrc1_out_ck",
 697				      "asrc2_out_ck",
 698				      "asrc3_out_ck",
 699				      "audio_afe_pd",
 700				      "audio_afe_conn_pd",
 701				      "audio_a1sys_pd",
 702				      "audio_a2sys_pd",
 703				      "audio_mrgif_pd";
 704
 705			assigned-clocks = <&topckgen CLK_TOP_AUD_MUX1_SEL>,
 706					  <&topckgen CLK_TOP_AUD_MUX2_SEL>,
 707					  <&topckgen CLK_TOP_AUD_MUX1_DIV>,
 708					  <&topckgen CLK_TOP_AUD_MUX2_DIV>;
 709			assigned-clock-parents = <&topckgen CLK_TOP_AUD1PLL_98M>,
 710						 <&topckgen CLK_TOP_AUD2PLL_90M>;
 711			assigned-clock-rates = <0>, <0>, <49152000>, <45158400>;
 712		};
 713	};
 714
 715	mmc0: mmc@11230000 {
 716		compatible = "mediatek,mt7623-mmc",
 717			     "mediatek,mt2701-mmc";
 718		reg = <0 0x11230000 0 0x1000>;
 719		interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_LOW>;
 720		clocks = <&pericfg CLK_PERI_MSDC30_0>,
 721			 <&topckgen CLK_TOP_MSDC30_0_SEL>;
 722		clock-names = "source", "hclk";
 723		status = "disabled";
 724	};
 725
 726	mmc1: mmc@11240000 {
 727		compatible = "mediatek,mt7623-mmc",
 728			     "mediatek,mt2701-mmc";
 729		reg = <0 0x11240000 0 0x1000>;
 730		interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_LOW>;
 731		clocks = <&pericfg CLK_PERI_MSDC30_1>,
 732			 <&topckgen CLK_TOP_MSDC30_1_SEL>;
 733		clock-names = "source", "hclk";
 734		status = "disabled";
 735	};
 736
 737	vdecsys: syscon@16000000 {
 738		compatible = "mediatek,mt7623-vdecsys",
 739			     "mediatek,mt2701-vdecsys",
 740			     "syscon";
 741		reg = <0 0x16000000 0 0x1000>;
 742		#clock-cells = <1>;
 743	};
 744
 745	hifsys: syscon@1a000000 {
 746		compatible = "mediatek,mt7623-hifsys",
 747			     "mediatek,mt2701-hifsys";
 748		reg = <0 0x1a000000 0 0x1000>;
 749		#clock-cells = <1>;
 750		#reset-cells = <1>;
 751	};
 752
 753	pcie: pcie@1a140000 {
 754		compatible = "mediatek,mt7623-pcie";
 755		device_type = "pci";
 756		reg = <0 0x1a140000 0 0x1000>, /* PCIe shared registers */
 757		      <0 0x1a142000 0 0x1000>, /* Port0 registers */
 758		      <0 0x1a143000 0 0x1000>, /* Port1 registers */
 759		      <0 0x1a144000 0 0x1000>; /* Port2 registers */
 760		reg-names = "subsys", "port0", "port1", "port2";
 761		#address-cells = <3>;
 762		#size-cells = <2>;
 763		#interrupt-cells = <1>;
 764		interrupt-map-mask = <0xf800 0 0 0>;
 765		interrupt-map = <0x0000 0 0 0 &sysirq GIC_SPI 193 IRQ_TYPE_LEVEL_LOW>,
 766				<0x0800 0 0 0 &sysirq GIC_SPI 194 IRQ_TYPE_LEVEL_LOW>,
 767				<0x1000 0 0 0 &sysirq GIC_SPI 195 IRQ_TYPE_LEVEL_LOW>;
 768		clocks = <&topckgen CLK_TOP_ETHIF_SEL>,
 769			 <&hifsys CLK_HIFSYS_PCIE0>,
 770			 <&hifsys CLK_HIFSYS_PCIE1>,
 771			 <&hifsys CLK_HIFSYS_PCIE2>;
 772		clock-names = "free_ck", "sys_ck0", "sys_ck1", "sys_ck2";
 773		resets = <&hifsys MT2701_HIFSYS_PCIE0_RST>,
 774			 <&hifsys MT2701_HIFSYS_PCIE1_RST>,
 775			 <&hifsys MT2701_HIFSYS_PCIE2_RST>;
 776		reset-names = "pcie-rst0", "pcie-rst1", "pcie-rst2";
 777		phys = <&pcie0_port PHY_TYPE_PCIE>,
 778		       <&pcie1_port PHY_TYPE_PCIE>,
 779		       <&u3port1 PHY_TYPE_PCIE>;
 780		phy-names = "pcie-phy0", "pcie-phy1", "pcie-phy2";
 781		power-domains = <&scpsys MT2701_POWER_DOMAIN_HIF>;
 782		bus-range = <0x00 0xff>;
 783		status = "disabled";
 784		ranges = <0x81000000 0 0x1a160000 0 0x1a160000 0 0x00010000
 785			  0x83000000 0 0x60000000 0 0x60000000 0 0x10000000>;
 786
 787		pcie@0,0 {
 788			reg = <0x0000 0 0 0 0>;
 789			#address-cells = <3>;
 790			#size-cells = <2>;
 791			#interrupt-cells = <1>;
 792			interrupt-map-mask = <0 0 0 0>;
 793			interrupt-map = <0 0 0 0 &sysirq GIC_SPI 193 IRQ_TYPE_LEVEL_LOW>;
 794			ranges;
 795			status = "disabled";
 796		};
 797
 798		pcie@1,0 {
 799			reg = <0x0800 0 0 0 0>;
 800			#address-cells = <3>;
 801			#size-cells = <2>;
 802			#interrupt-cells = <1>;
 803			interrupt-map-mask = <0 0 0 0>;
 804			interrupt-map = <0 0 0 0 &sysirq GIC_SPI 194 IRQ_TYPE_LEVEL_LOW>;
 805			ranges;
 806			status = "disabled";
 807		};
 808
 809		pcie@2,0 {
 810			reg = <0x1000 0 0 0 0>;
 811			#address-cells = <3>;
 812			#size-cells = <2>;
 813			#interrupt-cells = <1>;
 814			interrupt-map-mask = <0 0 0 0>;
 815			interrupt-map = <0 0 0 0 &sysirq GIC_SPI 195 IRQ_TYPE_LEVEL_LOW>;
 816			ranges;
 817			status = "disabled";
 818		};
 819	};
 820
 821	pcie0_phy: t-phy@1a149000 {
 822		compatible = "mediatek,mt7623-tphy",
 823			     "mediatek,generic-tphy-v1";
 824		reg = <0 0x1a149000 0 0x0700>;
 825		#address-cells = <2>;
 826		#size-cells = <2>;
 827		ranges;
 828		status = "disabled";
 829
 830		pcie0_port: pcie-phy@1a149900 {
 831			reg = <0 0x1a149900 0 0x0700>;
 832			clocks = <&clk26m>;
 833			clock-names = "ref";
 834			#phy-cells = <1>;
 835			status = "okay";
 836		};
 837	};
 838
 839	pcie1_phy: t-phy@1a14a000 {
 840		compatible = "mediatek,mt7623-tphy",
 841			     "mediatek,generic-tphy-v1";
 842		reg = <0 0x1a14a000 0 0x0700>;
 843		#address-cells = <2>;
 844		#size-cells = <2>;
 845		ranges;
 846		status = "disabled";
 847
 848		pcie1_port: pcie-phy@1a14a900 {
 849			reg = <0 0x1a14a900 0 0x0700>;
 850			clocks = <&clk26m>;
 851			clock-names = "ref";
 852			#phy-cells = <1>;
 853			status = "okay";
 854		};
 855	};
 856
 857	usb1: usb@1a1c0000 {
 858		compatible = "mediatek,mt7623-xhci",
 859			     "mediatek,mtk-xhci";
 860		reg = <0 0x1a1c0000 0 0x1000>,
 861		      <0 0x1a1c4700 0 0x0100>;
 862		reg-names = "mac", "ippc";
 863		interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_LOW>;
 864		clocks = <&hifsys CLK_HIFSYS_USB0PHY>,
 865			 <&topckgen CLK_TOP_ETHIF_SEL>;
 866		clock-names = "sys_ck", "ref_ck";
 867		power-domains = <&scpsys MT2701_POWER_DOMAIN_HIF>;
 868		phys = <&u2port0 PHY_TYPE_USB2>, <&u3port0 PHY_TYPE_USB3>;
 869		status = "disabled";
 870	};
 871
 872	u3phy1: t-phy@1a1c4000 {
 873		compatible = "mediatek,mt7623-tphy",
 874			     "mediatek,generic-tphy-v1";
 875		reg = <0 0x1a1c4000 0 0x0700>;
 876		#address-cells = <2>;
 877		#size-cells = <2>;
 878		ranges;
 879		status = "disabled";
 880
 881		u2port0: usb-phy@1a1c4800 {
 882			reg = <0 0x1a1c4800 0 0x0100>;
 883			clocks = <&topckgen CLK_TOP_USB_PHY48M>;
 884			clock-names = "ref";
 885			#phy-cells = <1>;
 886			status = "okay";
 887		};
 888
 889		u3port0: usb-phy@1a1c4900 {
 890			reg = <0 0x1a1c4900 0 0x0700>;
 891			clocks = <&clk26m>;
 892			clock-names = "ref";
 893			#phy-cells = <1>;
 894			status = "okay";
 895		};
 896	};
 897
 898	usb2: usb@1a240000 {
 899		compatible = "mediatek,mt7623-xhci",
 900			     "mediatek,mtk-xhci";
 901		reg = <0 0x1a240000 0 0x1000>,
 902		      <0 0x1a244700 0 0x0100>;
 903		reg-names = "mac", "ippc";
 904		interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_LOW>;
 905		clocks = <&hifsys CLK_HIFSYS_USB1PHY>,
 906			 <&topckgen CLK_TOP_ETHIF_SEL>;
 907		clock-names = "sys_ck", "ref_ck";
 908		power-domains = <&scpsys MT2701_POWER_DOMAIN_HIF>;
 909		phys = <&u2port1 PHY_TYPE_USB2>, <&u3port1 PHY_TYPE_USB3>;
 910		status = "disabled";
 911	};
 912
 913	u3phy2: t-phy@1a244000 {
 914		compatible = "mediatek,mt7623-tphy",
 915			     "mediatek,generic-tphy-v1";
 916		reg = <0 0x1a244000 0 0x0700>;
 917		#address-cells = <2>;
 918		#size-cells = <2>;
 919		ranges;
 920		status = "disabled";
 921
 922		u2port1: usb-phy@1a244800 {
 923			reg = <0 0x1a244800 0 0x0100>;
 924			clocks = <&topckgen CLK_TOP_USB_PHY48M>;
 925			clock-names = "ref";
 926			#phy-cells = <1>;
 927			status = "okay";
 928		};
 929
 930		u3port1: usb-phy@1a244900 {
 931			reg = <0 0x1a244900 0 0x0700>;
 932			clocks = <&clk26m>;
 933			clock-names = "ref";
 934			#phy-cells = <1>;
 935			status = "okay";
 936		};
 937	};
 938
 939	ethsys: syscon@1b000000 {
 940		compatible = "mediatek,mt7623-ethsys",
 941			     "mediatek,mt2701-ethsys",
 942			     "syscon";
 943		reg = <0 0x1b000000 0 0x1000>;
 944		#clock-cells = <1>;
 945		#reset-cells = <1>;
 946	};
 947
 948	hsdma: dma-controller@1b007000 {
 949		compatible = "mediatek,mt7623-hsdma";
 950		reg = <0 0x1b007000 0 0x1000>;
 951		interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_LOW>;
 952		clocks = <&ethsys CLK_ETHSYS_HSDMA>;
 953		clock-names = "hsdma";
 954		power-domains = <&scpsys MT2701_POWER_DOMAIN_ETH>;
 955		#dma-cells = <1>;
 956	};
 957
 958	eth: ethernet@1b100000 {
 959		compatible = "mediatek,mt7623-eth",
 960			     "mediatek,mt2701-eth",
 961			     "syscon";
 962		reg = <0 0x1b100000 0 0x20000>;
 963		interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_LOW>,
 964			     <GIC_SPI 199 IRQ_TYPE_LEVEL_LOW>,
 965			     <GIC_SPI 198 IRQ_TYPE_LEVEL_LOW>;
 966		clocks = <&topckgen CLK_TOP_ETHIF_SEL>,
 967			 <&ethsys CLK_ETHSYS_ESW>,
 968			 <&ethsys CLK_ETHSYS_GP1>,
 969			 <&ethsys CLK_ETHSYS_GP2>,
 970			 <&apmixedsys CLK_APMIXED_TRGPLL>;
 971		clock-names = "ethif", "esw", "gp1", "gp2", "trgpll";
 972		resets = <&ethsys MT2701_ETHSYS_FE_RST>,
 973			 <&ethsys MT2701_ETHSYS_GMAC_RST>,
 974			 <&ethsys MT2701_ETHSYS_PPE_RST>;
 975		reset-names = "fe", "gmac", "ppe";
 976		power-domains = <&scpsys MT2701_POWER_DOMAIN_ETH>;
 977		mediatek,ethsys = <&ethsys>;
 978		mediatek,pctl = <&syscfg_pctl_a>;
 979		#address-cells = <1>;
 980		#size-cells = <0>;
 981		status = "disabled";
 982
 983		gmac0: mac@0 {
 984			compatible = "mediatek,eth-mac";
 985			reg = <0>;
 986			status = "disabled";
 987		};
 988
 989		gmac1: mac@1 {
 990			compatible = "mediatek,eth-mac";
 991			reg = <1>;
 992			status = "disabled";
 993		};
 994	};
 995
 996	crypto: crypto@1b240000 {
 997		compatible = "mediatek,eip97-crypto";
 998		reg = <0 0x1b240000 0 0x20000>;
 999		interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_LOW>,
1000			     <GIC_SPI 83 IRQ_TYPE_LEVEL_LOW>,
1001			     <GIC_SPI 84 IRQ_TYPE_LEVEL_LOW>,
1002			     <GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>,
1003			     <GIC_SPI 97 IRQ_TYPE_LEVEL_LOW>;
1004		clocks = <&ethsys CLK_ETHSYS_CRYPTO>;
1005		clock-names = "cryp";
1006		power-domains = <&scpsys MT2701_POWER_DOMAIN_ETH>;
1007		status = "disabled";
1008	};
1009
1010	bdpsys: syscon@1c000000 {
1011		compatible = "mediatek,mt7623-bdpsys",
1012			     "mediatek,mt2701-bdpsys",
1013			     "syscon";
1014		reg = <0 0x1c000000 0 0x1000>;
1015		#clock-cells = <1>;
1016	};
1017};
1018
1019&pio {
1020	cir_pins_a:cir-default {
1021		pins-cir {
1022			pinmux = <MT7623_PIN_46_IR_FUNC_IR>;
1023			bias-disable;
1024		};
1025	};
1026
1027	i2c0_pins_a: i2c0-default {
1028		pins-i2c0 {
1029			pinmux = <MT7623_PIN_75_SDA0_FUNC_SDA0>,
1030				 <MT7623_PIN_76_SCL0_FUNC_SCL0>;
1031			bias-disable;
1032		};
1033	};
1034
1035	i2c1_pins_a: i2c1-default {
1036		pin-i2c1 {
1037			pinmux = <MT7623_PIN_57_SDA1_FUNC_SDA1>,
1038				 <MT7623_PIN_58_SCL1_FUNC_SCL1>;
1039			bias-disable;
1040		};
1041	};
1042
1043	i2c1_pins_b: i2c1-alt {
1044		pin-i2c1 {
1045			pinmux = <MT7623_PIN_242_URTS2_FUNC_SCL1>,
1046				 <MT7623_PIN_243_UCTS2_FUNC_SDA1>;
1047			bias-disable;
1048		};
1049	};
1050
1051	i2c2_pins_a: i2c2-default {
1052		pin-i2c2 {
1053			pinmux = <MT7623_PIN_77_SDA2_FUNC_SDA2>,
1054				 <MT7623_PIN_78_SCL2_FUNC_SCL2>;
1055			bias-disable;
1056		};
1057	};
1058
1059	i2c2_pins_b: i2c2-alt {
1060		pin-i2c2 {
1061			pinmux = <MT7623_PIN_122_GPIO122_FUNC_SDA2>,
1062				 <MT7623_PIN_123_HTPLG_FUNC_SCL2>;
1063			bias-disable;
1064		};
1065	};
1066
1067	i2s0_pins_a: i2s0-default {
1068		pin-i2s0 {
1069			pinmux = <MT7623_PIN_49_I2S0_DATA_FUNC_I2S0_DATA>,
1070				 <MT7623_PIN_72_I2S0_DATA_IN_FUNC_I2S0_DATA_IN>,
1071				 <MT7623_PIN_73_I2S0_LRCK_FUNC_I2S0_LRCK>,
1072				 <MT7623_PIN_74_I2S0_BCK_FUNC_I2S0_BCK>,
1073				 <MT7623_PIN_126_I2S0_MCLK_FUNC_I2S0_MCLK>;
1074			drive-strength = <MTK_DRIVE_12mA>;
1075			bias-pull-down;
1076		};
1077	};
1078
1079	i2s1_pins_a: i2s1-default {
1080		pin-i2s1 {
1081			pinmux = <MT7623_PIN_33_I2S1_DATA_FUNC_I2S1_DATA>,
1082				 <MT7623_PIN_34_I2S1_DATA_IN_FUNC_I2S1_DATA_IN>,
1083				 <MT7623_PIN_35_I2S1_BCK_FUNC_I2S1_BCK>,
1084				 <MT7623_PIN_36_I2S1_LRCK_FUNC_I2S1_LRCK>,
1085				 <MT7623_PIN_37_I2S1_MCLK_FUNC_I2S1_MCLK>;
1086			drive-strength = <MTK_DRIVE_12mA>;
1087			bias-pull-down;
1088		};
1089	};
1090
1091	key_pins_a: keys-alt {
1092		pins-keys {
1093			pinmux = <MT7623_PIN_256_GPIO256_FUNC_GPIO256>,
1094				 <MT7623_PIN_257_GPIO257_FUNC_GPIO257> ;
1095			input-enable;
1096		};
1097	};
1098
1099	led_pins_a: leds-alt {
1100		pins-leds {
1101			pinmux = <MT7623_PIN_239_EXT_SDIO0_FUNC_GPIO239>,
1102				 <MT7623_PIN_240_EXT_XCS_FUNC_GPIO240>,
1103				 <MT7623_PIN_241_EXT_SCK_FUNC_GPIO241>;
1104		};
1105	};
1106
1107	mmc0_pins_default: mmc0default {
1108		pins-cmd-dat {
1109			pinmux = <MT7623_PIN_111_MSDC0_DAT7_FUNC_MSDC0_DAT7>,
1110				 <MT7623_PIN_112_MSDC0_DAT6_FUNC_MSDC0_DAT6>,
1111				 <MT7623_PIN_113_MSDC0_DAT5_FUNC_MSDC0_DAT5>,
1112				 <MT7623_PIN_114_MSDC0_DAT4_FUNC_MSDC0_DAT4>,
1113				 <MT7623_PIN_118_MSDC0_DAT3_FUNC_MSDC0_DAT3>,
1114				 <MT7623_PIN_119_MSDC0_DAT2_FUNC_MSDC0_DAT2>,
1115				 <MT7623_PIN_120_MSDC0_DAT1_FUNC_MSDC0_DAT1>,
1116				 <MT7623_PIN_121_MSDC0_DAT0_FUNC_MSDC0_DAT0>,
1117				 <MT7623_PIN_116_MSDC0_CMD_FUNC_MSDC0_CMD>;
1118			input-enable;
1119			bias-pull-up;
1120		};
1121
1122		pins-clk {
1123			pinmux = <MT7623_PIN_117_MSDC0_CLK_FUNC_MSDC0_CLK>;
1124			bias-pull-down;
1125		};
1126
1127		pins-rst {
1128			pinmux = <MT7623_PIN_115_MSDC0_RSTB_FUNC_MSDC0_RSTB>;
1129			bias-pull-up;
1130		};
1131	};
1132
1133	mmc0_pins_uhs: mmc0 {
1134		pins-cmd-dat {
1135			pinmux = <MT7623_PIN_111_MSDC0_DAT7_FUNC_MSDC0_DAT7>,
1136				 <MT7623_PIN_112_MSDC0_DAT6_FUNC_MSDC0_DAT6>,
1137				 <MT7623_PIN_113_MSDC0_DAT5_FUNC_MSDC0_DAT5>,
1138				 <MT7623_PIN_114_MSDC0_DAT4_FUNC_MSDC0_DAT4>,
1139				 <MT7623_PIN_118_MSDC0_DAT3_FUNC_MSDC0_DAT3>,
1140				 <MT7623_PIN_119_MSDC0_DAT2_FUNC_MSDC0_DAT2>,
1141				 <MT7623_PIN_120_MSDC0_DAT1_FUNC_MSDC0_DAT1>,
1142				 <MT7623_PIN_121_MSDC0_DAT0_FUNC_MSDC0_DAT0>,
1143				 <MT7623_PIN_116_MSDC0_CMD_FUNC_MSDC0_CMD>;
1144			input-enable;
1145			drive-strength = <2>;
1146			bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
1147		};
1148
1149		pins-clk {
1150			pinmux = <MT7623_PIN_117_MSDC0_CLK_FUNC_MSDC0_CLK>;
1151			drive-strength = <2>;
1152			bias-pull-down = <MTK_PUPD_SET_R1R0_01>;
1153		};
1154
1155		pins-rst {
1156			pinmux = <MT7623_PIN_115_MSDC0_RSTB_FUNC_MSDC0_RSTB>;
1157			bias-pull-up;
1158		};
1159	};
1160
1161	mmc1_pins_default: mmc1default {
1162		pins-cmd-dat {
1163			pinmux = <MT7623_PIN_107_MSDC1_DAT0_FUNC_MSDC1_DAT0>,
1164				 <MT7623_PIN_108_MSDC1_DAT1_FUNC_MSDC1_DAT1>,
1165				 <MT7623_PIN_109_MSDC1_DAT2_FUNC_MSDC1_DAT2>,
1166				 <MT7623_PIN_110_MSDC1_DAT3_FUNC_MSDC1_DAT3>,
1167				 <MT7623_PIN_105_MSDC1_CMD_FUNC_MSDC1_CMD>;
1168			input-enable;
1169			drive-strength = <4>;
1170			bias-pull-up = <MTK_PUPD_SET_R1R0_10>;
1171		};
1172
1173		pins-clk {
1174			pinmux = <MT7623_PIN_106_MSDC1_CLK_FUNC_MSDC1_CLK>;
1175			bias-pull-down;
1176			drive-strength = <4>;
1177		};
1178
1179		pins-wp {
1180			pinmux = <MT7623_PIN_29_EINT7_FUNC_MSDC1_WP>;
1181			input-enable;
1182			bias-pull-up;
1183		};
1184
1185		pins-insert {
1186			pinmux = <MT7623_PIN_261_MSDC1_INS_FUNC_GPIO261>;
1187			bias-pull-up;
1188		};
1189	};
1190
1191	mmc1_pins_uhs: mmc1 {
1192		pins-cmd-dat {
1193			pinmux = <MT7623_PIN_107_MSDC1_DAT0_FUNC_MSDC1_DAT0>,
1194				 <MT7623_PIN_108_MSDC1_DAT1_FUNC_MSDC1_DAT1>,
1195				 <MT7623_PIN_109_MSDC1_DAT2_FUNC_MSDC1_DAT2>,
1196				 <MT7623_PIN_110_MSDC1_DAT3_FUNC_MSDC1_DAT3>,
1197				 <MT7623_PIN_105_MSDC1_CMD_FUNC_MSDC1_CMD>;
1198			input-enable;
1199			drive-strength = <4>;
1200			bias-pull-up = <MTK_PUPD_SET_R1R0_10>;
1201		};
1202
1203		pins-clk {
1204			pinmux = <MT7623_PIN_106_MSDC1_CLK_FUNC_MSDC1_CLK>;
1205			drive-strength = <4>;
1206			bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
1207		};
1208	};
1209
1210	nand_pins_default: nanddefault {
1211		pins-ale {
1212			pinmux = <MT7623_PIN_116_MSDC0_CMD_FUNC_NALE>;
1213			drive-strength = <8>;
1214			bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
1215		};
1216
1217		pins-dat {
1218			pinmux = <MT7623_PIN_111_MSDC0_DAT7_FUNC_NLD7>,
1219				 <MT7623_PIN_112_MSDC0_DAT6_FUNC_NLD6>,
1220				 <MT7623_PIN_114_MSDC0_DAT4_FUNC_NLD4>,
1221				 <MT7623_PIN_118_MSDC0_DAT3_FUNC_NLD3>,
1222				 <MT7623_PIN_121_MSDC0_DAT0_FUNC_NLD0>,
1223				 <MT7623_PIN_120_MSDC0_DAT1_FUNC_NLD1>,
1224				 <MT7623_PIN_113_MSDC0_DAT5_FUNC_NLD5>,
1225				 <MT7623_PIN_115_MSDC0_RSTB_FUNC_NLD8>,
1226				 <MT7623_PIN_119_MSDC0_DAT2_FUNC_NLD2>;
1227			input-enable;
1228			drive-strength = <8>;
1229			bias-pull-up;
1230		};
1231
1232		pins-we {
1233			pinmux = <MT7623_PIN_117_MSDC0_CLK_FUNC_NWEB>;
1234			drive-strength = <8>;
1235			bias-pull-up = <MTK_PUPD_SET_R1R0_10>;
1236		};
1237	};
1238
1239	pcie_default: pcie_pin_default {
1240		pins_cmd_dat {
1241			pinmux = <MT7623_PIN_208_AUD_EXT_CK1_FUNC_PCIE0_PERST_N>,
1242				 <MT7623_PIN_209_AUD_EXT_CK2_FUNC_PCIE1_PERST_N>;
1243			bias-disable;
1244		};
1245	};
1246
1247	pwm_pins_a: pwm-default {
1248		pins-pwm {
1249			pinmux = <MT7623_PIN_203_PWM0_FUNC_PWM0>,
1250				 <MT7623_PIN_204_PWM1_FUNC_PWM1>,
1251				 <MT7623_PIN_205_PWM2_FUNC_PWM2>,
1252				 <MT7623_PIN_206_PWM3_FUNC_PWM3>,
1253				 <MT7623_PIN_207_PWM4_FUNC_PWM4>;
1254		};
1255	};
1256
1257	spi0_pins_a: spi0-default {
1258		pins-spi {
1259			pinmux = <MT7623_PIN_53_SPI0_CSN_FUNC_SPI0_CS>,
1260				<MT7623_PIN_54_SPI0_CK_FUNC_SPI0_CK>,
1261				<MT7623_PIN_55_SPI0_MI_FUNC_SPI0_MI>,
1262				<MT7623_PIN_56_SPI0_MO_FUNC_SPI0_MO>;
1263			bias-disable;
1264		};
1265	};
1266
1267	spi1_pins_a: spi1-default {
1268		pins-spi {
1269			pinmux = <MT7623_PIN_7_SPI1_CSN_FUNC_SPI1_CS>,
1270				<MT7623_PIN_199_SPI1_CK_FUNC_SPI1_CK>,
1271				<MT7623_PIN_8_SPI1_MI_FUNC_SPI1_MI>,
1272				<MT7623_PIN_9_SPI1_MO_FUNC_SPI1_MO>;
1273		};
1274	};
1275
1276	spi2_pins_a: spi2-default {
1277		pins-spi {
1278			pinmux = <MT7623_PIN_101_SPI2_CSN_FUNC_SPI2_CS>,
1279				 <MT7623_PIN_104_SPI2_CK_FUNC_SPI2_CK>,
1280				 <MT7623_PIN_102_SPI2_MI_FUNC_SPI2_MI>,
1281				 <MT7623_PIN_103_SPI2_MO_FUNC_SPI2_MO>;
1282		};
1283	};
1284
1285	uart0_pins_a: uart0-default {
1286		pins-dat {
1287			pinmux = <MT7623_PIN_79_URXD0_FUNC_URXD0>,
1288				 <MT7623_PIN_80_UTXD0_FUNC_UTXD0>;
1289		};
1290	};
1291
1292	uart1_pins_a: uart1-default {
1293		pins-dat {
1294			pinmux = <MT7623_PIN_81_URXD1_FUNC_URXD1>,
1295				 <MT7623_PIN_82_UTXD1_FUNC_UTXD1>;
1296		};
1297	};
1298
1299	uart2_pins_a: uart2-default {
1300		pins-dat {
1301			pinmux = <MT7623_PIN_14_GPIO14_FUNC_URXD2>,
1302				 <MT7623_PIN_15_GPIO15_FUNC_UTXD2>;
1303		};
1304	};
1305
1306	uart2_pins_b: uart2-alt {
1307		pins-dat {
1308			pinmux = <MT7623_PIN_200_URXD2_FUNC_URXD2>,
1309				 <MT7623_PIN_201_UTXD2_FUNC_UTXD2>;
1310		};
1311	};
1312};