mt6582.dtsi

  1// SPDX-License-Identifier: GPL-2.0+
  2/*
  3 * Copyright (c) 2021 Maxim Kutnij <gtk3@inbox.ru>
  4 */
  5
  6#include <dt-bindings/interrupt-controller/irq.h>
  7#include <dt-bindings/interrupt-controller/arm-gic.h>
  8
  9/ {
 10	#address-cells = <1>;
 11	#size-cells = <1>;
 12	interrupt-parent = <&sysirq>;
 13
 14	cpus {
 15		#size-cells = <0>;
 16		#address-cells = <1>;
 17		enable-method = "mediatek,mt6589-smp";
 18
 19		cpu@0 {
 20			device_type = "cpu";
 21			compatible = "arm,cortex-a7";
 22			reg = <0x0>;
 23		};
 24		cpu@1 {
 25			device_type = "cpu";
 26			compatible = "arm,cortex-a7";
 27			reg = <0x1>;
 28		};
 29		cpu@2 {
 30			device_type = "cpu";
 31			compatible = "arm,cortex-a7";
 32			reg = <0x2>;
 33		};
 34		cpu@3 {
 35			device_type = "cpu";
 36			compatible = "arm,cortex-a7";
 37			reg = <0x3>;
 38		};
 39	};
 40
 41	uart_clk: dummy26m {
 42		compatible = "fixed-clock";
 43		#clock-cells = <0>;
 44		clock-frequency = <26000000>;
 45	};
 46
 47	system_clk: dummy13m {
 48		compatible = "fixed-clock";
 49		#clock-cells = <0>;
 50		clock-frequency = <13000000>;
 51	};
 52
 53	rtc_clk: dummy32k {
 54		compatible = "fixed-clock";
 55		#clock-cells = <0>;
 56		clock-frequency = <32000>;
 57	};
 58
 59	soc {
 60		#address-cells = <1>;
 61		#size-cells = <1>;
 62		compatible = "simple-bus";
 63		ranges;
 64
 65		watchdog: watchdog@10007000 {
 66			compatible = "mediatek,mt6582-wdt", "mediatek,mt6589-wdt";
 67			reg = <0x10007000 0x100>;
 68		};
 69
 70		timer: timer@10008000 {
 71			compatible = "mediatek,mt6582-timer", "mediatek,mt6577-timer";
 72			reg = <0x10008000 0x80>;
 73			interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_LOW>;
 74			clocks = <&system_clk>, <&rtc_clk>;
 75		};
 76
 77		sysirq: interrupt-controller@10200100 {
 78			compatible = "mediatek,mt6582-sysirq", "mediatek,mt6577-sysirq";
 79			reg = <0x10200100 0x1c>;
 80			interrupt-parent = <&gic>;
 81			interrupt-controller;
 82			#interrupt-cells = <3>;
 83		};
 84
 85		gic: interrupt-controller@10211000 {
 86			compatible = "arm,cortex-a7-gic";
 87			#interrupt-cells = <3>;
 88			interrupt-controller;
 89			interrupt-parent = <&gic>;
 90			reg = <0x10211000 0x1000>,
 91			      <0x10212000 0x2000>,
 92			      <0x10214000 0x2000>,
 93			      <0x10216000 0x2000>;
 94		};
 95
 96		uart0: serial@11002000 {
 97			compatible = "mediatek,mt6582-uart", "mediatek,mt6577-uart";
 98			reg = <0x11002000 0x400>;
 99			interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_LOW>;
100			clocks = <&uart_clk>;
101			clock-names = "baud";
102			status = "disabled";
103		};
104
105		uart1: serial@11003000 {
106			compatible = "mediatek,mt6582-uart", "mediatek,mt6577-uart";
107			reg = <0x11003000 0x400>;
108			interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_LOW>;
109			clocks = <&uart_clk>;
110			clock-names = "baud";
111			status = "disabled";
112		};
113
114		uart2: serial@11004000 {
115			compatible = "mediatek,mt6582-uart", "mediatek,mt6577-uart";
116			reg = <0x11004000 0x400>;
117			interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_LOW>;
118			clocks = <&uart_clk>;
119			clock-names = "baud";
120			status = "disabled";
121		};
122
123		uart3: serial@11005000 {
124			compatible = "mediatek,mt6582-uart", "mediatek,mt6577-uart";
125			reg = <0x11005000 0x400>;
126			interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_LOW>;
127			clocks = <&uart_clk>;
128			clock-names = "baud";
129			status = "disabled";
130		};
131	};
132};