socfpga_arria10_mercury_aa1.dtsi

  1// SPDX-License-Identifier: GPL-2.0
  2/*
  3 * Copyright 2022 Google LLC
  4 */
  5
  6#include "socfpga_arria10.dtsi"
  7
  8/ {
  9
 10	model = "Enclustra Mercury+ AA1";
 11	compatible = "enclustra,mercury-aa1",
 12		     "altr,socfpga-arria10", "altr,socfpga";
 13
 14	aliases {
 15		ethernet0 = &gmac0;
 16		serial1 = &uart1;
 17		spi0 = &qspi;
 18	};
 19
 20	memory@0 {
 21		name = "memory";
 22		device_type = "memory";
 23		reg = <0x0 0x80000000>; /* 2GB */
 24	};
 25
 26	chosen {
 27		stdout-path = "serial1:115200n8";
 28	};
 29
 30	/* Adjusted the i2c labels to use generic base-board dtsi files for
 31	 * Enclustra Arria10 and Cyclone5 SoMs.
 32	 *
 33	 * The set of i2c0 and i2c1 labels defined in socfpga_cyclone5.dtsi and in
 34	 * socfpga_arria10.dtsi do not allow for using the same base-board .dtsi
 35	 * fragments. Thus define generic labels here to match the correct i2c
 36	 * bus in a generic base-board .dtsi file.
 37	 */
 38	soc {
 39		i2c_encl: i2c@ffc02300 {
 40		};
 41		i2c_encl_fpga: i2c@ffc02200 {
 42		};
 43	};
 44};
 45
 46&i2c_encl {
 47	status = "okay";
 48	i2c-sda-hold-time-ns = <300>;
 49	clock-frequency = <100000>;
 50
 51	atsha204a: crypto@64 {
 52		compatible = "atmel,atsha204a";
 53		reg = <0x64>;
 54	};
 55
 56	isl12022: rtc@6f {
 57		compatible = "isil,isl12022";
 58		reg = <0x6f>;
 59	};
 60};
 61
 62&i2c_encl_fpga {
 63	i2c-sda-hold-time-ns = <300>;
 64	status = "disabled";
 65};
 66
 67&gmac0 {
 68	status = "okay";
 69	phy-mode = "rgmii-id";
 70	phy-addr = <0xffffffff>; /* probe for phy addr */
 71	max-frame-size = <3800>;
 72	phy-handle = <&phy3>;
 73
 74	/delete-property/ mac-address;
 75
 76	mdio {
 77		#address-cells = <1>;
 78		#size-cells = <0>;
 79		compatible = "snps,dwmac-mdio";
 80		phy3: ethernet-phy@3 {
 81			reg = <3>;
 82
 83			/* Add 2ns RX clock delay (1.2ns + 0.78ns)*/
 84			rxc-skew-ps = <1680>; /* 780ps */
 85			rxd0-skew-ps = <420>; /* 0ps */
 86			rxd1-skew-ps = <420>; /* 0ps */
 87			rxd2-skew-ps = <420>; /* 0ps */
 88			rxd3-skew-ps = <420>; /* 0ps */
 89			rxdv-skew-ps = <420>; /* 0ps */
 90
 91			/* Add 1.38ns TX clock delay (0.96ns + 0.42ns)*/
 92			txc-skew-ps = <1860>; /* 960ps */
 93			txd0-skew-ps = <0>; /* -420ps */
 94			txd1-skew-ps = <0>; /* -420ps */
 95			txd2-skew-ps = <0>; /* -420ps */
 96			txd3-skew-ps = <0>; /* -420ps */
 97			txen-skew-ps = <0>; /* -420ps */
 98		};
 99	};
100};
101
102&gpio0 {
103	status = "okay";
104};
105
106&gpio1 {
107	status = "okay";
108};
109
110&gpio2 {
111	status = "okay";
112};
113
114&uart0 {
115	status = "disabled";
116};
117
118&uart1 {
119	status = "okay";
120};
121
122/* Following mappings are taken from arria10 socdk dts */
123&mmc {
124	status = "okay";
125	cap-sd-highspeed;
126	broken-cd;
127	bus-width = <4>;
128	clk-phase-sd-hs = <0>, <135>;
129};
130
131&osc1 {
132	clock-frequency = <33330000>;
133};
134
135&eccmgr {
136	sdmmca-ecc@ff8c2c00 {
137		compatible = "altr,socfpga-sdmmc-ecc";
138		reg = <0xff8c2c00 0x400>;
139		altr,ecc-parent = <&mmc>;
140		interrupts = <15 IRQ_TYPE_LEVEL_HIGH>,
141					 <47 IRQ_TYPE_LEVEL_HIGH>,
142					 <16 IRQ_TYPE_LEVEL_HIGH>,
143					 <48 IRQ_TYPE_LEVEL_HIGH>;
144	};
145};
146
147&qspi {
148	status = "okay";
149	flash0: flash@0 {
150		u-boot,dm-pre-reloc;
151		#address-cells = <1>;
152		#size-cells = <1>;
153		compatible = "jedec,spi-nor";
154		reg = <0>;
155
156		spi-rx-bus-width = <4>;
157		spi-tx-bus-width = <4>;
158		spi-max-frequency = <10000000>;
159
160		cdns,read-delay = <4>;
161		cdns,tshsl-ns = <50>;
162		cdns,tsd2d-ns = <50>;
163		cdns,tchsh-ns = <4>;
164		cdns,tslch-ns = <4>;
165
166		partition@raw {
167			label = "Flash Raw";
168			reg = <0x0 0x4000000>;
169		};
170	};
171};
172
173&watchdog1 {
174	status = "disabled";
175};
176
177&usb0 {
178	status = "okay";
179	dr_mode = "host";
180};