intel-ixp42x-actiontec-mi424wr.dtsi

  1// SPDX-License-Identifier: ISC
  2/*
  3 * Device Tree file for the IXP425-based Actiontec MI424WR
  4 * Based on a board file from OpenWrt by Jose Vasconcellos.
  5 */
  6
  7#include "intel-ixp42x.dtsi"
  8#include <dt-bindings/input/input.h>
  9#include <dt-bindings/leds/common.h>
 10
 11/ {
 12	#address-cells = <1>;
 13	#size-cells = <1>;
 14
 15	memory@0 {
 16		device_type = "memory";
 17		reg = <0x00000000 0x02000000>;
 18	};
 19
 20	chosen {
 21		bootargs = "console=ttyS0,115200n8";
 22		stdout-path = "uart1:115200n8";
 23	};
 24
 25	leds {
 26		compatible = "gpio-leds";
 27
 28		led-wan-coax {
 29			color = <LED_COLOR_ID_GREEN>;
 30			function = "wan-coax";
 31			gpios = <&gpio0 11 GPIO_ACTIVE_HIGH>;
 32			default-state = "off";
 33		};
 34		led-power-alarm {
 35			color = <LED_COLOR_ID_RED>;
 36			function = LED_FUNCTION_ALARM;
 37			gpios = <&gpio1 0 GPIO_ACTIVE_HIGH>;
 38			default-state = "off";
 39		};
 40		led-power {
 41			color = <LED_COLOR_ID_GREEN>;
 42			function = LED_FUNCTION_POWER;
 43			gpios = <&gpio1 1 GPIO_ACTIVE_HIGH>;
 44			default-state = "on";
 45			linux,default-trigger = "heartbeat";
 46		};
 47		led-wireless {
 48			color = <LED_COLOR_ID_GREEN>;
 49			function = LED_FUNCTION_WLAN;
 50			gpios = <&gpio1 2 GPIO_ACTIVE_LOW>;
 51			default-state = "off";
 52		};
 53		led-internet-down {
 54			color = <LED_COLOR_ID_RED>;
 55			function = "internet-down";
 56			gpios = <&gpio1 3 GPIO_ACTIVE_HIGH>;
 57			default-state = "off";
 58		};
 59		led-internet-up {
 60			color = <LED_COLOR_ID_GREEN>;
 61			function = "internet-up";
 62			gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>;
 63			default-state = "off";
 64		};
 65		led-lan-coax {
 66			color = <LED_COLOR_ID_GREEN>;
 67			function = "lan-coax";
 68			gpios = <&gpio1 5 GPIO_ACTIVE_HIGH>;
 69			default-state = "off";
 70		};
 71		led-wan-ethernet-alarm {
 72			color = <LED_COLOR_ID_RED>;
 73			function = "wan-ethernet-alarm";
 74			gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>;
 75			default-state = "off";
 76		};
 77		/* The last three LEDs are not mounted but traces exist on the PCB */
 78		led-phone-1 {
 79			color = <LED_COLOR_ID_GREEN>;
 80			function = "phone-1";
 81			gpios = <&gpio1 8 GPIO_ACTIVE_LOW>;
 82			default-state = "off";
 83		};
 84		led-phone-2 {
 85			color = <LED_COLOR_ID_GREEN>;
 86			function = "phone-2";
 87			gpios = <&gpio1 9 GPIO_ACTIVE_LOW>;
 88			default-state = "off";
 89		};
 90		led-voip {
 91			color = <LED_COLOR_ID_GREEN>;
 92			function = "voip";
 93			gpios = <&gpio1 10 GPIO_ACTIVE_LOW>;
 94			default-state = "off";
 95		};
 96	};
 97
 98	gpio_keys {
 99		compatible = "gpio-keys";
100
101		button-reset {
102			wakeup-source;
103			linux,code = <KEY_RESTART>;
104			label = "reset";
105			gpios = <&gpio0 10 GPIO_ACTIVE_LOW>;
106		};
107	};
108
109	spi {
110		compatible = "spi-gpio";
111		#address-cells = <1>;
112		#size-cells = <0>;
113
114		sck-gpios = <&gpio0 2 GPIO_ACTIVE_HIGH>;
115		mosi-gpios = <&gpio0 4 GPIO_ACTIVE_HIGH>;
116		miso-gpios = <&gpio0 3 GPIO_ACTIVE_HIGH>;
117		cs-gpios = <&gpio0 9 GPIO_ACTIVE_LOW>;
118		num-chipselects = <1>;
119
120		ethernet-switch@0 {
121			compatible = "micrel,ks8995";
122			reg = <0>;
123			spi-max-frequency = <50000000>;
124
125			ethernet-ports {
126				#address-cells = <1>;
127				#size-cells = <0>;
128
129				ethernet-port@0 {
130					reg = <0>;
131					label = "lan1";
132					phy-mode = "mii";
133					phy-handle = <&phy1>;
134				};
135				ethernet-port@1 {
136					reg = <1>;
137					label = "lan2";
138					phy-mode = "mii";
139					phy-handle = <&phy2>;
140				};
141				ethernet-port@2 {
142					reg = <2>;
143					label = "lan3";
144					phy-mode = "mii";
145					phy-handle = <&phy3>;
146				};
147				ethernet-port@3 {
148					reg = <3>;
149					label = "lan4";
150					phy-mode = "mii";
151					phy-handle = <&phy4>;
152				};
153				ethernet-port@4 {
154					reg = <4>;
155					phy-mode = "mii";
156					fixed-link {
157						speed = <100>;
158						full-duplex;
159					};
160				};
161
162			};
163		};
164	};
165
166	soc {
167		bus@c4000000 {
168			flash@0,0 {
169				compatible = "intel,ixp4xx-flash", "cfi-flash";
170				bank-width = <2>;
171				/*
172				 * 8 MB of Flash in 64 0x20000 sized blocks
173				 * mapped in at CS0.
174				 */
175				reg = <0 0x00000000 0x0800000>;
176
177				/* Configure expansion bus to allow writes */
178				intel,ixp4xx-eb-write-enable = <1>;
179
180				partitions {
181					compatible = "redboot-fis";
182					fis-index-block = <0x3f>;
183				};
184			};
185			gpio1: gpio@1,0 {
186				/* MMIO GPIO at CS1 */
187				compatible = "intel,ixp4xx-expansion-bus-mmio-gpio";
188				gpio-controller;
189				#gpio-cells = <2>;
190				big-endian;
191				reg = <1 0x00000000 0x2>;
192				reg-names = "dat";
193				/* Expansion bus settings */
194				intel,ixp4xx-eb-write-enable = <1>;
195
196				pci-reset-hog {
197					gpio-hog;
198					gpios = <7 GPIO_ACTIVE_HIGH>;
199					output-high;
200					line-name = "PCI reset";
201				};
202				pstn-relay-hog-1 {
203					gpio-hog;
204					gpios = <11 GPIO_ACTIVE_HIGH>;
205					output-low;
206					line-name = "PSTN relay control 1";
207				};
208				pstn-relay-hog-2 {
209					gpio-hog;
210					gpios = <12 GPIO_ACTIVE_HIGH>;
211					output-low;
212					line-name = "PSTN relay control 2";
213				};
214			};
215		};
216
217		pci@c0000000 {
218			status = "okay";
219
220			#interrupt-cells = <1>;
221			interrupt-map-mask = <0xf800 0 0 7>;
222			interrupt-map =
223			/* IDSEL 13 */
224			<0x6800 0 0 1 &gpio0 8 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 13 is irq 8 */
225			<0x6800 0 0 2 &gpio0 6 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 13 is irq 6 */
226			/* IDSEL 14 */
227			<0x7000 0 0 1 &gpio0 8 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 14 is irq 7 */
228			<0x7000 0 0 2 &gpio0 6 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 14 is irq 8 */
229			/* IDSEL 15 */
230			<0x7800 0 0 1 &gpio0 8 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 15 is irq 6 */
231			<0x7800 0 0 2 &gpio0 6 IRQ_TYPE_LEVEL_LOW>; /* INT B on slot 15 is irq 7 */
232		};
233
234		ethb: ethernet@c8009000 {
235			status = "okay";
236			queue-rx = <&qmgr 3>;
237			queue-txready = <&qmgr 20>;
238			phy-mode = "mii";
239
240			mdio {
241				#address-cells = <1>;
242				#size-cells = <0>;
243
244				/* 1, 2, 3 and 4 are ports on the KS8995 switch */
245				phy1: ethernet-phy@1 {
246					/* LAN1 */
247					reg = <1>;
248				};
249				phy2: ethernet-phy@2 {
250					/* LAN2 */
251					reg = <2>;
252				};
253				phy3: ethernet-phy@3 {
254					/* LAN3 */
255					reg = <3>;
256				};
257				phy4: ethernet-phy@4 {
258					/* LAN4 */
259					reg = <4>;
260				};
261			};
262		};
263
264		ethc: ethernet@c800a000 {
265			status = "okay";
266			queue-rx = <&qmgr 4>;
267			queue-txready = <&qmgr 21>;
268			phy-mode = "mii";
269		};
270	};
271};