bcm6846.dtsi

  1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
  2/*
  3 * Copyright 2022 Broadcom Ltd.
  4 */
  5
  6#include <dt-bindings/interrupt-controller/arm-gic.h>
  7#include <dt-bindings/interrupt-controller/irq.h>
  8
  9/ {
 10	compatible = "brcm,bcm6846", "brcm,bcmbca";
 11	#address-cells = <1>;
 12	#size-cells = <1>;
 13
 14	interrupt-parent = <&gic>;
 15
 16	cpus {
 17		#address-cells = <1>;
 18		#size-cells = <0>;
 19
 20		CA7_0: cpu@0 {
 21			device_type = "cpu";
 22			compatible = "arm,cortex-a7";
 23			reg = <0x0>;
 24			next-level-cache = <&L2_0>;
 25			enable-method = "psci";
 26		};
 27
 28		CA7_1: cpu@1 {
 29			device_type = "cpu";
 30			compatible = "arm,cortex-a7";
 31			reg = <0x1>;
 32			next-level-cache = <&L2_0>;
 33			enable-method = "psci";
 34		};
 35
 36		L2_0: l2-cache0 {
 37			compatible = "cache";
 38			cache-level = <2>;
 39			cache-unified;
 40		};
 41	};
 42
 43	timer {
 44		compatible = "arm,armv7-timer";
 45		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
 46			<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
 47			<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
 48			<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
 49		arm,cpu-registers-not-fw-configured;
 50	};
 51
 52	pmu: pmu {
 53		compatible = "arm,cortex-a7-pmu";
 54		interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
 55			<GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
 56		interrupt-affinity = <&CA7_0>, <&CA7_1>;
 57	};
 58
 59	clocks: clocks {
 60		periph_clk: periph-clk {
 61			compatible = "fixed-clock";
 62			#clock-cells = <0>;
 63			clock-frequency = <200000000>;
 64		};
 65
 66		hsspi_pll: hsspi-pll {
 67			compatible = "fixed-clock";
 68			#clock-cells = <0>;
 69			clock-frequency = <400000000>;
 70		};
 71	};
 72
 73	psci {
 74		compatible = "arm,psci-0.2";
 75		method = "smc";
 76	};
 77
 78	axi@81000000 {
 79		compatible = "simple-bus";
 80		#address-cells = <1>;
 81		#size-cells = <1>;
 82		ranges = <0 0x81000000 0x8000>;
 83
 84		gic: interrupt-controller@1000 {
 85			compatible = "arm,cortex-a7-gic";
 86			#interrupt-cells = <3>;
 87			interrupt-controller;
 88			interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
 89			reg = <0x1000 0x1000>,
 90				<0x2000 0x2000>,
 91				<0x4000 0x2000>,
 92				<0x6000 0x2000>;
 93		};
 94	};
 95
 96	bus@ff800000 {
 97		compatible = "simple-bus";
 98		#address-cells = <1>;
 99		#size-cells = <1>;
100		ranges = <0 0xff800000 0x800000>;
101
102		watchdog@480 {
103			compatible = "brcm,bcm6345-wdt";
104			reg = <0x480 0x10>;
105		};
106
107		/* GPIOs 0 .. 31 */
108		gpio0: gpio@500 {
109			compatible = "brcm,bcm6345-gpio";
110			reg = <0x500 0x04>, <0x520 0x04>;
111			reg-names = "dirout", "dat";
112			gpio-controller;
113			#gpio-cells = <2>;
114			status = "disabled";
115		};
116
117		/* GPIOs 32 .. 63 */
118		gpio1: gpio@504 {
119			compatible = "brcm,bcm6345-gpio";
120			reg = <0x504 0x04>, <0x524 0x04>;
121			reg-names = "dirout", "dat";
122			gpio-controller;
123			#gpio-cells = <2>;
124			status = "disabled";
125		};
126
127		/* GPIOs 64 .. 95 */
128		gpio2: gpio@508 {
129			compatible = "brcm,bcm6345-gpio";
130			reg = <0x508 0x04>, <0x528 0x04>;
131			reg-names = "dirout", "dat";
132			gpio-controller;
133			#gpio-cells = <2>;
134			status = "disabled";
135		};
136
137		/* GPIOs 96 .. 127 */
138		gpio3: gpio@50c {
139			compatible = "brcm,bcm6345-gpio";
140			reg = <0x50c 0x04>, <0x52c 0x04>;
141			reg-names = "dirout", "dat";
142			gpio-controller;
143			#gpio-cells = <2>;
144			status = "disabled";
145		};
146
147		/* GPIOs 128 .. 159 */
148		gpio4: gpio@510 {
149			compatible = "brcm,bcm6345-gpio";
150			reg = <0x510 0x04>, <0x530 0x04>;
151			reg-names = "dirout", "dat";
152			gpio-controller;
153			#gpio-cells = <2>;
154			status = "disabled";
155		};
156
157		/* GPIOs 160 .. 191 */
158		gpio5: gpio@514 {
159			compatible = "brcm,bcm6345-gpio";
160			reg = <0x514 0x04>, <0x534 0x04>;
161			reg-names = "dirout", "dat";
162			gpio-controller;
163			#gpio-cells = <2>;
164			status = "disabled";
165		};
166
167		/* GPIOs 192 .. 223 */
168		gpio6: gpio@518 {
169			compatible = "brcm,bcm6345-gpio";
170			reg = <0x518 0x04>, <0x538 0x04>;
171			reg-names = "dirout", "dat";
172			gpio-controller;
173			#gpio-cells = <2>;
174			status = "disabled";
175		};
176
177		/* GPIOs 224 .. 255 */
178		gpio7: gpio@51c {
179			compatible = "brcm,bcm6345-gpio";
180			reg = <0x51c 0x04>, <0x53c 0x04>;
181			reg-names = "dirout", "dat";
182			gpio-controller;
183			#gpio-cells = <2>;
184			status = "disabled";
185		};
186
187		uart0: serial@640 {
188			compatible = "brcm,bcm6345-uart";
189			reg = <0x640 0x1b>;
190			interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
191			clocks = <&periph_clk>;
192			clock-names = "refclk";
193			status = "disabled";
194		};
195
196		rng@b80 {
197			compatible = "brcm,iproc-rng200";
198			reg = <0xb80 0x28>;
199			interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
200		};
201
202		leds: led-controller@800 {
203			#address-cells = <1>;
204			#size-cells = <0>;
205			compatible = "brcm,bcm63138-leds";
206			reg = <0x800 0xdc>;
207			status = "disabled";
208		};
209
210		hsspi: spi@1000 {
211			#address-cells = <1>;
212			#size-cells = <0>;
213			compatible = "brcm,bcm6846-hsspi", "brcm,bcmbca-hsspi-v1.0";
214			reg = <0x1000 0x600>;
215			interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
216			clocks = <&hsspi_pll &hsspi_pll>;
217			clock-names = "hsspi", "pll";
218			num-cs = <8>;
219			status = "disabled";
220		};
221
222		nand_controller: nand-controller@1800 {
223			#address-cells = <1>;
224			#size-cells = <0>;
225			compatible = "brcm,nand-bcm63138", "brcm,brcmnand-v7.1", "brcm,brcmnand";
226			reg = <0x1800 0x600>, <0x2000 0x10>;
227			reg-names = "nand", "nand-int-base";
228			status = "disabled";
229
230			nandcs: nand@0 {
231				compatible = "brcm,nandcs";
232				reg = <0>;
233			};
234		};
235
236		mdio: mdio@2060 {
237			compatible = "brcm,bcm6846-mdio";
238			reg = <0x02060 0x10>, <0x5a068 0x4>;
239			reg-names = "mdio", "mdio_indir_rw";
240			#address-cells = <1>;
241			#size-cells = <0>;
242			status = "disabled";
243		};
244
245		pl081_dma: dma-controller@59000 {
246			compatible = "arm,pl081", "arm,primecell";
247			// The magic B105F00D info is missing
248			arm,primecell-periphid = <0x00041081>;
249			reg = <0x59000 0x1000>;
250			interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
251			memcpy-burst-size = <256>;
252			memcpy-bus-width = <32>;
253			clocks = <&periph_clk>;
254			clock-names = "apb_pclk";
255			#dma-cells = <2>;
256		};
257	};
258};