bcm63138.dtsi

  1// SPDX-License-Identifier: GPL-2.0
  2/*
  3 * Broadcom BCM63138 DSL SoCs Device Tree
  4 */
  5
  6#include <dt-bindings/interrupt-controller/arm-gic.h>
  7#include <dt-bindings/interrupt-controller/irq.h>
  8
  9/ {
 10	#address-cells = <1>;
 11	#size-cells = <1>;
 12	compatible = "brcm,bcm63138", "brcm,bcmbca";
 13	model = "Broadcom BCM963138 Reference Board";
 14	interrupt-parent = <&gic>;
 15
 16	aliases {
 17		uart0 = &serial0;
 18		uart1 = &serial1;
 19	};
 20
 21	cpus {
 22		#address-cells = <1>;
 23		#size-cells = <0>;
 24
 25		cpu@0 {
 26			device_type = "cpu";
 27			compatible = "arm,cortex-a9";
 28			next-level-cache = <&L2>;
 29			reg = <0>;
 30			enable-method = "brcm,bcm63138";
 31		};
 32
 33		cpu@1 {
 34			device_type = "cpu";
 35			compatible = "arm,cortex-a9";
 36			next-level-cache = <&L2>;
 37			reg = <1>;
 38			enable-method = "brcm,bcm63138";
 39			resets = <&pmb0 4 1>;
 40		};
 41	};
 42
 43	clocks {
 44		/* UBUS peripheral clock */
 45		periph_clk: periph_clk {
 46			#clock-cells = <0>;
 47			compatible = "fixed-clock";
 48			clock-frequency = <50000000>;
 49			clock-output-names = "periph";
 50		};
 51
 52		/* peripheral clock for system timer */
 53		axi_clk: axi_clk {
 54			#clock-cells = <0>;
 55			compatible = "fixed-factor-clock";
 56			clocks = <&armpll>;
 57			clock-div = <2>;
 58			clock-mult = <1>;
 59		};
 60
 61		/* APB bus clock */
 62		apb_clk: apb_clk {
 63			#clock-cells = <0>;
 64			compatible = "fixed-factor-clock";
 65			clocks = <&armpll>;
 66			clock-div = <4>;
 67			clock-mult = <1>;
 68		};
 69
 70		hsspi_pll: hsspi-pll {
 71			compatible = "fixed-clock";
 72			#clock-cells = <0>;
 73			clock-frequency = <400000000>;
 74		};
 75	};
 76
 77	/* ARM bus */
 78	axi@80000000 {
 79		compatible = "simple-bus";
 80		ranges = <0 0x80000000 0x784000>;
 81		#address-cells = <1>;
 82		#size-cells = <1>;
 83
 84		L2: cache-controller@1d000 {
 85			compatible = "arm,pl310-cache";
 86			reg = <0x1d000 0x1000>;
 87			cache-unified;
 88			cache-level = <2>;
 89			cache-size = <524288>;
 90			cache-sets = <1024>;
 91			cache-line-size = <32>;
 92			interrupts = <GIC_PPI 0 IRQ_TYPE_LEVEL_HIGH>;
 93		};
 94
 95		scu: scu@1e000 {
 96			compatible = "arm,cortex-a9-scu";
 97			reg = <0x1e000 0x100>;
 98		};
 99
100		gic: interrupt-controller@1f000 {
101			compatible = "arm,cortex-a9-gic";
102			reg = <0x1f000 0x1000
103				0x1e100 0x100>;
104			#interrupt-cells = <3>;
105			#address-cells = <0>;
106			interrupt-controller;
107		};
108
109		global_timer: timer@1e200 {
110			compatible = "arm,cortex-a9-global-timer";
111			reg = <0x1e200 0x20>;
112			interrupts = <GIC_PPI 11 IRQ_TYPE_EDGE_RISING>;
113			clocks = <&axi_clk>;
114		};
115
116		local_timer: local-timer@1e600 {
117			compatible = "arm,cortex-a9-twd-timer";
118			reg = <0x1e600 0x20>;
119			interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) |
120						  IRQ_TYPE_EDGE_RISING)>;
121			clocks = <&axi_clk>;
122		};
123
124		twd_watchdog: watchdog@1e620 {
125			compatible = "arm,cortex-a9-twd-wdt";
126			reg = <0x1e620 0x20>;
127			interrupts = <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) |
128						  IRQ_TYPE_LEVEL_HIGH)>;
129		};
130
131		armpll: armpll@20000 {
132			#clock-cells = <0>;
133			compatible = "brcm,bcm63138-armpll";
134			clocks = <&periph_clk>;
135			reg = <0x20000 0xf00>;
136		};
137
138		pmb0: reset-controller@4800c0 {
139			compatible = "brcm,bcm63138-pmb";
140			reg = <0x4800c0 0x10>;
141			#reset-cells = <2>;
142		};
143
144		pmb1: reset-controller@4800e0 {
145			compatible = "brcm,bcm63138-pmb";
146			reg = <0x4800e0 0x10>;
147			#reset-cells = <2>;
148		};
149
150		ahci: sata@a000 {
151			compatible = "brcm,bcm63138-ahci", "brcm,sata3-ahci";
152			reg-names = "ahci", "top-ctrl";
153			reg = <0xa000 0x9ac>, <0x8040 0x24>;
154			interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
155			#address-cells = <1>;
156			#size-cells = <0>;
157			resets = <&pmb0 3 1>;
158			reset-names = "ahci";
159			status = "disabled";
160
161			sata0: sata-port@0 {
162				reg = <0>;
163				phys = <&sata_phy0>;
164			};
165		};
166
167		sata_phy: sata-phy@8100 {
168			compatible = "brcm,bcm63138-sata-phy", "brcm,phy-sata3";
169			reg = <0x8100 0x1e00>;
170			reg-names = "phy";
171			#address-cells = <1>;
172			#size-cells = <0>;
173			status = "disabled";
174
175			sata_phy0: sata-phy@0 {
176				reg = <0>;
177				#phy-cells = <0>;
178			};
179		};
180	};
181
182	/* Legacy UBUS base */
183	ubus@fffe8000 {
184		compatible = "simple-bus";
185		#address-cells = <1>;
186		#size-cells = <1>;
187		ranges = <0 0xfffe8000 0x10000>;
188
189		timer: timer@80 {
190			compatible = "brcm,bcm6328-timer", "syscon";
191			reg = <0x80 0x3c>;
192		};
193
194		/* GPIOs 0 .. 31 */
195		gpio0: gpio@100 {
196			compatible = "brcm,bcm6345-gpio";
197			reg = <0x100 0x04>, <0x114 0x04>;
198			reg-names = "dirout", "dat";
199			gpio-controller;
200			#gpio-cells = <2>;
201			status = "disabled";
202		};
203
204		/* GPIOs 32 .. 63 */
205		gpio1: gpio@104 {
206			compatible = "brcm,bcm6345-gpio";
207			reg = <0x104 0x04>, <0x118 0x04>;
208			reg-names = "dirout", "dat";
209			gpio-controller;
210			#gpio-cells = <2>;
211			status = "disabled";
212		};
213
214		/* GPIOs 64 .. 95 */
215		gpio2: gpio@108 {
216			compatible = "brcm,bcm6345-gpio";
217			reg = <0x108 0x04>, <0x11c 0x04>;
218			reg-names = "dirout", "dat";
219			gpio-controller;
220			#gpio-cells = <2>;
221			status = "disabled";
222		};
223
224		/* GPIOs 96 .. 127 */
225		gpio3: gpio@10c {
226			compatible = "brcm,bcm6345-gpio";
227			reg = <0x10c 0x04>, <0x120 0x04>;
228			reg-names = "dirout", "dat";
229			gpio-controller;
230			#gpio-cells = <2>;
231			status = "disabled";
232		};
233
234		/* GPIOs 128 .. 159 */
235		gpio4: gpio@110 {
236			compatible = "brcm,bcm6345-gpio";
237			reg = <0x110 0x04>, <0x124 0x04>;
238			reg-names = "dirout", "dat";
239			gpio-controller;
240			#gpio-cells = <2>;
241			status = "disabled";
242		};
243
244		rng@300 {
245			compatible = "brcm,iproc-rng200";
246			reg = <0x300 0x28>;
247			interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
248		};
249
250		serial0: serial@600 {
251			compatible = "brcm,bcm6345-uart";
252			reg = <0x600 0x1b>;
253			interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
254			clocks = <&periph_clk>;
255			clock-names = "periph";
256			status = "disabled";
257		};
258
259		serial1: serial@620 {
260			compatible = "brcm,bcm6345-uart";
261			reg = <0x620 0x1b>;
262			interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
263			clocks = <&periph_clk>;
264			clock-names = "periph";
265			status = "disabled";
266		};
267
268		leds: led-controller@700 {
269			#address-cells = <1>;
270			#size-cells = <0>;
271			compatible = "brcm,bcm63138-leds";
272			reg = <0x700 0xdc>;
273			status = "disabled";
274		};
275
276		hsspi: spi@1000 {
277			#address-cells = <1>;
278			#size-cells = <0>;
279			compatible = "brcm,bcm63138-hsspi", "brcm,bcmbca-hsspi-v1.0";
280			reg = <0x1000 0x600>;
281			interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
282			clocks = <&hsspi_pll &hsspi_pll>;
283			clock-names = "hsspi", "pll";
284			num-cs = <8>;
285			status = "disabled";
286		};
287
288		nand_controller: nand-controller@2000 {
289			#address-cells = <1>;
290			#size-cells = <0>;
291			compatible = "brcm,nand-bcm63138", "brcm,brcmnand-v7.0", "brcm,brcmnand";
292			reg = <0x2000 0x600>, <0xf0 0x10>;
293			reg-names = "nand", "nand-int-base";
294			status = "disabled";
295			interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
296			interrupt-names = "nand_ctlrdy";
297
298			nandcs: nand@0 {
299				compatible = "brcm,nandcs";
300				reg = <0>;
301			};
302		};
303
304		serial@4400 {
305			compatible = "brcm,bcm63138-hs-uart", "brcm,bcmbca-hs-uart";
306			reg = <0x4400 0x1e0>;
307			interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
308		};
309
310		bootlut: bootlut@8000 {
311			compatible = "brcm,bcm63138-bootlut";
312			reg = <0x8000 0x50>;
313		};
314
315		pl081_dma: dma-controller@d000 {
316			compatible = "arm,pl081", "arm,primecell";
317			// The magic B105F00D info is missing
318			arm,primecell-periphid = <0x00041081>;
319			reg = <0xd000 0x1000>;
320			interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
321			memcpy-burst-size = <256>;
322			memcpy-bus-width = <32>;
323			clocks = <&periph_clk>;
324			clock-names = "apb_pclk";
325			#dma-cells = <2>;
326		};
327
328		reboot {
329			compatible = "syscon-reboot";
330			regmap = <&timer>;
331			offset = <0x34>;
332			mask = <1>;
333		};
334	};
335};