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bcm2711.dtsi
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linux-6.19.14/arch/arm/boot/dts/broadcom/bcm2711.dtsi
1// SPDX-License-Identifier: GPL-2.0 2#include "bcm283x.dtsi" 3 4#include <dt-bindings/interrupt-controller/arm-gic.h> 5#include <dt-bindings/soc/bcm2835-pm.h> 6 7/ { 8 compatible = "brcm,bcm2711"; 9 10 #address-cells = <2>; 11 #size-cells = <1>; 12 13 interrupt-parent = <&gicv2>; 14 15 vc4: gpu { 16 compatible = "brcm,bcm2711-vc5"; 17 status = "disabled"; 18 }; 19 20 clk_27MHz: clk-27M { 21 #clock-cells = <0>; 22 compatible = "fixed-clock"; 23 clock-frequency = <27000000>; 24 clock-output-names = "27MHz-clock"; 25 }; 26 27 clk_108MHz: clk-108M { 28 #clock-cells = <0>; 29 compatible = "fixed-clock"; 30 clock-frequency = <108000000>; 31 clock-output-names = "108MHz-clock"; 32 }; 33 34 soc { 35 /* 36 * Defined ranges: 37 * Common BCM283x peripherals 38 * BCM2711-specific peripherals 39 * ARM-local peripherals 40 */ 41 ranges = <0x7e000000 0x0 0xfe000000 0x01800000>, 42 <0x7c000000 0x0 0xfc000000 0x02000000>, 43 <0x40000000 0x0 0xff800000 0x00800000>; 44 /* Emulate a contiguous 30-bit address range for DMA */ 45 dma-ranges = <0xc0000000 0x0 0x00000000 0x40000000>; 46 47 /* 48 * This node is the provider for the enable-method for 49 * bringing up secondary cores. 50 */ 51 local_intc: interrupt-controller@40000000 { 52 compatible = "brcm,bcm2836-l1-intc"; 53 reg = <0x40000000 0x100>; 54 }; 55 56 gicv2: interrupt-controller@40041000 { 57 interrupt-controller; 58 #interrupt-cells = <3>; 59 compatible = "arm,gic-400"; 60 reg = <0x40041000 0x1000>, 61 <0x40042000 0x2000>, 62 <0x40044000 0x2000>, 63 <0x40046000 0x2000>; 64 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | 65 IRQ_TYPE_LEVEL_HIGH)>; 66 }; 67 68 avs_monitor: avs-monitor@7d5d2000 { 69 compatible = "brcm,bcm2711-avs-monitor", 70 "syscon", "simple-mfd"; 71 reg = <0x7d5d2000 0xf00>; 72 73 thermal: thermal { 74 compatible = "brcm,bcm2711-thermal"; 75 #thermal-sensor-cells = <0>; 76 }; 77 }; 78 79 dma: dma-controller@7e007000 { 80 compatible = "brcm,bcm2835-dma"; 81 reg = <0x7e007000 0xb00>; 82 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>, 83 <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>, 84 <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>, 85 <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>, 86 <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, 87 <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>, 88 <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>, 89 /* DMA lite 7 - 10 */ 90 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>, 91 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>, 92 <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>, 93 <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>; 94 interrupt-names = "dma0", 95 "dma1", 96 "dma2", 97 "dma3", 98 "dma4", 99 "dma5", 100 "dma6", 101 "dma7", 102 "dma8", 103 "dma9", 104 "dma10"; 105 #dma-cells = <1>; 106 brcm,dma-channel-mask = <0x07f5>; 107 }; 108 109 pm: watchdog@7e100000 { 110 compatible = "brcm,bcm2711-pm", "brcm,bcm2835-pm-wdt"; 111 #power-domain-cells = <1>; 112 #reset-cells = <1>; 113 reg = <0x7e100000 0x114>, 114 <0x7e00a000 0x24>, 115 <0x7ec11000 0x20>; 116 reg-names = "pm", "asb", "rpivid_asb"; 117 clocks = <&clocks BCM2835_CLOCK_V3D>, 118 <&clocks BCM2835_CLOCK_PERI_IMAGE>, 119 <&clocks BCM2835_CLOCK_H264>, 120 <&clocks BCM2835_CLOCK_ISP>; 121 clock-names = "v3d", "peri_image", "h264", "isp"; 122 system-power-controller; 123 }; 124 125 rng@7e104000 { 126 compatible = "brcm,bcm2711-rng200"; 127 reg = <0x7e104000 0x28>; 128 }; 129 130 uart2: serial@7e201400 { 131 compatible = "arm,pl011", "arm,primecell"; 132 reg = <0x7e201400 0x200>; 133 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; 134 clocks = <&clocks BCM2835_CLOCK_UART>, 135 <&clocks BCM2835_CLOCK_VPU>; 136 clock-names = "uartclk", "apb_pclk"; 137 arm,primecell-periphid = <0x00341011>; 138 status = "disabled"; 139 }; 140 141 uart3: serial@7e201600 { 142 compatible = "arm,pl011", "arm,primecell"; 143 reg = <0x7e201600 0x200>; 144 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; 145 clocks = <&clocks BCM2835_CLOCK_UART>, 146 <&clocks BCM2835_CLOCK_VPU>; 147 clock-names = "uartclk", "apb_pclk"; 148 arm,primecell-periphid = <0x00341011>; 149 status = "disabled"; 150 }; 151 152 uart4: serial@7e201800 { 153 compatible = "arm,pl011", "arm,primecell"; 154 reg = <0x7e201800 0x200>; 155 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; 156 clocks = <&clocks BCM2835_CLOCK_UART>, 157 <&clocks BCM2835_CLOCK_VPU>; 158 clock-names = "uartclk", "apb_pclk"; 159 arm,primecell-periphid = <0x00341011>; 160 status = "disabled"; 161 }; 162 163 uart5: serial@7e201a00 { 164 compatible = "arm,pl011", "arm,primecell"; 165 reg = <0x7e201a00 0x200>; 166 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; 167 clocks = <&clocks BCM2835_CLOCK_UART>, 168 <&clocks BCM2835_CLOCK_VPU>; 169 clock-names = "uartclk", "apb_pclk"; 170 arm,primecell-periphid = <0x00341011>; 171 status = "disabled"; 172 }; 173 174 spi3: spi@7e204600 { 175 compatible = "brcm,bcm2835-spi"; 176 reg = <0x7e204600 0x0200>; 177 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 178 clocks = <&clocks BCM2835_CLOCK_VPU>; 179 #address-cells = <1>; 180 #size-cells = <0>; 181 status = "disabled"; 182 }; 183 184 spi4: spi@7e204800 { 185 compatible = "brcm,bcm2835-spi"; 186 reg = <0x7e204800 0x0200>; 187 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 188 clocks = <&clocks BCM2835_CLOCK_VPU>; 189 #address-cells = <1>; 190 #size-cells = <0>; 191 status = "disabled"; 192 }; 193 194 spi5: spi@7e204a00 { 195 compatible = "brcm,bcm2835-spi"; 196 reg = <0x7e204a00 0x0200>; 197 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 198 clocks = <&clocks BCM2835_CLOCK_VPU>; 199 #address-cells = <1>; 200 #size-cells = <0>; 201 status = "disabled"; 202 }; 203 204 spi6: spi@7e204c00 { 205 compatible = "brcm,bcm2835-spi"; 206 reg = <0x7e204c00 0x0200>; 207 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 208 clocks = <&clocks BCM2835_CLOCK_VPU>; 209 #address-cells = <1>; 210 #size-cells = <0>; 211 status = "disabled"; 212 }; 213 214 i2c3: i2c@7e205600 { 215 compatible = "brcm,bcm2711-i2c", "brcm,bcm2835-i2c"; 216 reg = <0x7e205600 0x200>; 217 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 218 clocks = <&clocks BCM2835_CLOCK_VPU>; 219 #address-cells = <1>; 220 #size-cells = <0>; 221 status = "disabled"; 222 }; 223 224 i2c4: i2c@7e205800 { 225 compatible = "brcm,bcm2711-i2c", "brcm,bcm2835-i2c"; 226 reg = <0x7e205800 0x200>; 227 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 228 clocks = <&clocks BCM2835_CLOCK_VPU>; 229 #address-cells = <1>; 230 #size-cells = <0>; 231 status = "disabled"; 232 }; 233 234 i2c5: i2c@7e205a00 { 235 compatible = "brcm,bcm2711-i2c", "brcm,bcm2835-i2c"; 236 reg = <0x7e205a00 0x200>; 237 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 238 clocks = <&clocks BCM2835_CLOCK_VPU>; 239 #address-cells = <1>; 240 #size-cells = <0>; 241 status = "disabled"; 242 }; 243 244 i2c6: i2c@7e205c00 { 245 compatible = "brcm,bcm2711-i2c", "brcm,bcm2835-i2c"; 246 reg = <0x7e205c00 0x200>; 247 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 248 clocks = <&clocks BCM2835_CLOCK_VPU>; 249 #address-cells = <1>; 250 #size-cells = <0>; 251 status = "disabled"; 252 }; 253 254 pixelvalve0: pixelvalve@7e206000 { 255 compatible = "brcm,bcm2711-pixelvalve0"; 256 reg = <0x7e206000 0x100>; 257 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; 258 status = "disabled"; 259 }; 260 261 pixelvalve1: pixelvalve@7e207000 { 262 compatible = "brcm,bcm2711-pixelvalve1"; 263 reg = <0x7e207000 0x100>; 264 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; 265 status = "disabled"; 266 }; 267 268 pixelvalve2: pixelvalve@7e20a000 { 269 compatible = "brcm,bcm2711-pixelvalve2"; 270 reg = <0x7e20a000 0x100>; 271 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; 272 status = "disabled"; 273 }; 274 275 pwm1: pwm@7e20c800 { 276 compatible = "brcm,bcm2835-pwm"; 277 reg = <0x7e20c800 0x28>; 278 clocks = <&clocks BCM2835_CLOCK_PWM>; 279 assigned-clocks = <&clocks BCM2835_CLOCK_PWM>; 280 assigned-clock-rates = <10000000>; 281 #pwm-cells = <3>; 282 status = "disabled"; 283 }; 284 285 pixelvalve4: pixelvalve@7e216000 { 286 compatible = "brcm,bcm2711-pixelvalve4"; 287 reg = <0x7e216000 0x100>; 288 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; 289 status = "disabled"; 290 }; 291 292 hvs: hvs@7e400000 { 293 compatible = "brcm,bcm2711-hvs"; 294 reg = <0x7e400000 0x8000>; 295 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 296 }; 297 298 pixelvalve3: pixelvalve@7ec12000 { 299 compatible = "brcm,bcm2711-pixelvalve3"; 300 reg = <0x7ec12000 0x100>; 301 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; 302 status = "disabled"; 303 }; 304 305 vec: vec@7ec13000 { 306 compatible = "brcm,bcm2711-vec"; 307 reg = <0x7ec13000 0x1000>; 308 clocks = <&clocks BCM2835_CLOCK_VEC>; 309 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; 310 status = "disabled"; 311 }; 312 313 dvp: clock@7ef00000 { 314 compatible = "brcm,brcm2711-dvp"; 315 reg = <0x7ef00000 0x10>; 316 clocks = <&clk_108MHz>; 317 #clock-cells = <1>; 318 #reset-cells = <1>; 319 }; 320 321 aon_intr: interrupt-controller@7ef00100 { 322 compatible = "brcm,bcm2711-l2-intc", "brcm,l2-intc"; 323 reg = <0x7ef00100 0x30>; 324 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 325 interrupt-controller; 326 #interrupt-cells = <1>; 327 }; 328 329 hdmi0: hdmi@7ef00700 { 330 compatible = "brcm,bcm2711-hdmi0"; 331 reg = <0x7ef00700 0x300>, 332 <0x7ef00300 0x200>, 333 <0x7ef00f00 0x80>, 334 <0x7ef00f80 0x80>, 335 <0x7ef01b00 0x200>, 336 <0x7ef01f00 0x400>, 337 <0x7ef00200 0x80>, 338 <0x7ef04300 0x100>, 339 <0x7ef20000 0x100>; 340 reg-names = "hdmi", 341 "dvp", 342 "phy", 343 "rm", 344 "packet", 345 "metadata", 346 "csc", 347 "cec", 348 "hd"; 349 clock-names = "hdmi", "bvb", "audio", "cec"; 350 resets = <&dvp 0>; 351 interrupt-parent = <&aon_intr>; 352 interrupts = <0>, <1>, <2>, 353 <3>, <4>, <5>; 354 interrupt-names = "cec-tx", "cec-rx", "cec-low", 355 "wakeup", "hpd-connected", "hpd-removed"; 356 ddc = <&ddc0>; 357 dmas = <&dma 10>; 358 dma-names = "audio-rx"; 359 status = "disabled"; 360 }; 361 362 ddc0: i2c@7ef04500 { 363 compatible = "brcm,bcm2711-hdmi-i2c"; 364 reg = <0x7ef04500 0x100>, <0x7ef00b00 0x300>; 365 reg-names = "bsc", "auto-i2c"; 366 clock-frequency = <97500>; 367 status = "disabled"; 368 }; 369 370 hdmi1: hdmi@7ef05700 { 371 compatible = "brcm,bcm2711-hdmi1"; 372 reg = <0x7ef05700 0x300>, 373 <0x7ef05300 0x200>, 374 <0x7ef05f00 0x80>, 375 <0x7ef05f80 0x80>, 376 <0x7ef06b00 0x200>, 377 <0x7ef06f00 0x400>, 378 <0x7ef00280 0x80>, 379 <0x7ef09300 0x100>, 380 <0x7ef20000 0x100>; 381 reg-names = "hdmi", 382 "dvp", 383 "phy", 384 "rm", 385 "packet", 386 "metadata", 387 "csc", 388 "cec", 389 "hd"; 390 ddc = <&ddc1>; 391 clock-names = "hdmi", "bvb", "audio", "cec"; 392 resets = <&dvp 1>; 393 interrupt-parent = <&aon_intr>; 394 interrupts = <8>, <7>, <6>, 395 <9>, <10>, <11>; 396 interrupt-names = "cec-tx", "cec-rx", "cec-low", 397 "wakeup", "hpd-connected", "hpd-removed"; 398 dmas = <&dma 17>; 399 dma-names = "audio-rx"; 400 status = "disabled"; 401 }; 402 403 ddc1: i2c@7ef09500 { 404 compatible = "brcm,bcm2711-hdmi-i2c"; 405 reg = <0x7ef09500 0x100>, <0x7ef05b00 0x300>; 406 reg-names = "bsc", "auto-i2c"; 407 clock-frequency = <97500>; 408 status = "disabled"; 409 }; 410 }; 411 412 /* 413 * emmc2 has different DMA constraints based on SoC revisions. It was 414 * moved into its own bus, so as for RPi4's firmware to update them. 415 * The firmware will find whether the emmc2bus alias is defined, and if 416 * so, it'll edit the dma-ranges property below accordingly. 417 */ 418 emmc2bus: emmc2bus { 419 compatible = "simple-bus"; 420 #address-cells = <2>; 421 #size-cells = <1>; 422 423 ranges = <0x0 0x7e000000 0x0 0xfe000000 0x01800000>; 424 dma-ranges = <0x0 0xc0000000 0x0 0x00000000 0x40000000>; 425 426 emmc2: mmc@7e340000 { 427 compatible = "brcm,bcm2711-emmc2"; 428 reg = <0x0 0x7e340000 0x100>; 429 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>; 430 clocks = <&clocks BCM2711_CLOCK_EMMC2>; 431 status = "disabled"; 432 }; 433 }; 434 435 pmu { 436 compatible = "arm,cortex-a72-pmu"; 437 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, 438 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, 439 <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, 440 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 441 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; 442 }; 443 444 timer { 445 compatible = "arm,armv8-timer"; 446 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | 447 IRQ_TYPE_LEVEL_LOW)>, 448 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | 449 IRQ_TYPE_LEVEL_LOW)>, 450 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | 451 IRQ_TYPE_LEVEL_LOW)>, 452 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | 453 IRQ_TYPE_LEVEL_LOW)>; 454 }; 455 456 cpus: cpus { 457 #address-cells = <1>; 458 #size-cells = <0>; 459 enable-method = "brcm,bcm2836-smp"; // for ARM 32-bit 460 461 /* Source for d/i-cache-line-size and d/i-cache-sets 462 * https://developer.arm.com/documentation/100095/0003 463 * /Level-1-Memory-System/About-the-L1-memory-system?lang=en 464 * Source for d/i-cache-size 465 * https://www.raspberrypi.com/documentation/computers 466 * /processors.html#bcm2711 467 */ 468 cpu0: cpu@0 { 469 device_type = "cpu"; 470 compatible = "arm,cortex-a72"; 471 reg = <0>; 472 enable-method = "spin-table"; 473 cpu-release-addr = <0x0 0x000000d8>; 474 d-cache-size = <0x8000>; 475 d-cache-line-size = <64>; 476 d-cache-sets = <256>; // 32KiB(size)/64(line-size)=512ways/2-way set 477 i-cache-size = <0xc000>; 478 i-cache-line-size = <64>; 479 i-cache-sets = <256>; // 48KiB(size)/64(line-size)=768ways/3-way set 480 next-level-cache = <&l2>; 481 }; 482 483 cpu1: cpu@1 { 484 device_type = "cpu"; 485 compatible = "arm,cortex-a72"; 486 reg = <1>; 487 enable-method = "spin-table"; 488 cpu-release-addr = <0x0 0x000000e0>; 489 d-cache-size = <0x8000>; 490 d-cache-line-size = <64>; 491 d-cache-sets = <256>; // 32KiB(size)/64(line-size)=512ways/2-way set 492 i-cache-size = <0xc000>; 493 i-cache-line-size = <64>; 494 i-cache-sets = <256>; // 48KiB(size)/64(line-size)=768ways/3-way set 495 next-level-cache = <&l2>; 496 }; 497 498 cpu2: cpu@2 { 499 device_type = "cpu"; 500 compatible = "arm,cortex-a72"; 501 reg = <2>; 502 enable-method = "spin-table"; 503 cpu-release-addr = <0x0 0x000000e8>; 504 d-cache-size = <0x8000>; 505 d-cache-line-size = <64>; 506 d-cache-sets = <256>; // 32KiB(size)/64(line-size)=512ways/2-way set 507 i-cache-size = <0xc000>; 508 i-cache-line-size = <64>; 509 i-cache-sets = <256>; // 48KiB(size)/64(line-size)=768ways/3-way set 510 next-level-cache = <&l2>; 511 }; 512 513 cpu3: cpu@3 { 514 device_type = "cpu"; 515 compatible = "arm,cortex-a72"; 516 reg = <3>; 517 enable-method = "spin-table"; 518 cpu-release-addr = <0x0 0x000000f0>; 519 d-cache-size = <0x8000>; 520 d-cache-line-size = <64>; 521 d-cache-sets = <256>; // 32KiB(size)/64(line-size)=512ways/2-way set 522 i-cache-size = <0xc000>; 523 i-cache-line-size = <64>; 524 i-cache-sets = <256>; // 48KiB(size)/64(line-size)=768ways/3-way set 525 next-level-cache = <&l2>; 526 }; 527 528 /* Source for d/i-cache-line-size and d/i-cache-sets 529 * https://developer.arm.com/documentation/100095/0003 530 * /Level-2-Memory-System/About-the-L2-memory-system?lang=en 531 * Source for d/i-cache-size 532 * https://www.raspberrypi.com/documentation/computers 533 * /processors.html#bcm2711 534 */ 535 l2: l2-cache0 { 536 compatible = "cache"; 537 cache-unified; 538 cache-size = <0x100000>; 539 cache-line-size = <64>; 540 cache-sets = <1024>; // 1MiB(size)/64(line-size)=16384ways/16-way set 541 cache-level = <2>; 542 }; 543 }; 544 545 scb { 546 compatible = "simple-bus"; 547 #address-cells = <2>; 548 #size-cells = <1>; 549 550 ranges = <0x0 0x7c000000 0x0 0xfc000000 0x03800000>, 551 <0x6 0x00000000 0x6 0x00000000 0x40000000>; 552 553 pcie0: pcie@7d500000 { 554 compatible = "brcm,bcm2711-pcie"; 555 reg = <0x0 0x7d500000 0x9310>; 556 device_type = "pci"; 557 #address-cells = <3>; 558 #interrupt-cells = <1>; 559 #size-cells = <2>; 560 interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, 561 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; 562 interrupt-names = "pcie", "msi"; 563 interrupt-map-mask = <0x0 0x0 0x0 0x7>; 564 interrupt-map = <0 0 0 1 &gicv2 GIC_SPI 143 565 IRQ_TYPE_LEVEL_HIGH>, 566 <0 0 0 2 &gicv2 GIC_SPI 144 567 IRQ_TYPE_LEVEL_HIGH>, 568 <0 0 0 3 &gicv2 GIC_SPI 145 569 IRQ_TYPE_LEVEL_HIGH>, 570 <0 0 0 4 &gicv2 GIC_SPI 146 571 IRQ_TYPE_LEVEL_HIGH>; 572 msi-controller; 573 msi-parent = <&pcie0>; 574 575 ranges = <0x02000000 0x0 0xf8000000 0x6 0x00000000 576 0x0 0x04000000>; 577 /* 578 * The wrapper around the PCIe block has a bug 579 * preventing it from accessing beyond the first 3GB of 580 * memory. 581 */ 582 dma-ranges = <0x02000000 0x0 0x00000000 0x0 0x00000000 583 0x0 0xc0000000>; 584 brcm,enable-ssc; 585 }; 586 587 genet: ethernet@7d580000 { 588 compatible = "brcm,bcm2711-genet-v5"; 589 reg = <0x0 0x7d580000 0x10000>; 590 #address-cells = <0x1>; 591 #size-cells = <0x1>; 592 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>, 593 <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>; 594 status = "disabled"; 595 596 genet_mdio: mdio@e14 { 597 compatible = "brcm,genet-mdio-v5"; 598 reg = <0xe14 0x8>; 599 reg-names = "mdio"; 600 #address-cells = <0x1>; 601 #size-cells = <0x0>; 602 }; 603 }; 604 605 xhci: usb@7e9c0000 { 606 compatible = "brcm,bcm2711-xhci", "brcm,xhci-brcm-v2"; 607 reg = <0x0 0x7e9c0000 0x100000>; 608 #address-cells = <1>; 609 #size-cells = <0>; 610 interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>; 611 power-domains = <&pm BCM2835_POWER_DOMAIN_USB>; 612 /* DWC2 and this IP block share the same USB PHY, 613 * enabling both at the same time results in lockups. 614 * So keep this node disabled and let the bootloader 615 * decide which interface should be enabled. 616 */ 617 status = "disabled"; 618 }; 619 620 v3d: gpu@7ec00000 { 621 compatible = "brcm,2711-v3d"; 622 reg = <0x0 0x7ec00000 0x4000>, 623 <0x0 0x7ec04000 0x4000>; 624 reg-names = "hub", "core0"; 625 626 power-domains = <&pm BCM2835_POWER_DOMAIN_GRAFX_V3D>; 627 resets = <&pm BCM2835_RESET_V3D>; 628 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 629 }; 630 }; 631}; 632 633&clk_osc { 634 clock-frequency = <54000000>; 635}; 636 637&clocks { 638 compatible = "brcm,bcm2711-cprman"; 639}; 640 641&cpu_thermal { 642 coefficients = <(-487) 410040>; 643 thermal-sensors = <&thermal>; 644}; 645 646&dsi0 { 647 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; 648}; 649 650&dsi1 { 651 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 652 compatible = "brcm,bcm2711-dsi1"; 653}; 654 655&gpio { 656 compatible = "brcm,bcm2711-gpio"; 657 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 658 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 659 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 660 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 661 662 gpio-ranges = <&gpio 0 0 58>; 663 664 gpclk0_gpio49: gpclk0-gpio49 { 665 pin-gpclk { 666 pins = "gpio49"; 667 function = "alt1"; 668 bias-disable; 669 }; 670 }; 671 gpclk1_gpio50: gpclk1-gpio50 { 672 pin-gpclk { 673 pins = "gpio50"; 674 function = "alt1"; 675 bias-disable; 676 }; 677 }; 678 gpclk2_gpio51: gpclk2-gpio51 { 679 pin-gpclk { 680 pins = "gpio51"; 681 function = "alt1"; 682 bias-disable; 683 }; 684 }; 685 686 i2c0_gpio46: i2c0-gpio46 { 687 pin-sda { 688 function = "alt0"; 689 pins = "gpio46"; 690 bias-pull-up; 691 }; 692 pin-scl { 693 function = "alt0"; 694 pins = "gpio47"; 695 bias-disable; 696 }; 697 }; 698 i2c1_gpio46: i2c1-gpio46 { 699 pin-sda { 700 function = "alt1"; 701 pins = "gpio46"; 702 bias-pull-up; 703 }; 704 pin-scl { 705 function = "alt1"; 706 pins = "gpio47"; 707 bias-disable; 708 }; 709 }; 710 i2c3_gpio2: i2c3-gpio2 { 711 pin-sda { 712 function = "alt5"; 713 pins = "gpio2"; 714 bias-pull-up; 715 }; 716 pin-scl { 717 function = "alt5"; 718 pins = "gpio3"; 719 bias-disable; 720 }; 721 }; 722 i2c3_gpio4: i2c3-gpio4 { 723 pin-sda { 724 function = "alt5"; 725 pins = "gpio4"; 726 bias-pull-up; 727 }; 728 pin-scl { 729 function = "alt5"; 730 pins = "gpio5"; 731 bias-disable; 732 }; 733 }; 734 i2c4_gpio6: i2c4-gpio6 { 735 pin-sda { 736 function = "alt5"; 737 pins = "gpio6"; 738 bias-pull-up; 739 }; 740 pin-scl { 741 function = "alt5"; 742 pins = "gpio7"; 743 bias-disable; 744 }; 745 }; 746 i2c4_gpio8: i2c4-gpio8 { 747 pin-sda { 748 function = "alt5"; 749 pins = "gpio8"; 750 bias-pull-up; 751 }; 752 pin-scl { 753 function = "alt5"; 754 pins = "gpio9"; 755 bias-disable; 756 }; 757 }; 758 i2c5_gpio10: i2c5-gpio10 { 759 pin-sda { 760 function = "alt5"; 761 pins = "gpio10"; 762 bias-pull-up; 763 }; 764 pin-scl { 765 function = "alt5"; 766 pins = "gpio11"; 767 bias-disable; 768 }; 769 }; 770 i2c5_gpio12: i2c5-gpio12 { 771 pin-sda { 772 function = "alt5"; 773 pins = "gpio12"; 774 bias-pull-up; 775 }; 776 pin-scl { 777 function = "alt5"; 778 pins = "gpio13"; 779 bias-disable; 780 }; 781 }; 782 i2c6_gpio0: i2c6-gpio0 { 783 pin-sda { 784 function = "alt5"; 785 pins = "gpio0"; 786 bias-pull-up; 787 }; 788 pin-scl { 789 function = "alt5"; 790 pins = "gpio1"; 791 bias-disable; 792 }; 793 }; 794 i2c6_gpio22: i2c6-gpio22 { 795 pin-sda { 796 function = "alt5"; 797 pins = "gpio22"; 798 bias-pull-up; 799 }; 800 pin-scl { 801 function = "alt5"; 802 pins = "gpio23"; 803 bias-disable; 804 }; 805 }; 806 i2c_slave_gpio8: i2c-slave-gpio8 { 807 pins-i2c-slave { 808 pins = "gpio8", 809 "gpio9", 810 "gpio10", 811 "gpio11"; 812 function = "alt3"; 813 }; 814 }; 815 816 jtag_gpio48: jtag-gpio48 { 817 pins-jtag { 818 pins = "gpio48", 819 "gpio49", 820 "gpio50", 821 "gpio51", 822 "gpio52", 823 "gpio53"; 824 function = "alt4"; 825 }; 826 }; 827 828 mii_gpio28: mii-gpio28 { 829 pins-mii { 830 pins = "gpio28", 831 "gpio29", 832 "gpio30", 833 "gpio31"; 834 function = "alt4"; 835 }; 836 }; 837 mii_gpio36: mii-gpio36 { 838 pins-mii { 839 pins = "gpio36", 840 "gpio37", 841 "gpio38", 842 "gpio39"; 843 function = "alt5"; 844 }; 845 }; 846 847 pcm_gpio50: pcm-gpio50 { 848 pins-pcm { 849 pins = "gpio50", 850 "gpio51", 851 "gpio52", 852 "gpio53"; 853 function = "alt2"; 854 }; 855 }; 856 857 pwm0_0_gpio12: pwm0-0-gpio12 { 858 pin-pwm { 859 pins = "gpio12"; 860 function = "alt0"; 861 bias-disable; 862 }; 863 }; 864 pwm0_0_gpio18: pwm0-0-gpio18 { 865 pin-pwm { 866 pins = "gpio18"; 867 function = "alt5"; 868 bias-disable; 869 }; 870 }; 871 pwm1_0_gpio40: pwm1-0-gpio40 { 872 pin-pwm { 873 pins = "gpio40"; 874 function = "alt0"; 875 bias-disable; 876 }; 877 }; 878 pwm0_1_gpio13: pwm0-1-gpio13 { 879 pin-pwm { 880 pins = "gpio13"; 881 function = "alt0"; 882 bias-disable; 883 }; 884 }; 885 pwm0_1_gpio19: pwm0-1-gpio19 { 886 pin-pwm { 887 pins = "gpio19"; 888 function = "alt5"; 889 bias-disable; 890 }; 891 }; 892 pwm1_1_gpio41: pwm1-1-gpio41 { 893 pin-pwm { 894 pins = "gpio41"; 895 function = "alt0"; 896 bias-disable; 897 }; 898 }; 899 pwm0_1_gpio45: pwm0-1-gpio45 { 900 pin-pwm { 901 pins = "gpio45"; 902 function = "alt0"; 903 bias-disable; 904 }; 905 }; 906 pwm0_0_gpio52: pwm0-0-gpio52 { 907 pin-pwm { 908 pins = "gpio52"; 909 function = "alt1"; 910 bias-disable; 911 }; 912 }; 913 pwm0_1_gpio53: pwm0-1-gpio53 { 914 pin-pwm { 915 pins = "gpio53"; 916 function = "alt1"; 917 bias-disable; 918 }; 919 }; 920 921 rgmii_gpio35: rgmii-gpio35 { 922 pin-start-stop { 923 pins = "gpio35"; 924 function = "alt4"; 925 }; 926 pin-rx-ok { 927 pins = "gpio36"; 928 function = "alt4"; 929 }; 930 }; 931 rgmii_irq_gpio34: rgmii-irq-gpio34 { 932 pin-irq { 933 pins = "gpio34"; 934 function = "alt5"; 935 }; 936 }; 937 rgmii_irq_gpio39: rgmii-irq-gpio39 { 938 pin-irq { 939 pins = "gpio39"; 940 function = "alt4"; 941 }; 942 }; 943 rgmii_mdio_gpio28: rgmii-mdio-gpio28 { 944 pins-mdio { 945 pins = "gpio28", 946 "gpio29"; 947 function = "alt5"; 948 }; 949 }; 950 rgmii_mdio_gpio37: rgmii-mdio-gpio37 { 951 pins-mdio { 952 pins = "gpio37", 953 "gpio38"; 954 function = "alt4"; 955 }; 956 }; 957 958 spi0_gpio46: spi0-gpio46 { 959 pins-spi { 960 pins = "gpio46", 961 "gpio47", 962 "gpio48", 963 "gpio49"; 964 function = "alt2"; 965 }; 966 }; 967 spi2_gpio46: spi2-gpio46 { 968 pins-spi { 969 pins = "gpio46", 970 "gpio47", 971 "gpio48", 972 "gpio49", 973 "gpio50"; 974 function = "alt5"; 975 }; 976 }; 977 spi3_gpio0: spi3-gpio0 { 978 pins-spi { 979 pins = "gpio0", 980 "gpio1", 981 "gpio2", 982 "gpio3"; 983 function = "alt3"; 984 }; 985 }; 986 spi4_gpio4: spi4-gpio4 { 987 pins-spi { 988 pins = "gpio4", 989 "gpio5", 990 "gpio6", 991 "gpio7"; 992 function = "alt3"; 993 }; 994 }; 995 spi5_gpio12: spi5-gpio12 { 996 pins-spi { 997 pins = "gpio12", 998 "gpio13", 999 "gpio14", 1000 "gpio15"; 1001 function = "alt3"; 1002 }; 1003 }; 1004 spi6_gpio18: spi6-gpio18 { 1005 pins-spi { 1006 pins = "gpio18", 1007 "gpio19", 1008 "gpio20", 1009 "gpio21"; 1010 function = "alt3"; 1011 }; 1012 }; 1013 1014 uart2_gpio0: uart2-gpio0 { 1015 pin-tx { 1016 pins = "gpio0"; 1017 function = "alt4"; 1018 bias-disable; 1019 }; 1020 pin-rx { 1021 pins = "gpio1"; 1022 function = "alt4"; 1023 bias-pull-up; 1024 }; 1025 }; 1026 uart2_ctsrts_gpio2: uart2-ctsrts-gpio2 { 1027 pin-cts { 1028 pins = "gpio2"; 1029 function = "alt4"; 1030 bias-pull-up; 1031 }; 1032 pin-rts { 1033 pins = "gpio3"; 1034 function = "alt4"; 1035 bias-disable; 1036 }; 1037 }; 1038 uart3_gpio4: uart3-gpio4 { 1039 pin-tx { 1040 pins = "gpio4"; 1041 function = "alt4"; 1042 bias-disable; 1043 }; 1044 pin-rx { 1045 pins = "gpio5"; 1046 function = "alt4"; 1047 bias-pull-up; 1048 }; 1049 }; 1050 uart3_ctsrts_gpio6: uart3-ctsrts-gpio6 { 1051 pin-cts { 1052 pins = "gpio6"; 1053 function = "alt4"; 1054 bias-pull-up; 1055 }; 1056 pin-rts { 1057 pins = "gpio7"; 1058 function = "alt4"; 1059 bias-disable; 1060 }; 1061 }; 1062 uart4_gpio8: uart4-gpio8 { 1063 pin-tx { 1064 pins = "gpio8"; 1065 function = "alt4"; 1066 bias-disable; 1067 }; 1068 pin-rx { 1069 pins = "gpio9"; 1070 function = "alt4"; 1071 bias-pull-up; 1072 }; 1073 }; 1074 uart4_ctsrts_gpio10: uart4-ctsrts-gpio10 { 1075 pin-cts { 1076 pins = "gpio10"; 1077 function = "alt4"; 1078 bias-pull-up; 1079 }; 1080 pin-rts { 1081 pins = "gpio11"; 1082 function = "alt4"; 1083 bias-disable; 1084 }; 1085 }; 1086 uart5_gpio12: uart5-gpio12 { 1087 pin-tx { 1088 pins = "gpio12"; 1089 function = "alt4"; 1090 bias-disable; 1091 }; 1092 pin-rx { 1093 pins = "gpio13"; 1094 function = "alt4"; 1095 bias-pull-up; 1096 }; 1097 }; 1098 uart5_ctsrts_gpio14: uart5-ctsrts-gpio14 { 1099 pin-cts { 1100 pins = "gpio14"; 1101 function = "alt4"; 1102 bias-pull-up; 1103 }; 1104 pin-rts { 1105 pins = "gpio15"; 1106 function = "alt4"; 1107 bias-disable; 1108 }; 1109 }; 1110}; 1111 1112&rmem { 1113 #address-cells = <2>; 1114}; 1115 1116&csi0 { 1117 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; 1118}; 1119 1120&csi1 { 1121 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 1122}; 1123 1124&cma { 1125 /* 1126 * arm64 reserves the CMA by default somewhere in ZONE_DMA32, 1127 * that's not good enough for the BCM2711 as some devices can 1128 * only address the lower 1G of memory (ZONE_DMA). 1129 */ 1130 alloc-ranges = <0x0 0x00000000 0x40000000>; 1131}; 1132 1133&i2c0 { 1134 compatible = "brcm,bcm2711-i2c", "brcm,bcm2835-i2c"; 1135 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 1136}; 1137 1138&i2c1 { 1139 compatible = "brcm,bcm2711-i2c", "brcm,bcm2835-i2c"; 1140 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 1141}; 1142 1143&mailbox { 1144 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 1145}; 1146 1147&sdhci { 1148 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>; 1149}; 1150 1151&sdhost { 1152 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; 1153}; 1154 1155&spi { 1156 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 1157}; 1158 1159&spi1 { 1160 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; 1161}; 1162 1163&spi2 { 1164 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; 1165}; 1166 1167&system_timer { 1168 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>, 1169 <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 1170 <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>, 1171 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; 1172}; 1173 1174&txp { 1175 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 1176}; 1177 1178&uart0 { 1179 arm,primecell-periphid = <0x00341011>; 1180 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; 1181}; 1182 1183&uart1 { 1184 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; 1185}; 1186 1187&usb { 1188 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 1189}; 1190 1191&vec { 1192 compatible = "brcm,bcm2711-vec"; 1193 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; 1194};
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