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aspeed-g4.dtsi
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linux-6.19.14/arch/arm/boot/dts/aspeed/aspeed-g4.dtsi
1// SPDX-License-Identifier: GPL-2.0+ 2#include <dt-bindings/clock/aspeed-clock.h> 3 4/ { 5 model = "Aspeed BMC"; 6 compatible = "aspeed,ast2400"; 7 #address-cells = <1>; 8 #size-cells = <1>; 9 interrupt-parent = <&vic>; 10 11 aliases { 12 i2c0 = &i2c0; 13 i2c1 = &i2c1; 14 i2c2 = &i2c2; 15 i2c3 = &i2c3; 16 i2c4 = &i2c4; 17 i2c5 = &i2c5; 18 i2c6 = &i2c6; 19 i2c7 = &i2c7; 20 i2c8 = &i2c8; 21 i2c9 = &i2c9; 22 i2c10 = &i2c10; 23 i2c11 = &i2c11; 24 i2c12 = &i2c12; 25 i2c13 = &i2c13; 26 serial0 = &uart1; 27 serial1 = &uart2; 28 serial2 = &uart3; 29 serial3 = &uart4; 30 serial4 = &uart5; 31 serial5 = &vuart; 32 }; 33 34 cpus { 35 #address-cells = <1>; 36 #size-cells = <0>; 37 38 cpu@0 { 39 compatible = "arm,arm926ej-s"; 40 device_type = "cpu"; 41 reg = <0>; 42 }; 43 }; 44 45 memory@40000000 { 46 device_type = "memory"; 47 reg = <0x40000000 0>; 48 }; 49 50 ahb { 51 compatible = "simple-bus"; 52 #address-cells = <1>; 53 #size-cells = <1>; 54 ranges; 55 56 fmc: spi@1e620000 { 57 reg = <0x1e620000 0x94>, <0x20000000 0x10000000>; 58 #address-cells = <1>; 59 #size-cells = <0>; 60 compatible = "aspeed,ast2400-fmc"; 61 clocks = <&syscon ASPEED_CLK_AHB>; 62 status = "disabled"; 63 interrupts = <19>; 64 flash@0 { 65 reg = < 0 >; 66 compatible = "jedec,spi-nor"; 67 spi-rx-bus-width = <2>; 68 spi-max-frequency = <50000000>; 69 status = "disabled"; 70 }; 71 flash@1 { 72 reg = < 1 >; 73 compatible = "jedec,spi-nor"; 74 spi-rx-bus-width = <2>; 75 spi-max-frequency = <50000000>; 76 status = "disabled"; 77 }; 78 flash@2 { 79 reg = < 2 >; 80 compatible = "jedec,spi-nor"; 81 spi-rx-bus-width = <2>; 82 spi-max-frequency = <50000000>; 83 status = "disabled"; 84 }; 85 flash@3 { 86 reg = < 3 >; 87 compatible = "jedec,spi-nor"; 88 spi-rx-bus-width = <2>; 89 spi-max-frequency = <50000000>; 90 status = "disabled"; 91 }; 92 flash@4 { 93 reg = < 4 >; 94 compatible = "jedec,spi-nor"; 95 spi-rx-bus-width = <2>; 96 spi-max-frequency = <50000000>; 97 status = "disabled"; 98 }; 99 }; 100 101 spi: spi@1e630000 { 102 reg = <0x1e630000 0x18>, <0x30000000 0x10000000>; 103 #address-cells = <1>; 104 #size-cells = <0>; 105 compatible = "aspeed,ast2400-spi"; 106 clocks = <&syscon ASPEED_CLK_AHB>; 107 status = "disabled"; 108 flash@0 { 109 reg = < 0 >; 110 compatible = "jedec,spi-nor"; 111 spi-max-frequency = <50000000>; 112 spi-rx-bus-width = <2>; 113 status = "disabled"; 114 }; 115 }; 116 117 vic: interrupt-controller@1e6c0080 { 118 compatible = "aspeed,ast2400-vic"; 119 interrupt-controller; 120 #interrupt-cells = <1>; 121 valid-sources = <0xffffffff 0x0007ffff>; 122 reg = <0x1e6c0080 0x80>; 123 }; 124 125 cvic: interrupt-controller@1e6c2000 { 126 compatible = "aspeed,ast2400-cvic", "aspeed,cvic"; 127 valid-sources = <0x7fffffff>; 128 reg = <0x1e6c2000 0x80>; 129 }; 130 131 mac0: ethernet@1e660000 { 132 compatible = "aspeed,ast2400-mac", "faraday,ftgmac100"; 133 reg = <0x1e660000 0x180>; 134 interrupts = <2>; 135 clocks = <&syscon ASPEED_CLK_GATE_MAC1CLK>; 136 status = "disabled"; 137 }; 138 139 mac1: ethernet@1e680000 { 140 compatible = "aspeed,ast2400-mac", "faraday,ftgmac100"; 141 reg = <0x1e680000 0x180>; 142 interrupts = <3>; 143 clocks = <&syscon ASPEED_CLK_GATE_MAC2CLK>; 144 status = "disabled"; 145 }; 146 147 ehci0: usb@1e6a1000 { 148 compatible = "aspeed,ast2400-ehci", "generic-ehci"; 149 reg = <0x1e6a1000 0x100>; 150 interrupts = <5>; 151 clocks = <&syscon ASPEED_CLK_GATE_USBPORT1CLK>; 152 pinctrl-names = "default"; 153 pinctrl-0 = <&pinctrl_usb2h_default>; 154 status = "disabled"; 155 }; 156 157 uhci: usb@1e6b0000 { 158 compatible = "aspeed,ast2400-uhci", "generic-uhci"; 159 reg = <0x1e6b0000 0x100>; 160 interrupts = <14>; 161 #ports = <3>; 162 clocks = <&syscon ASPEED_CLK_GATE_USBUHCICLK>; 163 status = "disabled"; 164 /* 165 * No default pinmux, it will follow EHCI, use an explicit pinmux 166 * override if you don't enable EHCI 167 */ 168 }; 169 170 vhub: usb-vhub@1e6a0000 { 171 compatible = "aspeed,ast2400-usb-vhub"; 172 reg = <0x1e6a0000 0x300>; 173 interrupts = <5>; 174 clocks = <&syscon ASPEED_CLK_GATE_USBPORT1CLK>; 175 aspeed,vhub-downstream-ports = <5>; 176 aspeed,vhub-generic-endpoints = <15>; 177 pinctrl-names = "default"; 178 pinctrl-0 = <&pinctrl_usb2d_default>; 179 status = "disabled"; 180 }; 181 182 apb { 183 compatible = "simple-bus"; 184 #address-cells = <1>; 185 #size-cells = <1>; 186 ranges; 187 188 syscon: syscon@1e6e2000 { 189 compatible = "aspeed,ast2400-scu", "syscon", "simple-mfd"; 190 reg = <0x1e6e2000 0x1a8>; 191 #address-cells = <1>; 192 #size-cells = <1>; 193 ranges = <0 0x1e6e2000 0x1000>; 194 #clock-cells = <1>; 195 #reset-cells = <1>; 196 197 p2a: p2a-control@2c { 198 reg = <0x2c 0x4>; 199 compatible = "aspeed,ast2400-p2a-ctrl"; 200 status = "disabled"; 201 }; 202 203 silicon-id@7c { 204 compatible = "aspeed,ast2400-silicon-id", "aspeed,silicon-id"; 205 reg = <0x7c 0x4>; 206 }; 207 208 pinctrl: pinctrl@80 { 209 reg = <0x80 0x18>, <0xa0 0x10>; 210 compatible = "aspeed,ast2400-pinctrl"; 211 }; 212 }; 213 214 rng: hwrng@1e6e2078 { 215 compatible = "timeriomem_rng"; 216 reg = <0x1e6e2078 0x4>; 217 period = <1>; 218 quality = <100>; 219 }; 220 221 adc: adc@1e6e9000 { 222 compatible = "aspeed,ast2400-adc"; 223 reg = <0x1e6e9000 0xb0>; 224 clocks = <&syscon ASPEED_CLK_APB>; 225 resets = <&syscon ASPEED_RESET_ADC>; 226 #io-channel-cells = <1>; 227 status = "disabled"; 228 }; 229 230 sram: sram@1e720000 { 231 compatible = "mmio-sram"; 232 reg = <0x1e720000 0x8000>; // 32K 233 ranges; 234 #address-cells = <1>; 235 #size-cells = <1>; 236 }; 237 238 video: video@1e700000 { 239 compatible = "aspeed,ast2400-video-engine"; 240 reg = <0x1e700000 0x1000>; 241 clocks = <&syscon ASPEED_CLK_GATE_VCLK>, 242 <&syscon ASPEED_CLK_GATE_ECLK>; 243 clock-names = "vclk", "eclk"; 244 interrupts = <7>; 245 status = "disabled"; 246 }; 247 248 sdmmc: sd-controller@1e740000 { 249 compatible = "aspeed,ast2400-sd-controller"; 250 reg = <0x1e740000 0x100>; 251 #address-cells = <1>; 252 #size-cells = <1>; 253 ranges = <0 0x1e740000 0x10000>; 254 clocks = <&syscon ASPEED_CLK_GATE_SDCLK>; 255 status = "disabled"; 256 257 sdhci0: sdhci@100 { 258 compatible = "aspeed,ast2400-sdhci"; 259 reg = <0x100 0x100>; 260 interrupts = <26>; 261 sdhci,auto-cmd12; 262 clocks = <&syscon ASPEED_CLK_SDIO>; 263 status = "disabled"; 264 }; 265 266 sdhci1: sdhci@200 { 267 compatible = "aspeed,ast2400-sdhci"; 268 reg = <0x200 0x100>; 269 interrupts = <26>; 270 sdhci,auto-cmd12; 271 clocks = <&syscon ASPEED_CLK_SDIO>; 272 status = "disabled"; 273 }; 274 }; 275 276 gpio: gpio@1e780000 { 277 #gpio-cells = <2>; 278 gpio-controller; 279 compatible = "aspeed,ast2400-gpio"; 280 reg = <0x1e780000 0x1000>; 281 interrupts = <20>; 282 gpio-ranges = <&pinctrl 0 0 220>; 283 clocks = <&syscon ASPEED_CLK_APB>; 284 interrupt-controller; 285 #interrupt-cells = <2>; 286 }; 287 288 timer: timer@1e782000 { 289 /* This timer is a Faraday FTTMR010 derivative */ 290 compatible = "aspeed,ast2400-timer"; 291 reg = <0x1e782000 0x90>; 292 interrupts = <16 17 18 35 36 37 38 39>; 293 clocks = <&syscon ASPEED_CLK_APB>; 294 clock-names = "PCLK"; 295 }; 296 297 rtc: rtc@1e781000 { 298 compatible = "aspeed,ast2400-rtc"; 299 reg = <0x1e781000 0x18>; 300 status = "disabled"; 301 }; 302 303 uart1: serial@1e783000 { 304 compatible = "ns16550a"; 305 reg = <0x1e783000 0x20>; 306 reg-shift = <2>; 307 interrupts = <9>; 308 clocks = <&syscon ASPEED_CLK_GATE_UART1CLK>; 309 resets = <&lpc_reset 4>; 310 no-loopback-test; 311 status = "disabled"; 312 }; 313 314 uart5: serial@1e784000 { 315 compatible = "ns16550a"; 316 reg = <0x1e784000 0x20>; 317 reg-shift = <2>; 318 interrupts = <10>; 319 clocks = <&syscon ASPEED_CLK_GATE_UART5CLK>; 320 no-loopback-test; 321 status = "disabled"; 322 }; 323 324 wdt1: watchdog@1e785000 { 325 compatible = "aspeed,ast2400-wdt"; 326 reg = <0x1e785000 0x1c>; 327 clocks = <&syscon ASPEED_CLK_APB>; 328 }; 329 330 wdt2: watchdog@1e785020 { 331 compatible = "aspeed,ast2400-wdt"; 332 reg = <0x1e785020 0x1c>; 333 clocks = <&syscon ASPEED_CLK_APB>; 334 }; 335 336 pwm_tacho: pwm-tacho-controller@1e786000 { 337 compatible = "aspeed,ast2400-pwm-tacho"; 338 #address-cells = <1>; 339 #size-cells = <0>; 340 reg = <0x1e786000 0x1000>; 341 clocks = <&syscon ASPEED_CLK_24M>; 342 resets = <&syscon ASPEED_RESET_PWM>; 343 status = "disabled"; 344 }; 345 346 vuart: serial@1e787000 { 347 compatible = "aspeed,ast2400-vuart"; 348 reg = <0x1e787000 0x40>; 349 reg-shift = <2>; 350 interrupts = <8>; 351 clocks = <&syscon ASPEED_CLK_APB>; 352 no-loopback-test; 353 status = "disabled"; 354 }; 355 356 lpc: lpc@1e789000 { 357 compatible = "aspeed,ast2400-lpc-v2", "simple-mfd", "syscon"; 358 reg = <0x1e789000 0x1000>; 359 360 #address-cells = <1>; 361 #size-cells = <1>; 362 ranges = <0x0 0x1e789000 0x1000>; 363 364 lpc_ctrl: lpc-ctrl@80 { 365 compatible = "aspeed,ast2400-lpc-ctrl"; 366 reg = <0x80 0x10>; 367 clocks = <&syscon ASPEED_CLK_GATE_LCLK>; 368 status = "disabled"; 369 }; 370 371 lpc_snoop: lpc-snoop@90 { 372 compatible = "aspeed,ast2400-lpc-snoop"; 373 reg = <0x90 0x8>; 374 interrupts = <8>; 375 clocks = <&syscon ASPEED_CLK_GATE_LCLK>; 376 status = "disabled"; 377 }; 378 379 lhc: lhc@a0 { 380 compatible = "aspeed,ast2400-lhc"; 381 reg = <0xa0 0x24 0xc8 0x8>; 382 }; 383 384 lpc_reset: reset-controller@98 { 385 compatible = "aspeed,ast2400-lpc-reset"; 386 reg = <0x98 0x4>; 387 #reset-cells = <1>; 388 }; 389 390 ibt: ibt@140 { 391 compatible = "aspeed,ast2400-ibt-bmc"; 392 reg = <0x140 0x18>; 393 interrupts = <8>; 394 clocks = <&syscon ASPEED_CLK_GATE_LCLK>; 395 status = "disabled"; 396 }; 397 398 uart_routing: uart-routing@9c { 399 compatible = "aspeed,ast2400-uart-routing"; 400 reg = <0x9c 0x4>; 401 status = "disabled"; 402 }; 403 }; 404 405 peci0: peci-controller@1e78b000 { 406 compatible = "aspeed,ast2400-peci"; 407 reg = <0x1e78b000 0x60>; 408 interrupts = <15>; 409 clocks = <&syscon ASPEED_CLK_GATE_REFCLK>; 410 resets = <&syscon ASPEED_RESET_PECI>; 411 cmd-timeout-ms = <1000>; 412 clock-frequency = <1000000>; 413 status = "disabled"; 414 }; 415 416 uart2: serial@1e78d000 { 417 compatible = "ns16550a"; 418 reg = <0x1e78d000 0x20>; 419 reg-shift = <2>; 420 interrupts = <32>; 421 clocks = <&syscon ASPEED_CLK_GATE_UART2CLK>; 422 resets = <&lpc_reset 5>; 423 no-loopback-test; 424 status = "disabled"; 425 }; 426 427 uart3: serial@1e78e000 { 428 compatible = "ns16550a"; 429 reg = <0x1e78e000 0x20>; 430 reg-shift = <2>; 431 interrupts = <33>; 432 clocks = <&syscon ASPEED_CLK_GATE_UART3CLK>; 433 resets = <&lpc_reset 6>; 434 no-loopback-test; 435 status = "disabled"; 436 }; 437 438 uart4: serial@1e78f000 { 439 compatible = "ns16550a"; 440 reg = <0x1e78f000 0x20>; 441 reg-shift = <2>; 442 interrupts = <34>; 443 clocks = <&syscon ASPEED_CLK_GATE_UART4CLK>; 444 resets = <&lpc_reset 7>; 445 no-loopback-test; 446 status = "disabled"; 447 }; 448 449 i2c: bus@1e78a000 { 450 compatible = "simple-bus"; 451 #address-cells = <1>; 452 #size-cells = <1>; 453 ranges = <0 0x1e78a000 0x1000>; 454 }; 455 }; 456 }; 457}; 458 459&i2c { 460 i2c_ic: interrupt-controller@0 { 461 #interrupt-cells = <1>; 462 compatible = "aspeed,ast2400-i2c-ic"; 463 reg = <0x0 0x40>; 464 interrupts = <12>; 465 interrupt-controller; 466 }; 467 468 i2c0: i2c@40 { 469 #address-cells = <1>; 470 #size-cells = <0>; 471 472 reg = <0x40 0x40>; 473 compatible = "aspeed,ast2400-i2c-bus"; 474 clocks = <&syscon ASPEED_CLK_APB>; 475 resets = <&syscon ASPEED_RESET_I2C>; 476 bus-frequency = <100000>; 477 interrupts = <0>; 478 interrupt-parent = <&i2c_ic>; 479 status = "disabled"; 480 /* Does not need pinctrl properties */ 481 }; 482 483 i2c1: i2c@80 { 484 #address-cells = <1>; 485 #size-cells = <0>; 486 487 reg = <0x80 0x40>; 488 compatible = "aspeed,ast2400-i2c-bus"; 489 clocks = <&syscon ASPEED_CLK_APB>; 490 resets = <&syscon ASPEED_RESET_I2C>; 491 bus-frequency = <100000>; 492 interrupts = <1>; 493 interrupt-parent = <&i2c_ic>; 494 status = "disabled"; 495 /* Does not need pinctrl properties */ 496 }; 497 498 i2c2: i2c@c0 { 499 #address-cells = <1>; 500 #size-cells = <0>; 501 502 reg = <0xc0 0x40>; 503 compatible = "aspeed,ast2400-i2c-bus"; 504 clocks = <&syscon ASPEED_CLK_APB>; 505 resets = <&syscon ASPEED_RESET_I2C>; 506 bus-frequency = <100000>; 507 interrupts = <2>; 508 interrupt-parent = <&i2c_ic>; 509 pinctrl-names = "default"; 510 pinctrl-0 = <&pinctrl_i2c3_default>; 511 status = "disabled"; 512 }; 513 514 i2c3: i2c@100 { 515 #address-cells = <1>; 516 #size-cells = <0>; 517 518 reg = <0x100 0x40>; 519 compatible = "aspeed,ast2400-i2c-bus"; 520 clocks = <&syscon ASPEED_CLK_APB>; 521 resets = <&syscon ASPEED_RESET_I2C>; 522 bus-frequency = <100000>; 523 interrupts = <3>; 524 interrupt-parent = <&i2c_ic>; 525 pinctrl-names = "default"; 526 pinctrl-0 = <&pinctrl_i2c4_default>; 527 status = "disabled"; 528 }; 529 530 i2c4: i2c@140 { 531 #address-cells = <1>; 532 #size-cells = <0>; 533 534 reg = <0x140 0x40>; 535 compatible = "aspeed,ast2400-i2c-bus"; 536 clocks = <&syscon ASPEED_CLK_APB>; 537 resets = <&syscon ASPEED_RESET_I2C>; 538 bus-frequency = <100000>; 539 interrupts = <4>; 540 interrupt-parent = <&i2c_ic>; 541 pinctrl-names = "default"; 542 pinctrl-0 = <&pinctrl_i2c5_default>; 543 status = "disabled"; 544 }; 545 546 i2c5: i2c@180 { 547 #address-cells = <1>; 548 #size-cells = <0>; 549 550 reg = <0x180 0x40>; 551 compatible = "aspeed,ast2400-i2c-bus"; 552 clocks = <&syscon ASPEED_CLK_APB>; 553 resets = <&syscon ASPEED_RESET_I2C>; 554 bus-frequency = <100000>; 555 interrupts = <5>; 556 interrupt-parent = <&i2c_ic>; 557 pinctrl-names = "default"; 558 pinctrl-0 = <&pinctrl_i2c6_default>; 559 status = "disabled"; 560 }; 561 562 i2c6: i2c@1c0 { 563 #address-cells = <1>; 564 #size-cells = <0>; 565 566 reg = <0x1c0 0x40>; 567 compatible = "aspeed,ast2400-i2c-bus"; 568 clocks = <&syscon ASPEED_CLK_APB>; 569 resets = <&syscon ASPEED_RESET_I2C>; 570 bus-frequency = <100000>; 571 interrupts = <6>; 572 interrupt-parent = <&i2c_ic>; 573 pinctrl-names = "default"; 574 pinctrl-0 = <&pinctrl_i2c7_default>; 575 status = "disabled"; 576 }; 577 578 i2c7: i2c@300 { 579 #address-cells = <1>; 580 #size-cells = <0>; 581 582 reg = <0x300 0x40>; 583 compatible = "aspeed,ast2400-i2c-bus"; 584 clocks = <&syscon ASPEED_CLK_APB>; 585 resets = <&syscon ASPEED_RESET_I2C>; 586 bus-frequency = <100000>; 587 interrupts = <7>; 588 interrupt-parent = <&i2c_ic>; 589 pinctrl-names = "default"; 590 pinctrl-0 = <&pinctrl_i2c8_default>; 591 status = "disabled"; 592 }; 593 594 i2c8: i2c@340 { 595 #address-cells = <1>; 596 #size-cells = <0>; 597 598 reg = <0x340 0x40>; 599 compatible = "aspeed,ast2400-i2c-bus"; 600 clocks = <&syscon ASPEED_CLK_APB>; 601 resets = <&syscon ASPEED_RESET_I2C>; 602 bus-frequency = <100000>; 603 interrupts = <8>; 604 interrupt-parent = <&i2c_ic>; 605 pinctrl-names = "default"; 606 pinctrl-0 = <&pinctrl_i2c9_default>; 607 status = "disabled"; 608 }; 609 610 i2c9: i2c@380 { 611 #address-cells = <1>; 612 #size-cells = <0>; 613 614 reg = <0x380 0x40>; 615 compatible = "aspeed,ast2400-i2c-bus"; 616 clocks = <&syscon ASPEED_CLK_APB>; 617 resets = <&syscon ASPEED_RESET_I2C>; 618 bus-frequency = <100000>; 619 interrupts = <9>; 620 interrupt-parent = <&i2c_ic>; 621 pinctrl-names = "default"; 622 pinctrl-0 = <&pinctrl_i2c10_default>; 623 status = "disabled"; 624 }; 625 626 i2c10: i2c@3c0 { 627 #address-cells = <1>; 628 #size-cells = <0>; 629 630 reg = <0x3c0 0x40>; 631 compatible = "aspeed,ast2400-i2c-bus"; 632 clocks = <&syscon ASPEED_CLK_APB>; 633 resets = <&syscon ASPEED_RESET_I2C>; 634 bus-frequency = <100000>; 635 interrupts = <10>; 636 interrupt-parent = <&i2c_ic>; 637 pinctrl-names = "default"; 638 pinctrl-0 = <&pinctrl_i2c11_default>; 639 status = "disabled"; 640 }; 641 642 i2c11: i2c@400 { 643 #address-cells = <1>; 644 #size-cells = <0>; 645 646 reg = <0x400 0x40>; 647 compatible = "aspeed,ast2400-i2c-bus"; 648 clocks = <&syscon ASPEED_CLK_APB>; 649 resets = <&syscon ASPEED_RESET_I2C>; 650 bus-frequency = <100000>; 651 interrupts = <11>; 652 interrupt-parent = <&i2c_ic>; 653 pinctrl-names = "default"; 654 pinctrl-0 = <&pinctrl_i2c12_default>; 655 status = "disabled"; 656 }; 657 658 i2c12: i2c@440 { 659 #address-cells = <1>; 660 #size-cells = <0>; 661 662 reg = <0x440 0x40>; 663 compatible = "aspeed,ast2400-i2c-bus"; 664 clocks = <&syscon ASPEED_CLK_APB>; 665 resets = <&syscon ASPEED_RESET_I2C>; 666 bus-frequency = <100000>; 667 interrupts = <12>; 668 interrupt-parent = <&i2c_ic>; 669 pinctrl-names = "default"; 670 pinctrl-0 = <&pinctrl_i2c13_default>; 671 status = "disabled"; 672 }; 673 674 i2c13: i2c@480 { 675 #address-cells = <1>; 676 #size-cells = <0>; 677 678 reg = <0x480 0x40>; 679 compatible = "aspeed,ast2400-i2c-bus"; 680 clocks = <&syscon ASPEED_CLK_APB>; 681 resets = <&syscon ASPEED_RESET_I2C>; 682 bus-frequency = <100000>; 683 interrupts = <13>; 684 interrupt-parent = <&i2c_ic>; 685 pinctrl-names = "default"; 686 pinctrl-0 = <&pinctrl_i2c14_default>; 687 status = "disabled"; 688 }; 689}; 690 691&pinctrl { 692 pinctrl_acpi_default: acpi_default { 693 function = "ACPI"; 694 groups = "ACPI"; 695 }; 696 697 pinctrl_adc0_default: adc0_default { 698 function = "ADC0"; 699 groups = "ADC0"; 700 }; 701 702 pinctrl_adc1_default: adc1_default { 703 function = "ADC1"; 704 groups = "ADC1"; 705 }; 706 707 pinctrl_adc10_default: adc10_default { 708 function = "ADC10"; 709 groups = "ADC10"; 710 }; 711 712 pinctrl_adc11_default: adc11_default { 713 function = "ADC11"; 714 groups = "ADC11"; 715 }; 716 717 pinctrl_adc12_default: adc12_default { 718 function = "ADC12"; 719 groups = "ADC12"; 720 }; 721 722 pinctrl_adc13_default: adc13_default { 723 function = "ADC13"; 724 groups = "ADC13"; 725 }; 726 727 pinctrl_adc14_default: adc14_default { 728 function = "ADC14"; 729 groups = "ADC14"; 730 }; 731 732 pinctrl_adc15_default: adc15_default { 733 function = "ADC15"; 734 groups = "ADC15"; 735 }; 736 737 pinctrl_adc2_default: adc2_default { 738 function = "ADC2"; 739 groups = "ADC2"; 740 }; 741 742 pinctrl_adc3_default: adc3_default { 743 function = "ADC3"; 744 groups = "ADC3"; 745 }; 746 747 pinctrl_adc4_default: adc4_default { 748 function = "ADC4"; 749 groups = "ADC4"; 750 }; 751 752 pinctrl_adc5_default: adc5_default { 753 function = "ADC5"; 754 groups = "ADC5"; 755 }; 756 757 pinctrl_adc6_default: adc6_default { 758 function = "ADC6"; 759 groups = "ADC6"; 760 }; 761 762 pinctrl_adc7_default: adc7_default { 763 function = "ADC7"; 764 groups = "ADC7"; 765 }; 766 767 pinctrl_adc8_default: adc8_default { 768 function = "ADC8"; 769 groups = "ADC8"; 770 }; 771 772 pinctrl_adc9_default: adc9_default { 773 function = "ADC9"; 774 groups = "ADC9"; 775 }; 776 777 pinctrl_bmcint_default: bmcint_default { 778 function = "BMCINT"; 779 groups = "BMCINT"; 780 }; 781 782 pinctrl_ddcclk_default: ddcclk_default { 783 function = "DDCCLK"; 784 groups = "DDCCLK"; 785 }; 786 787 pinctrl_ddcdat_default: ddcdat_default { 788 function = "DDCDAT"; 789 groups = "DDCDAT"; 790 }; 791 792 pinctrl_extrst_default: extrst_default { 793 function = "EXTRST"; 794 groups = "EXTRST"; 795 }; 796 797 pinctrl_flack_default: flack_default { 798 function = "FLACK"; 799 groups = "FLACK"; 800 }; 801 802 pinctrl_flbusy_default: flbusy_default { 803 function = "FLBUSY"; 804 groups = "FLBUSY"; 805 }; 806 807 pinctrl_flwp_default: flwp_default { 808 function = "FLWP"; 809 groups = "FLWP"; 810 }; 811 812 pinctrl_gpid_default: gpid_default { 813 function = "GPID"; 814 groups = "GPID"; 815 }; 816 817 pinctrl_gpid0_default: gpid0_default { 818 function = "GPID0"; 819 groups = "GPID0"; 820 }; 821 822 pinctrl_gpid2_default: gpid2_default { 823 function = "GPID2"; 824 groups = "GPID2"; 825 }; 826 827 pinctrl_gpid4_default: gpid4_default { 828 function = "GPID4"; 829 groups = "GPID4"; 830 }; 831 832 pinctrl_gpid6_default: gpid6_default { 833 function = "GPID6"; 834 groups = "GPID6"; 835 }; 836 837 pinctrl_gpie0_default: gpie0_default { 838 function = "GPIE0"; 839 groups = "GPIE0"; 840 }; 841 842 pinctrl_gpie2_default: gpie2_default { 843 function = "GPIE2"; 844 groups = "GPIE2"; 845 }; 846 847 pinctrl_gpie4_default: gpie4_default { 848 function = "GPIE4"; 849 groups = "GPIE4"; 850 }; 851 852 pinctrl_gpie6_default: gpie6_default { 853 function = "GPIE6"; 854 groups = "GPIE6"; 855 }; 856 857 pinctrl_i2c10_default: i2c10_default { 858 function = "I2C10"; 859 groups = "I2C10"; 860 }; 861 862 pinctrl_i2c11_default: i2c11_default { 863 function = "I2C11"; 864 groups = "I2C11"; 865 }; 866 867 pinctrl_i2c12_default: i2c12_default { 868 function = "I2C12"; 869 groups = "I2C12"; 870 }; 871 872 pinctrl_i2c13_default: i2c13_default { 873 function = "I2C13"; 874 groups = "I2C13"; 875 }; 876 877 pinctrl_i2c14_default: i2c14_default { 878 function = "I2C14"; 879 groups = "I2C14"; 880 }; 881 882 pinctrl_i2c3_default: i2c3_default { 883 function = "I2C3"; 884 groups = "I2C3"; 885 }; 886 887 pinctrl_i2c4_default: i2c4_default { 888 function = "I2C4"; 889 groups = "I2C4"; 890 }; 891 892 pinctrl_i2c5_default: i2c5_default { 893 function = "I2C5"; 894 groups = "I2C5"; 895 }; 896 897 pinctrl_i2c6_default: i2c6_default { 898 function = "I2C6"; 899 groups = "I2C6"; 900 }; 901 902 pinctrl_i2c7_default: i2c7_default { 903 function = "I2C7"; 904 groups = "I2C7"; 905 }; 906 907 pinctrl_i2c8_default: i2c8_default { 908 function = "I2C8"; 909 groups = "I2C8"; 910 }; 911 912 pinctrl_i2c9_default: i2c9_default { 913 function = "I2C9"; 914 groups = "I2C9"; 915 }; 916 917 pinctrl_lpcpd_default: lpcpd_default { 918 function = "LPCPD"; 919 groups = "LPCPD"; 920 }; 921 922 pinctrl_lpcpme_default: lpcpme_default { 923 function = "LPCPME"; 924 groups = "LPCPME"; 925 }; 926 927 pinctrl_lpcrst_default: lpcrst_default { 928 function = "LPCRST"; 929 groups = "LPCRST"; 930 }; 931 932 pinctrl_lpcsmi_default: lpcsmi_default { 933 function = "LPCSMI"; 934 groups = "LPCSMI"; 935 }; 936 937 pinctrl_mac1link_default: mac1link_default { 938 function = "MAC1LINK"; 939 groups = "MAC1LINK"; 940 }; 941 942 pinctrl_mac2link_default: mac2link_default { 943 function = "MAC2LINK"; 944 groups = "MAC2LINK"; 945 }; 946 947 pinctrl_mdio1_default: mdio1_default { 948 function = "MDIO1"; 949 groups = "MDIO1"; 950 }; 951 952 pinctrl_mdio2_default: mdio2_default { 953 function = "MDIO2"; 954 groups = "MDIO2"; 955 }; 956 957 pinctrl_ncts1_default: ncts1_default { 958 function = "NCTS1"; 959 groups = "NCTS1"; 960 }; 961 962 pinctrl_ncts2_default: ncts2_default { 963 function = "NCTS2"; 964 groups = "NCTS2"; 965 }; 966 967 pinctrl_ncts3_default: ncts3_default { 968 function = "NCTS3"; 969 groups = "NCTS3"; 970 }; 971 972 pinctrl_ncts4_default: ncts4_default { 973 function = "NCTS4"; 974 groups = "NCTS4"; 975 }; 976 977 pinctrl_ndcd1_default: ndcd1_default { 978 function = "NDCD1"; 979 groups = "NDCD1"; 980 }; 981 982 pinctrl_ndcd2_default: ndcd2_default { 983 function = "NDCD2"; 984 groups = "NDCD2"; 985 }; 986 987 pinctrl_ndcd3_default: ndcd3_default { 988 function = "NDCD3"; 989 groups = "NDCD3"; 990 }; 991 992 pinctrl_ndcd4_default: ndcd4_default { 993 function = "NDCD4"; 994 groups = "NDCD4"; 995 }; 996 997 pinctrl_ndsr1_default: ndsr1_default { 998 function = "NDSR1"; 999 groups = "NDSR1"; 1000 }; 1001 1002 pinctrl_ndsr2_default: ndsr2_default { 1003 function = "NDSR2"; 1004 groups = "NDSR2"; 1005 }; 1006 1007 pinctrl_ndsr3_default: ndsr3_default { 1008 function = "NDSR3"; 1009 groups = "NDSR3"; 1010 }; 1011 1012 pinctrl_ndsr4_default: ndsr4_default { 1013 function = "NDSR4"; 1014 groups = "NDSR4"; 1015 }; 1016 1017 pinctrl_ndtr1_default: ndtr1_default { 1018 function = "NDTR1"; 1019 groups = "NDTR1"; 1020 }; 1021 1022 pinctrl_ndtr2_default: ndtr2_default { 1023 function = "NDTR2"; 1024 groups = "NDTR2"; 1025 }; 1026 1027 pinctrl_ndtr3_default: ndtr3_default { 1028 function = "NDTR3"; 1029 groups = "NDTR3"; 1030 }; 1031 1032 pinctrl_ndtr4_default: ndtr4_default { 1033 function = "NDTR4"; 1034 groups = "NDTR4"; 1035 }; 1036 1037 pinctrl_ndts4_default: ndts4_default { 1038 function = "NDTS4"; 1039 groups = "NDTS4"; 1040 }; 1041 1042 pinctrl_nri1_default: nri1_default { 1043 function = "NRI1"; 1044 groups = "NRI1"; 1045 }; 1046 1047 pinctrl_nri2_default: nri2_default { 1048 function = "NRI2"; 1049 groups = "NRI2"; 1050 }; 1051 1052 pinctrl_nri3_default: nri3_default { 1053 function = "NRI3"; 1054 groups = "NRI3"; 1055 }; 1056 1057 pinctrl_nri4_default: nri4_default { 1058 function = "NRI4"; 1059 groups = "NRI4"; 1060 }; 1061 1062 pinctrl_nrts1_default: nrts1_default { 1063 function = "NRTS1"; 1064 groups = "NRTS1"; 1065 }; 1066 1067 pinctrl_nrts2_default: nrts2_default { 1068 function = "NRTS2"; 1069 groups = "NRTS2"; 1070 }; 1071 1072 pinctrl_nrts3_default: nrts3_default { 1073 function = "NRTS3"; 1074 groups = "NRTS3"; 1075 }; 1076 1077 pinctrl_oscclk_default: oscclk_default { 1078 function = "OSCCLK"; 1079 groups = "OSCCLK"; 1080 }; 1081 1082 pinctrl_pwm0_default: pwm0_default { 1083 function = "PWM0"; 1084 groups = "PWM0"; 1085 }; 1086 1087 pinctrl_pwm1_default: pwm1_default { 1088 function = "PWM1"; 1089 groups = "PWM1"; 1090 }; 1091 1092 pinctrl_pwm2_default: pwm2_default { 1093 function = "PWM2"; 1094 groups = "PWM2"; 1095 }; 1096 1097 pinctrl_pwm3_default: pwm3_default { 1098 function = "PWM3"; 1099 groups = "PWM3"; 1100 }; 1101 1102 pinctrl_pwm4_default: pwm4_default { 1103 function = "PWM4"; 1104 groups = "PWM4"; 1105 }; 1106 1107 pinctrl_pwm5_default: pwm5_default { 1108 function = "PWM5"; 1109 groups = "PWM5"; 1110 }; 1111 1112 pinctrl_pwm6_default: pwm6_default { 1113 function = "PWM6"; 1114 groups = "PWM6"; 1115 }; 1116 1117 pinctrl_pwm7_default: pwm7_default { 1118 function = "PWM7"; 1119 groups = "PWM7"; 1120 }; 1121 1122 pinctrl_rgmii1_default: rgmii1_default { 1123 function = "RGMII1"; 1124 groups = "RGMII1"; 1125 }; 1126 1127 pinctrl_rgmii2_default: rgmii2_default { 1128 function = "RGMII2"; 1129 groups = "RGMII2"; 1130 }; 1131 1132 pinctrl_rmii1_default: rmii1_default { 1133 function = "RMII1"; 1134 groups = "RMII1"; 1135 }; 1136 1137 pinctrl_rmii2_default: rmii2_default { 1138 function = "RMII2"; 1139 groups = "RMII2"; 1140 }; 1141 1142 pinctrl_rom16_default: rom16_default { 1143 function = "ROM16"; 1144 groups = "ROM16"; 1145 }; 1146 1147 pinctrl_rom8_default: rom8_default { 1148 function = "ROM8"; 1149 groups = "ROM8"; 1150 }; 1151 1152 pinctrl_romcs1_default: romcs1_default { 1153 function = "ROMCS1"; 1154 groups = "ROMCS1"; 1155 }; 1156 1157 pinctrl_romcs2_default: romcs2_default { 1158 function = "ROMCS2"; 1159 groups = "ROMCS2"; 1160 }; 1161 1162 pinctrl_romcs3_default: romcs3_default { 1163 function = "ROMCS3"; 1164 groups = "ROMCS3"; 1165 }; 1166 1167 pinctrl_romcs4_default: romcs4_default { 1168 function = "ROMCS4"; 1169 groups = "ROMCS4"; 1170 }; 1171 1172 pinctrl_rxd1_default: rxd1_default { 1173 function = "RXD1"; 1174 groups = "RXD1"; 1175 }; 1176 1177 pinctrl_rxd2_default: rxd2_default { 1178 function = "RXD2"; 1179 groups = "RXD2"; 1180 }; 1181 1182 pinctrl_rxd3_default: rxd3_default { 1183 function = "RXD3"; 1184 groups = "RXD3"; 1185 }; 1186 1187 pinctrl_rxd4_default: rxd4_default { 1188 function = "RXD4"; 1189 groups = "RXD4"; 1190 }; 1191 1192 pinctrl_salt1_default: salt1_default { 1193 function = "SALT1"; 1194 groups = "SALT1"; 1195 }; 1196 1197 pinctrl_salt2_default: salt2_default { 1198 function = "SALT2"; 1199 groups = "SALT2"; 1200 }; 1201 1202 pinctrl_salt3_default: salt3_default { 1203 function = "SALT3"; 1204 groups = "SALT3"; 1205 }; 1206 1207 pinctrl_salt4_default: salt4_default { 1208 function = "SALT4"; 1209 groups = "SALT4"; 1210 }; 1211 1212 pinctrl_sd1_default: sd1_default { 1213 function = "SD1"; 1214 groups = "SD1"; 1215 }; 1216 1217 pinctrl_sd2_default: sd2_default { 1218 function = "SD2"; 1219 groups = "SD2"; 1220 }; 1221 1222 pinctrl_sgpmck_default: sgpmck_default { 1223 function = "SGPMCK"; 1224 groups = "SGPMCK"; 1225 }; 1226 1227 pinctrl_sgpmi_default: sgpmi_default { 1228 function = "SGPMI"; 1229 groups = "SGPMI"; 1230 }; 1231 1232 pinctrl_sgpmld_default: sgpmld_default { 1233 function = "SGPMLD"; 1234 groups = "SGPMLD"; 1235 }; 1236 1237 pinctrl_sgpmo_default: sgpmo_default { 1238 function = "SGPMO"; 1239 groups = "SGPMO"; 1240 }; 1241 1242 pinctrl_sgpsck_default: sgpsck_default { 1243 function = "SGPSCK"; 1244 groups = "SGPSCK"; 1245 }; 1246 1247 pinctrl_sgpsi0_default: sgpsi0_default { 1248 function = "SGPSI0"; 1249 groups = "SGPSI0"; 1250 }; 1251 1252 pinctrl_sgpsi1_default: sgpsi1_default { 1253 function = "SGPSI1"; 1254 groups = "SGPSI1"; 1255 }; 1256 1257 pinctrl_sgpsld_default: sgpsld_default { 1258 function = "SGPSLD"; 1259 groups = "SGPSLD"; 1260 }; 1261 1262 pinctrl_sioonctrl_default: sioonctrl_default { 1263 function = "SIOONCTRL"; 1264 groups = "SIOONCTRL"; 1265 }; 1266 1267 pinctrl_siopbi_default: siopbi_default { 1268 function = "SIOPBI"; 1269 groups = "SIOPBI"; 1270 }; 1271 1272 pinctrl_siopbo_default: siopbo_default { 1273 function = "SIOPBO"; 1274 groups = "SIOPBO"; 1275 }; 1276 1277 pinctrl_siopwreq_default: siopwreq_default { 1278 function = "SIOPWREQ"; 1279 groups = "SIOPWREQ"; 1280 }; 1281 1282 pinctrl_siopwrgd_default: siopwrgd_default { 1283 function = "SIOPWRGD"; 1284 groups = "SIOPWRGD"; 1285 }; 1286 1287 pinctrl_sios3_default: sios3_default { 1288 function = "SIOS3"; 1289 groups = "SIOS3"; 1290 }; 1291 1292 pinctrl_sios5_default: sios5_default { 1293 function = "SIOS5"; 1294 groups = "SIOS5"; 1295 }; 1296 1297 pinctrl_siosci_default: siosci_default { 1298 function = "SIOSCI"; 1299 groups = "SIOSCI"; 1300 }; 1301 1302 pinctrl_spi1_default: spi1_default { 1303 function = "SPI1"; 1304 groups = "SPI1"; 1305 }; 1306 1307 pinctrl_spi1debug_default: spi1debug_default { 1308 function = "SPI1DEBUG"; 1309 groups = "SPI1DEBUG"; 1310 }; 1311 1312 pinctrl_spi1passthru_default: spi1passthru_default { 1313 function = "SPI1PASSTHRU"; 1314 groups = "SPI1PASSTHRU"; 1315 }; 1316 1317 pinctrl_spics1_default: spics1_default { 1318 function = "SPICS1"; 1319 groups = "SPICS1"; 1320 }; 1321 1322 pinctrl_timer3_default: timer3_default { 1323 function = "TIMER3"; 1324 groups = "TIMER3"; 1325 }; 1326 1327 pinctrl_timer4_default: timer4_default { 1328 function = "TIMER4"; 1329 groups = "TIMER4"; 1330 }; 1331 1332 pinctrl_timer5_default: timer5_default { 1333 function = "TIMER5"; 1334 groups = "TIMER5"; 1335 }; 1336 1337 pinctrl_timer6_default: timer6_default { 1338 function = "TIMER6"; 1339 groups = "TIMER6"; 1340 }; 1341 1342 pinctrl_timer7_default: timer7_default { 1343 function = "TIMER7"; 1344 groups = "TIMER7"; 1345 }; 1346 1347 pinctrl_timer8_default: timer8_default { 1348 function = "TIMER8"; 1349 groups = "TIMER8"; 1350 }; 1351 1352 pinctrl_txd1_default: txd1_default { 1353 function = "TXD1"; 1354 groups = "TXD1"; 1355 }; 1356 1357 pinctrl_txd2_default: txd2_default { 1358 function = "TXD2"; 1359 groups = "TXD2"; 1360 }; 1361 1362 pinctrl_txd3_default: txd3_default { 1363 function = "TXD3"; 1364 groups = "TXD3"; 1365 }; 1366 1367 pinctrl_txd4_default: txd4_default { 1368 function = "TXD4"; 1369 groups = "TXD4"; 1370 }; 1371 1372 pinctrl_uart6_default: uart6_default { 1373 function = "UART6"; 1374 groups = "UART6"; 1375 }; 1376 1377 pinctrl_usbcki_default: usbcki_default { 1378 function = "USBCKI"; 1379 groups = "USBCKI"; 1380 }; 1381 1382 pinctrl_usb2h_default: usb2h_default { 1383 function = "USB2H1"; 1384 groups = "USB2H1"; 1385 }; 1386 1387 pinctrl_usb2d_default: usb2d_default { 1388 function = "USB2D1"; 1389 groups = "USB2D1"; 1390 }; 1391 1392 pinctrl_vgabios_rom_default: vgabios_rom_default { 1393 function = "VGABIOS_ROM"; 1394 groups = "VGABIOS_ROM"; 1395 }; 1396 1397 pinctrl_vgahs_default: vgahs_default { 1398 function = "VGAHS"; 1399 groups = "VGAHS"; 1400 }; 1401 1402 pinctrl_vgavs_default: vgavs_default { 1403 function = "VGAVS"; 1404 groups = "VGAVS"; 1405 }; 1406 1407 pinctrl_vpi18_default: vpi18_default { 1408 function = "VPI18"; 1409 groups = "VPI18"; 1410 }; 1411 1412 pinctrl_vpi24_default: vpi24_default { 1413 function = "VPI24"; 1414 groups = "VPI24"; 1415 }; 1416 1417 pinctrl_vpi30_default: vpi30_default { 1418 function = "VPI30"; 1419 groups = "VPI30"; 1420 }; 1421 1422 pinctrl_vpo12_default: vpo12_default { 1423 function = "VPO12"; 1424 groups = "VPO12"; 1425 }; 1426 1427 pinctrl_vpo24_default: vpo24_default { 1428 function = "VPO24"; 1429 groups = "VPO24"; 1430 }; 1431 1432 pinctrl_wdtrst1_default: wdtrst1_default { 1433 function = "WDTRST1"; 1434 groups = "WDTRST1"; 1435 }; 1436 1437 pinctrl_wdtrst2_default: wdtrst2_default { 1438 function = "WDTRST2"; 1439 groups = "WDTRST2"; 1440 }; 1441};
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