sys_cabriolet.c

  1// SPDX-License-Identifier: GPL-2.0
  2/*
  3 *	linux/arch/alpha/kernel/sys_cabriolet.c
  4 *
  5 *	Copyright (C) 1995 David A Rusling
  6 *	Copyright (C) 1996 Jay A Estabrook
  7 *	Copyright (C) 1998, 1999, 2000 Richard Henderson
  8 *
  9 * Code supporting the PC164 and LX164.
 10 */
 11
 12#include <linux/kernel.h>
 13#include <linux/types.h>
 14#include <linux/mm.h>
 15#include <linux/sched.h>
 16#include <linux/pci.h>
 17#include <linux/init.h>
 18#include <linux/bitops.h>
 19
 20#include <asm/ptrace.h>
 21#include <asm/dma.h>
 22#include <asm/irq.h>
 23#include <asm/mmu_context.h>
 24#include <asm/io.h>
 25#include <asm/core_cia.h>
 26#include <asm/tlbflush.h>
 27
 28#include "proto.h"
 29#include "irq_impl.h"
 30#include "pci_impl.h"
 31#include "machvec_impl.h"
 32#include "pc873xx.h"
 33
 34/* Note mask bit is true for DISABLED irqs.  */
 35static unsigned long cached_irq_mask = ~0UL;
 36
 37static inline void
 38cabriolet_update_irq_hw(unsigned int irq, unsigned long mask)
 39{
 40	int ofs = (irq - 16) / 8;
 41	outb(mask >> (16 + ofs * 8), 0x804 + ofs);
 42}
 43
 44static inline void
 45cabriolet_enable_irq(struct irq_data *d)
 46{
 47	cabriolet_update_irq_hw(d->irq, cached_irq_mask &= ~(1UL << d->irq));
 48}
 49
 50static void
 51cabriolet_disable_irq(struct irq_data *d)
 52{
 53	cabriolet_update_irq_hw(d->irq, cached_irq_mask |= 1UL << d->irq);
 54}
 55
 56static struct irq_chip cabriolet_irq_type = {
 57	.name		= "CABRIOLET",
 58	.irq_unmask	= cabriolet_enable_irq,
 59	.irq_mask	= cabriolet_disable_irq,
 60	.irq_mask_ack	= cabriolet_disable_irq,
 61};
 62
 63static void 
 64cabriolet_device_interrupt(unsigned long v)
 65{
 66	unsigned long pld;
 67	unsigned int i;
 68
 69	/* Read the interrupt summary registers */
 70	pld = inb(0x804) | (inb(0x805) << 8) | (inb(0x806) << 16);
 71
 72	/*
 73	 * Now for every possible bit set, work through them and call
 74	 * the appropriate interrupt handler.
 75	 */
 76	while (pld) {
 77		i = ffz(~pld);
 78		pld &= pld - 1;	/* clear least bit set */
 79		if (i == 4) {
 80			isa_device_interrupt(v);
 81		} else {
 82			handle_irq(16 + i);
 83		}
 84	}
 85}
 86
 87static void __init
 88common_init_irq(void (*srm_dev_int)(unsigned long v))
 89{
 90	init_i8259a_irqs();
 91
 92	if (alpha_using_srm) {
 93		alpha_mv.device_interrupt = srm_dev_int;
 94		init_srm_irqs(35, 0);
 95	}
 96	else {
 97		long i;
 98
 99		outb(0xff, 0x804);
100		outb(0xff, 0x805);
101		outb(0xff, 0x806);
102
103		for (i = 16; i < 35; ++i) {
104			irq_set_chip_and_handler(i, &cabriolet_irq_type,
105						 handle_level_irq);
106			irq_set_status_flags(i, IRQ_LEVEL);
107		}
108	}
109
110	common_init_isa_dma();
111	if (request_irq(16 + 4, no_action, 0, "isa-cascade", NULL))
112		pr_err("Failed to register isa-cascade interrupt\n");
113}
114
115#ifndef CONFIG_ALPHA_PC164
116static void __init
117cabriolet_init_irq(void)
118{
119	common_init_irq(srm_device_interrupt);
120}
121#endif
122
123#if defined(CONFIG_ALPHA_GENERIC) || defined(CONFIG_ALPHA_PC164)
124/* In theory, the PC164 has the same interrupt hardware as the other
125   Cabriolet based systems.  However, something got screwed up late
126   in the development cycle which broke the interrupt masking hardware.
127   Repeat, it is not possible to mask and ack interrupts.  At all.
128
129   In an attempt to work around this, while processing interrupts,
130   we do not allow the IPL to drop below what it is currently.  This
131   prevents the possibility of recursion.  
132
133   ??? Another option might be to force all PCI devices to use edge
134   triggered rather than level triggered interrupts.  That might be
135   too invasive though.  */
136
137static void
138pc164_srm_device_interrupt(unsigned long v)
139{
140	__min_ipl = getipl();
141	srm_device_interrupt(v);
142	__min_ipl = 0;
143}
144
145static void
146pc164_device_interrupt(unsigned long v)
147{
148	__min_ipl = getipl();
149	cabriolet_device_interrupt(v);
150	__min_ipl = 0;
151}
152
153static void __init
154pc164_init_irq(void)
155{
156	common_init_irq(pc164_srm_device_interrupt);
157}
158#endif
159
160/*
161 * The EB66+ is very similar to the EB66 except that it does not have
162 * the on-board NCR and Tulip chips.  In the code below, I have used
163 * slot number to refer to the id select line and *not* the slot
164 * number used in the EB66+ documentation.  However, in the table,
165 * I've given the slot number, the id select line and the Jxx number
166 * that's printed on the board.  The interrupt pins from the PCI slots
167 * are wired into 3 interrupt summary registers at 0x804, 0x805 and
168 * 0x806 ISA.
169 *
170 * In the table, -1 means don't assign an IRQ number.  This is usually
171 * because it is the Saturn IO (SIO) PCI/ISA Bridge Chip.
172 */
173
174static inline int
175eb66p_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
176{
177	static char irq_tab[5][5] = {
178		/*INT  INTA  INTB  INTC   INTD */
179		{16+0, 16+0, 16+5,  16+9, 16+13},  /* IdSel 6,  slot 0, J25 */
180		{16+1, 16+1, 16+6, 16+10, 16+14},  /* IdSel 7,  slot 1, J26 */
181		{  -1,   -1,   -1,    -1,    -1},  /* IdSel 8,  SIO         */
182		{16+2, 16+2, 16+7, 16+11, 16+15},  /* IdSel 9,  slot 2, J27 */
183		{16+3, 16+3, 16+8, 16+12,  16+6}   /* IdSel 10, slot 3, J28 */
184	};
185	const long min_idsel = 6, max_idsel = 10, irqs_per_slot = 5;
186	return COMMON_TABLE_LOOKUP;
187}
188
189
190/*
191 * The AlphaPC64 is very similar to the EB66+ except that its slots
192 * are numbered differently.  In the code below, I have used slot
193 * number to refer to the id select line and *not* the slot number
194 * used in the AlphaPC64 documentation.  However, in the table, I've
195 * given the slot number, the id select line and the Jxx number that's
196 * printed on the board.  The interrupt pins from the PCI slots are
197 * wired into 3 interrupt summary registers at 0x804, 0x805 and 0x806
198 * ISA.
199 *
200 * In the table, -1 means don't assign an IRQ number.  This is usually
201 * because it is the Saturn IO (SIO) PCI/ISA Bridge Chip.
202 */
203
204static inline int
205cabriolet_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
206{
207	static char irq_tab[5][5] = {
208		/*INT   INTA  INTB  INTC   INTD */
209		{ 16+2, 16+2, 16+7, 16+11, 16+15}, /* IdSel 5,  slot 2, J21 */
210		{ 16+0, 16+0, 16+5,  16+9, 16+13}, /* IdSel 6,  slot 0, J19 */
211		{ 16+1, 16+1, 16+6, 16+10, 16+14}, /* IdSel 7,  slot 1, J20 */
212		{   -1,   -1,   -1,    -1,    -1}, /* IdSel 8,  SIO         */
213		{ 16+3, 16+3, 16+8, 16+12, 16+16}  /* IdSel 9,  slot 3, J22 */
214	};
215	const long min_idsel = 5, max_idsel = 9, irqs_per_slot = 5;
216	return COMMON_TABLE_LOOKUP;
217}
218
219static inline void __init
220cabriolet_enable_ide(void)
221{
222	if (pc873xx_probe() == -1) {
223		printk(KERN_ERR "Probing for PC873xx Super IO chip failed.\n");
224	 } else {
225		printk(KERN_INFO "Found %s Super IO chip at 0x%x\n",
226			pc873xx_get_model(), pc873xx_get_base());
227
228		pc873xx_enable_ide();
229	}
230}
231
232static inline void __init
233cia_cab_init_pci(void)
234{
235	cia_init_pci();
236	cabriolet_enable_ide();
237}
238
239/*
240 * The PC164 and LX164 have 19 PCI interrupts, four from each of the four
241 * PCI slots, the SIO, PCI/IDE, and USB.
242 * 
243 * Each of the interrupts can be individually masked. This is
244 * accomplished by setting the appropriate bit in the mask register.
245 * A bit is set by writing a "1" to the desired position in the mask
246 * register and cleared by writing a "0". There are 3 mask registers
247 * located at ISA address 804h, 805h and 806h.
248 * 
249 * An I/O read at ISA address 804h, 805h, 806h will return the
250 * state of the 11 PCI interrupts and not the state of the MASKED
251 * interrupts.
252 * 
253 * Note: A write to I/O 804h, 805h, and 806h the mask register will be
254 * updated.
255 * 
256 * 
257 * 				ISA DATA<7:0>
258 * ISA     +--------------------------------------------------------------+
259 * ADDRESS |   7   |   6   |   5   |   4   |   3   |   2  |   1   |   0   |
260 *         +==============================================================+
261 * 0x804   | INTB0 |  USB  |  IDE  |  SIO  | INTA3 |INTA2 | INTA1 | INTA0 |
262 *         +--------------------------------------------------------------+
263 * 0x805   | INTD0 | INTC3 | INTC2 | INTC1 | INTC0 |INTB3 | INTB2 | INTB1 |
264 *         +--------------------------------------------------------------+
265 * 0x806   | Rsrv  | Rsrv  | Rsrv  | Rsrv  | Rsrv  |INTD3 | INTD2 | INTD1 |
266 *         +--------------------------------------------------------------+
267 *         * Rsrv = reserved bits
268 *         Note: The mask register is write-only.
269 * 
270 * IdSel	
271 *   5	 32 bit PCI option slot 2
272 *   6	 64 bit PCI option slot 0
273 *   7	 64 bit PCI option slot 1
274 *   8	 Saturn I/O
275 *   9	 32 bit PCI option slot 3
276 *  10	 USB
277 *  11	 IDE
278 * 
279 */
280
281static inline int
282alphapc164_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
283{
284	static char irq_tab[7][5] = {
285		/*INT   INTA  INTB   INTC   INTD */
286		{ 16+2, 16+2, 16+9,  16+13, 16+17}, /* IdSel  5, slot 2, J20 */
287		{ 16+0, 16+0, 16+7,  16+11, 16+15}, /* IdSel  6, slot 0, J29 */
288		{ 16+1, 16+1, 16+8,  16+12, 16+16}, /* IdSel  7, slot 1, J26 */
289		{   -1,   -1,   -1,    -1,    -1},  /* IdSel  8, SIO */
290		{ 16+3, 16+3, 16+10, 16+14, 16+18}, /* IdSel  9, slot 3, J19 */
291		{ 16+6, 16+6, 16+6,  16+6,  16+6},  /* IdSel 10, USB */
292		{ 16+5, 16+5, 16+5,  16+5,  16+5}   /* IdSel 11, IDE */
293	};
294	const long min_idsel = 5, max_idsel = 11, irqs_per_slot = 5;
295	return COMMON_TABLE_LOOKUP;
296}
297
298static inline void __init
299alphapc164_init_pci(void)
300{
301	cia_init_pci();
302	SMC93x_Init();
303}
304
305
306/*
307 * The System Vector
308 */
309
310#if defined(CONFIG_ALPHA_GENERIC) || defined(CONFIG_ALPHA_LX164)
311struct alpha_machine_vector lx164_mv __initmv = {
312	.vector_name		= "LX164",
313	DO_EV5_MMU,
314	DO_DEFAULT_RTC,
315	DO_PYXIS_IO,
316	.machine_check		= cia_machine_check,
317	.max_isa_dma_address	= ALPHA_MAX_ISA_DMA_ADDRESS,
318	.min_io_address		= DEFAULT_IO_BASE,
319	.min_mem_address	= DEFAULT_MEM_BASE,
320	.pci_dac_offset		= PYXIS_DAC_OFFSET,
321
322	.nr_irqs		= 35,
323	.device_interrupt	= cabriolet_device_interrupt,
324
325	.init_arch		= pyxis_init_arch,
326	.init_irq		= cabriolet_init_irq,
327	.init_rtc		= common_init_rtc,
328	.init_pci		= alphapc164_init_pci,
329	.kill_arch		= cia_kill_arch,
330	.pci_map_irq		= alphapc164_map_irq,
331	.pci_swizzle		= common_swizzle,
332};
333ALIAS_MV(lx164)
334#endif
335
336#if defined(CONFIG_ALPHA_GENERIC) || defined(CONFIG_ALPHA_PC164)
337struct alpha_machine_vector pc164_mv __initmv = {
338	.vector_name		= "PC164",
339	DO_EV5_MMU,
340	DO_DEFAULT_RTC,
341	DO_CIA_IO,
342	.machine_check		= cia_machine_check,
343	.max_isa_dma_address	= ALPHA_MAX_ISA_DMA_ADDRESS,
344	.min_io_address		= DEFAULT_IO_BASE,
345	.min_mem_address	= CIA_DEFAULT_MEM_BASE,
346
347	.nr_irqs		= 35,
348	.device_interrupt	= pc164_device_interrupt,
349
350	.init_arch		= cia_init_arch,
351	.init_irq		= pc164_init_irq,
352	.init_rtc		= common_init_rtc,
353	.init_pci		= alphapc164_init_pci,
354	.kill_arch		= cia_kill_arch,
355	.pci_map_irq		= alphapc164_map_irq,
356	.pci_swizzle		= common_swizzle,
357};
358ALIAS_MV(pc164)
359#endif