core_marvel.c

   1// SPDX-License-Identifier: GPL-2.0
   2/*
   3 *	linux/arch/alpha/kernel/core_marvel.c
   4 *
   5 * Code common to all Marvel based systems.
   6 */
   7
   8#define __EXTERN_INLINE inline
   9#include <asm/io.h>
  10#include <asm/core_marvel.h>
  11#undef __EXTERN_INLINE
  12
  13#include <linux/types.h>
  14#include <linux/pci.h>
  15#include <linux/sched.h>
  16#include <linux/init.h>
  17#include <linux/vmalloc.h>
  18#include <linux/mc146818rtc.h>
  19#include <linux/rtc.h>
  20#include <linux/string.h>
  21#include <linux/module.h>
  22#include <linux/memblock.h>
  23
  24#include <asm/ptrace.h>
  25#include <asm/smp.h>
  26#include <asm/gct.h>
  27#include <asm/tlbflush.h>
  28#include <asm/vga.h>
  29
  30#include "proto.h"
  31#include "pci_impl.h"
  32
  33
  34/*
  35 * Debug helpers
  36 */
  37#define DEBUG_CONFIG 0
  38
  39#if DEBUG_CONFIG
  40# define DBG_CFG(args) printk args
  41#else
  42# define DBG_CFG(args)
  43#endif
  44
  45
  46/*
  47 * Private data
  48 */
  49static struct io7 *io7_head = NULL;
  50
  51
  52/*
  53 * Helper functions
  54 */
  55static unsigned long __attribute__ ((unused))
  56read_ev7_csr(int pe, unsigned long offset)
  57{
  58	ev7_csr *ev7csr = EV7_CSR_KERN(pe, offset);
  59	unsigned long q;
  60
  61	mb();
  62	q = ev7csr->csr;
  63	mb();
  64
  65	return q;
  66}
  67
  68static void __attribute__ ((unused))
  69write_ev7_csr(int pe, unsigned long offset, unsigned long q)
  70{
  71	ev7_csr *ev7csr = EV7_CSR_KERN(pe, offset);
  72
  73	mb();
  74	ev7csr->csr = q;
  75	mb();
  76}
  77
  78static char * __init
  79mk_resource_name(int pe, int port, char *str)
  80{
  81	char tmp[80];
  82	char *name;
  83	size_t sz;
  84
  85	sz = scnprintf(tmp, sizeof(tmp), "PCI %s PE %d PORT %d", str, pe, port);
  86	sz += 1; /* NUL terminator */
  87	name = memblock_alloc_or_panic(sz, SMP_CACHE_BYTES);
  88	strscpy(name, tmp, sz);
  89
  90	return name;
  91}
  92
  93inline struct io7 *
  94marvel_next_io7(struct io7 *prev)
  95{
  96	return (prev ? prev->next : io7_head);
  97}
  98
  99struct io7 *
 100marvel_find_io7(int pe)
 101{
 102	struct io7 *io7;
 103
 104	for (io7 = io7_head; io7 && io7->pe != pe; io7 = io7->next)
 105		continue;
 106
 107	return io7;
 108}
 109
 110static struct io7 * __init
 111alloc_io7(unsigned int pe)
 112{
 113	struct io7 *io7;
 114	struct io7 *insp;
 115	int h;
 116
 117	if (marvel_find_io7(pe)) {
 118		printk(KERN_WARNING "IO7 at PE %d already allocated!\n", pe);
 119		return NULL;
 120	}
 121
 122	io7 = memblock_alloc_or_panic(sizeof(*io7), SMP_CACHE_BYTES);
 123	io7->pe = pe;
 124	raw_spin_lock_init(&io7->irq_lock);
 125
 126	for (h = 0; h < 4; h++) {
 127		io7->ports[h].io7 = io7;
 128		io7->ports[h].port = h;
 129		io7->ports[h].enabled = 0; /* default to disabled */
 130	}
 131
 132	/*
 133	 * Insert in pe sorted order.
 134	 */
 135	if (NULL == io7_head)			/* empty list */
 136		io7_head = io7;	
 137	else if (io7_head->pe > io7->pe) {	/* insert at head */
 138		io7->next = io7_head;
 139		io7_head = io7;
 140	} else {				/* insert at position */
 141		for (insp = io7_head; insp; insp = insp->next) {
 142			if (insp->pe == io7->pe) {
 143				printk(KERN_ERR "Too many IO7s at PE %d\n", 
 144				       io7->pe);
 145				return NULL;
 146			}
 147
 148			if (NULL == insp->next || 
 149			    insp->next->pe > io7->pe) { /* insert here */
 150				io7->next = insp->next;
 151				insp->next = io7;
 152				break;
 153			}
 154		}
 155
 156		if (NULL == insp) { /* couldn't insert ?!? */
 157			printk(KERN_WARNING "Failed to insert IO7 at PE %d "
 158			       " - adding at head of list\n", io7->pe);
 159			io7->next = io7_head;
 160			io7_head = io7;
 161		}
 162	}
 163	
 164	return io7;
 165}
 166
 167void
 168io7_clear_errors(struct io7 *io7)
 169{
 170	io7_port7_csrs *p7csrs;
 171	io7_ioport_csrs *csrs;
 172	int port;
 173
 174
 175	/*
 176	 * First the IO ports.
 177	 */
 178	for (port = 0; port < 4; port++) {
 179		csrs = IO7_CSRS_KERN(io7->pe, port);
 180
 181		csrs->POx_ERR_SUM.csr = -1UL;
 182		csrs->POx_TLB_ERR.csr = -1UL;
 183		csrs->POx_SPL_COMPLT.csr = -1UL;
 184		csrs->POx_TRANS_SUM.csr = -1UL;
 185	}
 186
 187	/*
 188	 * Then the common ones.
 189	 */
 190	p7csrs = IO7_PORT7_CSRS_KERN(io7->pe);
 191
 192	p7csrs->PO7_ERROR_SUM.csr = -1UL;
 193	p7csrs->PO7_UNCRR_SYM.csr = -1UL;
 194	p7csrs->PO7_CRRCT_SYM.csr = -1UL;
 195}
 196
 197
 198/*
 199 * IO7 PCI, PCI/X, AGP configuration.
 200 */
 201static void __init
 202io7_init_hose(struct io7 *io7, int port)
 203{
 204	static int hose_index = 0;
 205
 206	struct pci_controller *hose = alloc_pci_controller();
 207	struct io7_port *io7_port = &io7->ports[port];
 208	io7_ioport_csrs *csrs = IO7_CSRS_KERN(io7->pe, port);
 209	int i;
 210
 211	hose->index = hose_index++;	/* arbitrary */
 212	
 213	/*
 214	 * We don't have an isa or legacy hose, but glibc expects to be
 215	 * able to use the bus == 0 / dev == 0 form of the iobase syscall
 216	 * to determine information about the i/o system. Since XFree86 
 217	 * relies on glibc's determination to tell whether or not to use
 218	 * sparse access, we need to point the pci_isa_hose at a real hose
 219	 * so at least that determination is correct.
 220	 */
 221	if (hose->index == 0)
 222		pci_isa_hose = hose;
 223
 224	io7_port->csrs = csrs;
 225	io7_port->hose = hose;
 226	hose->sysdata = io7_port;
 227
 228	hose->io_space = alloc_resource();
 229	hose->mem_space = alloc_resource();
 230
 231	/*
 232	 * Base addresses for userland consumption. Since these are going
 233	 * to be mapped, they are pure physical addresses.
 234	 */
 235	hose->sparse_mem_base = hose->sparse_io_base = 0;
 236	hose->dense_mem_base = IO7_MEM_PHYS(io7->pe, port);
 237	hose->dense_io_base = IO7_IO_PHYS(io7->pe, port);
 238
 239	/*
 240	 * Base addresses and resource ranges for kernel consumption.
 241	 */
 242	hose->config_space_base = (unsigned long)IO7_CONF_KERN(io7->pe, port);
 243
 244	hose->io_space->start = (unsigned long)IO7_IO_KERN(io7->pe, port);
 245	hose->io_space->end = hose->io_space->start + IO7_IO_SPACE - 1;
 246	hose->io_space->name = mk_resource_name(io7->pe, port, "IO");
 247	hose->io_space->flags = IORESOURCE_IO;
 248
 249	hose->mem_space->start = (unsigned long)IO7_MEM_KERN(io7->pe, port);
 250	hose->mem_space->end = hose->mem_space->start + IO7_MEM_SPACE - 1;
 251	hose->mem_space->name = mk_resource_name(io7->pe, port, "MEM");
 252	hose->mem_space->flags = IORESOURCE_MEM;
 253
 254	if (request_resource(&ioport_resource, hose->io_space) < 0)
 255		printk(KERN_ERR "Failed to request IO on hose %d\n", 
 256		       hose->index);
 257	if (request_resource(&iomem_resource, hose->mem_space) < 0)
 258		printk(KERN_ERR "Failed to request MEM on hose %d\n", 
 259		       hose->index);
 260
 261	/*
 262	 * Save the existing DMA window settings for later restoration.
 263	 */
 264	for (i = 0; i < 4; i++) {
 265		io7_port->saved_wbase[i] = csrs->POx_WBASE[i].csr;
 266		io7_port->saved_wmask[i] = csrs->POx_WMASK[i].csr;
 267		io7_port->saved_tbase[i] = csrs->POx_TBASE[i].csr;
 268	}
 269
 270	/*
 271	 * Set up the PCI to main memory translation windows.
 272	 *
 273	 * Window 0 is scatter-gather 8MB at 8MB
 274	 * Window 1 is direct access 1GB at 2GB
 275	 * Window 2 is scatter-gather (up-to) 1GB at 3GB
 276	 * Window 3 is disabled
 277	 */
 278
 279	/*
 280	 * TBIA before modifying windows.
 281	 */
 282	marvel_pci_tbi(hose, 0, -1);
 283
 284	/*
 285	 * Set up window 0 for scatter-gather 8MB at 8MB.
 286	 */
 287	hose->sg_isa = iommu_arena_new_node(0, hose, 0x00800000, 0x00800000, 0);
 288	hose->sg_isa->align_entry = 8;	/* cache line boundary */
 289	csrs->POx_WBASE[0].csr = 
 290		hose->sg_isa->dma_base | wbase_m_ena | wbase_m_sg;
 291	csrs->POx_WMASK[0].csr = (hose->sg_isa->size - 1) & wbase_m_addr;
 292	csrs->POx_TBASE[0].csr = virt_to_phys(hose->sg_isa->ptes);
 293
 294	/*
 295	 * Set up window 1 for direct-mapped 1GB at 2GB.
 296	 */
 297	csrs->POx_WBASE[1].csr = __direct_map_base | wbase_m_ena;
 298	csrs->POx_WMASK[1].csr = (__direct_map_size - 1) & wbase_m_addr;
 299	csrs->POx_TBASE[1].csr = 0;
 300
 301	/*
 302	 * Set up window 2 for scatter-gather (up-to) 1GB at 3GB.
 303	 */
 304	hose->sg_pci = iommu_arena_new_node(0, hose, 0xc0000000, 0x40000000, 0);
 305	hose->sg_pci->align_entry = 8;	/* cache line boundary */
 306	csrs->POx_WBASE[2].csr = 
 307		hose->sg_pci->dma_base | wbase_m_ena | wbase_m_sg;
 308	csrs->POx_WMASK[2].csr = (hose->sg_pci->size - 1) & wbase_m_addr;
 309	csrs->POx_TBASE[2].csr = virt_to_phys(hose->sg_pci->ptes);
 310
 311	/*
 312	 * Disable window 3.
 313	 */
 314	csrs->POx_WBASE[3].csr = 0;
 315
 316	/*
 317	 * Make sure that the AGP Monster Window is disabled.
 318	 */
 319	csrs->POx_CTRL.csr &= ~(1UL << 61);
 320
 321#if 1
 322	printk("FIXME: disabling master aborts\n");
 323	csrs->POx_MSK_HEI.csr &= ~(3UL << 14);
 324#endif
 325	/*
 326	 * TBIA after modifying windows.
 327	 */
 328	marvel_pci_tbi(hose, 0, -1);
 329}
 330
 331static void __init
 332marvel_init_io7(struct io7 *io7)
 333{
 334	int i;
 335
 336	printk("Initializing IO7 at PID %d\n", io7->pe);
 337
 338	/*
 339	 * Get the Port 7 CSR pointer.
 340	 */
 341	io7->csrs = IO7_PORT7_CSRS_KERN(io7->pe);
 342
 343	/*
 344	 * Init this IO7's hoses.
 345	 */
 346	for (i = 0; i < IO7_NUM_PORTS; i++) {
 347		io7_ioport_csrs *csrs = IO7_CSRS_KERN(io7->pe, i);
 348		if (csrs->POx_CACHE_CTL.csr == 8) {
 349			io7->ports[i].enabled = 1;
 350			io7_init_hose(io7, i);
 351		}
 352	}
 353}
 354
 355static void __init
 356marvel_io7_present(gct6_node *node)
 357{
 358	int pe;
 359
 360	if (node->type != GCT_TYPE_HOSE ||
 361	    node->subtype != GCT_SUBTYPE_IO_PORT_MODULE) 
 362		return;
 363
 364	pe = (node->id >> 8) & 0xff;
 365	printk("Found an IO7 at PID %d\n", pe);
 366
 367	alloc_io7(pe);
 368}
 369
 370static void __init
 371marvel_find_console_vga_hose(void)
 372{
 373#ifdef CONFIG_VGA_HOSE
 374	u64 *pu64 = (u64 *)((u64)hwrpb + hwrpb->ctbt_offset);
 375
 376	if (pu64[7] == 3) {	/* TERM_TYPE == graphics */
 377		struct pci_controller *hose = NULL;
 378		int h = (pu64[30] >> 24) & 0xff; /* TERM_OUT_LOC, hose # */
 379		struct io7 *io7;
 380		int pid, port;
 381
 382		/* FIXME - encoding is going to have to change for Marvel
 383		 *         since hose will be able to overflow a byte...
 384		 *         need to fix this decode when the console 
 385		 *         changes its encoding
 386		 */
 387		printk("console graphics is on hose %d (console)\n", h);
 388
 389		/*
 390		 * The console's hose numbering is:
 391		 *
 392		 *	hose<n:2>: PID
 393		 *	hose<1:0>: PORT
 394		 *
 395		 * We need to find the hose at that pid and port
 396		 */
 397		pid = h >> 2;
 398		port = h & 3;
 399		if ((io7 = marvel_find_io7(pid)))
 400			hose = io7->ports[port].hose;
 401
 402		if (hose) {
 403			printk("Console graphics on hose %d\n", hose->index);
 404			pci_vga_hose = hose;
 405		}
 406	}
 407#endif
 408}
 409
 410gct6_search_struct gct_wanted_node_list[] __initdata = {
 411	{ GCT_TYPE_HOSE, GCT_SUBTYPE_IO_PORT_MODULE, marvel_io7_present },
 412	{ 0, 0, NULL }
 413};
 414
 415/*
 416 * In case the GCT is not complete, let the user specify PIDs with IO7s
 417 * at boot time. Syntax is 'io7=a,b,c,...,n' where a-n are the PIDs (decimal)
 418 * where IO7s are connected
 419 */
 420static int __init
 421marvel_specify_io7(char *str)
 422{
 423	unsigned long pid;
 424	struct io7 *io7;
 425	char *pchar;
 426
 427	do {
 428		pid = simple_strtoul(str, &pchar, 0);
 429		if (pchar != str) {
 430			printk("User-specified IO7 at PID %lu\n", pid);
 431			io7 = alloc_io7(pid);
 432			if (io7) marvel_init_io7(io7);
 433		}
 434
 435		if (pchar == str) pchar++;
 436		str = pchar;
 437	} while(*str);
 438
 439	return 1;
 440}
 441__setup("io7=", marvel_specify_io7);
 442
 443void __init
 444marvel_init_arch(void)
 445{
 446	struct io7 *io7;
 447
 448	/* With multiple PCI busses, we play with I/O as physical addrs.  */
 449	ioport_resource.end = ~0UL;
 450
 451	/* PCI DMA Direct Mapping is 1GB at 2GB.  */
 452	__direct_map_base = 0x80000000;
 453	__direct_map_size = 0x40000000;
 454
 455	/* Parse the config tree.  */
 456	gct6_find_nodes(GCT_NODE_PTR(0), gct_wanted_node_list);
 457
 458	/* Init the io7s.  */
 459	for (io7 = NULL; NULL != (io7 = marvel_next_io7(io7)); ) 
 460		marvel_init_io7(io7);
 461
 462	/* Check for graphic console location (if any).  */
 463	marvel_find_console_vga_hose();
 464}
 465
 466void
 467marvel_kill_arch(int mode)
 468{
 469}
 470
 471
 472/*
 473 * PCI Configuration Space access functions
 474 *
 475 * Configuration space addresses have the following format:
 476 *
 477 * 	|2 2 2 2|1 1 1 1|1 1 1 1|1 1 
 478 * 	|3 2 1 0|9 8 7 6|5 4 3 2|1 0 9 8|7 6 5 4|3 2 1 0
 479 * 	+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
 480 * 	|B|B|B|B|B|B|B|B|D|D|D|D|D|F|F|F|R|R|R|R|R|R|R|R|
 481 * 	+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
 482 *
 483 *	 n:24	reserved for hose base
 484 *	23:16	bus number (8 bits = 128 possible buses)
 485 *	15:11	Device number (5 bits)
 486 *	10:8	function number
 487 *	 7:2	register number
 488 *  
 489 * Notes:
 490 *	IO7 determines whether to use a type 0 or type 1 config cycle
 491 *	based on the bus number. Therefore the bus number must be set 
 492 *	to 0 for the root bus on any hose.
 493 *	
 494 *	The function number selects which function of a multi-function device 
 495 *	(e.g., SCSI and Ethernet).
 496 * 
 497 */
 498
 499static inline unsigned long
 500build_conf_addr(struct pci_controller *hose, u8 bus, 
 501		unsigned int devfn, int where)
 502{
 503	return (hose->config_space_base | (bus << 16) | (devfn << 8) | where);
 504}
 505
 506static unsigned long
 507mk_conf_addr(struct pci_bus *pbus, unsigned int devfn, int where)
 508{
 509	struct pci_controller *hose = pbus->sysdata;
 510	struct io7_port *io7_port;
 511	unsigned long addr = 0;
 512	u8 bus = pbus->number;
 513
 514	if (!hose)
 515		return addr;
 516
 517	/* Check for enabled.  */
 518	io7_port = hose->sysdata;
 519	if (!io7_port->enabled)
 520		return addr;
 521
 522	if (!pbus->parent) { /* No parent means peer PCI bus. */
 523		/* Don't support idsel > 20 on primary bus.  */
 524		if (devfn >= PCI_DEVFN(21, 0))
 525			return addr;
 526		bus = 0;
 527	}
 528
 529	addr = build_conf_addr(hose, bus, devfn, where);
 530
 531	DBG_CFG(("mk_conf_addr: returning pci_addr 0x%lx\n", addr));
 532	return addr;
 533}
 534
 535static int
 536marvel_read_config(struct pci_bus *bus, unsigned int devfn, int where,
 537		   int size, u32 *value)
 538{
 539	unsigned long addr;
 540	
 541	if (0 == (addr = mk_conf_addr(bus, devfn, where)))
 542		return PCIBIOS_DEVICE_NOT_FOUND;
 543
 544	switch(size) {
 545	case 1:	
 546		*value = __kernel_ldbu(*(vucp)addr);
 547		break;
 548	case 2:	
 549		*value = __kernel_ldwu(*(vusp)addr);
 550		break;
 551	case 4:	
 552		*value = *(vuip)addr;
 553		break;
 554	default:
 555		return PCIBIOS_FUNC_NOT_SUPPORTED;
 556	}
 557
 558	return PCIBIOS_SUCCESSFUL;
 559}
 560
 561static int
 562marvel_write_config(struct pci_bus *bus, unsigned int devfn, int where,
 563		    int size, u32 value)
 564{
 565	unsigned long addr;
 566	
 567	if (0 == (addr = mk_conf_addr(bus, devfn, where)))
 568		return PCIBIOS_DEVICE_NOT_FOUND;
 569
 570	switch (size) {
 571	case 1:
 572		__kernel_stb(value, *(vucp)addr);
 573		mb();
 574		__kernel_ldbu(*(vucp)addr);
 575		break;
 576	case 2:
 577		__kernel_stw(value, *(vusp)addr);
 578		mb();
 579		__kernel_ldwu(*(vusp)addr);
 580		break;
 581	case 4:
 582		*(vuip)addr = value;
 583		mb();
 584		*(vuip)addr;
 585		break;
 586	default:
 587		return PCIBIOS_FUNC_NOT_SUPPORTED;
 588	}
 589
 590	return PCIBIOS_SUCCESSFUL;
 591}
 592
 593struct pci_ops marvel_pci_ops =
 594{
 595	.read =		marvel_read_config,
 596	.write = 	marvel_write_config,
 597};
 598
 599
 600/*
 601 * Other PCI helper functions.
 602 */
 603void
 604marvel_pci_tbi(struct pci_controller *hose, dma_addr_t start, dma_addr_t end)
 605{
 606	io7_ioport_csrs *csrs = ((struct io7_port *)hose->sysdata)->csrs;
 607
 608	wmb();
 609	csrs->POx_SG_TBIA.csr = 0;
 610	mb();
 611	csrs->POx_SG_TBIA.csr;
 612}
 613
 614
 615
 616/*
 617 * RTC Support
 618 */
 619struct marvel_rtc_access_info {
 620	unsigned long function;
 621	unsigned long index;
 622	unsigned long data;
 623};
 624
 625static void
 626__marvel_access_rtc(void *info)
 627{
 628	struct marvel_rtc_access_info *rtc_access = info;
 629
 630	register unsigned long __r0 __asm__("$0");
 631	register unsigned long __r16 __asm__("$16") = rtc_access->function;
 632	register unsigned long __r17 __asm__("$17") = rtc_access->index;
 633	register unsigned long __r18 __asm__("$18") = rtc_access->data;
 634	
 635	__asm__ __volatile__(
 636		"call_pal %4 # cserve rtc"
 637		: "=r"(__r16), "=r"(__r17), "=r"(__r18), "=r"(__r0)
 638		: "i"(PAL_cserve), "0"(__r16), "1"(__r17), "2"(__r18)
 639		: "$1", "$22", "$23", "$24", "$25");
 640
 641	rtc_access->data = __r0;
 642}
 643
 644static u8
 645__marvel_rtc_io(u8 b, unsigned long addr, int write)
 646{
 647	static u8 index = 0;
 648
 649	struct marvel_rtc_access_info rtc_access;
 650	u8 ret = 0;
 651
 652	switch(addr) {
 653	case 0x70:					/* RTC_PORT(0) */
 654		if (write) index = b;
 655		ret = index;
 656		break;
 657
 658	case 0x71:					/* RTC_PORT(1) */
 659		rtc_access.index = index;
 660		rtc_access.data = bcd2bin(b);
 661		rtc_access.function = 0x48 + !write;	/* GET/PUT_TOY */
 662
 663		__marvel_access_rtc(&rtc_access);
 664
 665		ret = bin2bcd(rtc_access.data);
 666		break;
 667
 668	default:
 669		printk(KERN_WARNING "Illegal RTC port %lx\n", addr);
 670		break;
 671	}
 672
 673	return ret;
 674}
 675
 676
 677/*
 678 * IO map support.
 679 */
 680void __iomem *
 681marvel_ioremap(unsigned long addr, unsigned long size)
 682{
 683	struct pci_controller *hose;
 684	unsigned long baddr, last;
 685	struct vm_struct *area;
 686	unsigned long vaddr;
 687	unsigned long *ptes;
 688	unsigned long pfn;
 689
 690	/*
 691	 * Adjust the address.
 692	 */ 
 693	FIXUP_MEMADDR_VGA(addr);
 694
 695	/*
 696	 * Find the hose.
 697	 */
 698	for (hose = hose_head; hose; hose = hose->next) {
 699		if ((addr >> 32) == (hose->mem_space->start >> 32))
 700			break; 
 701	}
 702	if (!hose)
 703		return NULL;
 704
 705	/*
 706	 * We have the hose - calculate the bus limits.
 707	 */
 708	baddr = addr - hose->mem_space->start;
 709	last = baddr + size - 1;
 710
 711	/*
 712	 * Is it direct-mapped?
 713	 */
 714	if ((baddr >= __direct_map_base) && 
 715	    ((baddr + size - 1) < __direct_map_base + __direct_map_size)) {
 716		addr = IDENT_ADDR | (baddr - __direct_map_base);
 717		return (void __iomem *) addr;
 718	}
 719
 720	/* 
 721	 * Check the scatter-gather arena.
 722	 */
 723	if (hose->sg_pci &&
 724	    baddr >= (unsigned long)hose->sg_pci->dma_base &&
 725	    last < (unsigned long)hose->sg_pci->dma_base + hose->sg_pci->size) {
 726
 727		/*
 728		 * Adjust the limits (mappings must be page aligned)
 729		 */
 730		baddr -= hose->sg_pci->dma_base;
 731		last -= hose->sg_pci->dma_base;
 732		baddr &= PAGE_MASK;
 733		size = PAGE_ALIGN(last) - baddr;
 734
 735		/*
 736		 * Map it.
 737		 */
 738		area = get_vm_area(size, VM_IOREMAP);
 739		if (!area)
 740			return NULL;
 741
 742		ptes = hose->sg_pci->ptes;
 743		for (vaddr = (unsigned long)area->addr; 
 744		    baddr <= last; 
 745		    baddr += PAGE_SIZE, vaddr += PAGE_SIZE) {
 746			pfn = ptes[baddr >> PAGE_SHIFT];
 747			if (!(pfn & 1)) {
 748				printk("ioremap failed... pte not valid...\n");
 749				vfree(area->addr);
 750				return NULL;
 751			}
 752			pfn >>= 1;	/* make it a true pfn */
 753			
 754			if (__alpha_remap_area_pages(vaddr,
 755						     pfn << PAGE_SHIFT, 
 756						     PAGE_SIZE, 0)) {
 757				printk("FAILED to map...\n");
 758				vfree(area->addr);
 759				return NULL;
 760			}
 761		}
 762
 763		flush_tlb_all();
 764
 765		vaddr = (unsigned long)area->addr + (addr & ~PAGE_MASK);
 766
 767		return (void __iomem *) vaddr;
 768	}
 769
 770	/* Assume it was already a reasonable address */
 771	vaddr = baddr + hose->mem_space->start;
 772	return (void __iomem *) vaddr;
 773}
 774
 775void
 776marvel_iounmap(volatile void __iomem *xaddr)
 777{
 778	unsigned long addr = (unsigned long) xaddr;
 779	if (addr >= VMALLOC_START)
 780		vfree((void *)(PAGE_MASK & addr)); 
 781}
 782
 783int
 784marvel_is_mmio(const volatile void __iomem *xaddr)
 785{
 786	unsigned long addr = (unsigned long) xaddr;
 787
 788	if (addr >= VMALLOC_START)
 789		return 1;
 790	else
 791		return (addr & 0xFF000000UL) == 0;
 792}
 793
 794#define __marvel_is_port_kbd(a)	(((a) == 0x60) || ((a) == 0x64))
 795#define __marvel_is_port_rtc(a)	(((a) == 0x70) || ((a) == 0x71))
 796
 797void __iomem *marvel_ioportmap (unsigned long addr)
 798{
 799	FIXUP_IOADDR_VGA(addr);
 800	return (void __iomem *)addr;
 801}
 802
 803u8
 804marvel_ioread8(const void __iomem *xaddr)
 805{
 806	unsigned long addr = (unsigned long) xaddr;
 807	if (__marvel_is_port_kbd(addr))
 808		return 0;
 809	else if (__marvel_is_port_rtc(addr))
 810		return __marvel_rtc_io(0, addr, 0);
 811	else if (marvel_is_ioaddr(addr))
 812		return __kernel_ldbu(*(vucp)addr);
 813	else
 814		/* this should catch other legacy addresses
 815		   that would normally fail on MARVEL,
 816		   because there really is nothing there...
 817		*/
 818		return ~0;
 819}
 820
 821void
 822marvel_iowrite8(u8 b, void __iomem *xaddr)
 823{
 824	unsigned long addr = (unsigned long) xaddr;
 825	if (__marvel_is_port_kbd(addr))
 826		return;
 827	else if (__marvel_is_port_rtc(addr)) 
 828		__marvel_rtc_io(b, addr, 1);
 829	else if (marvel_is_ioaddr(addr))
 830		__kernel_stb(b, *(vucp)addr);
 831}
 832
 833#ifndef CONFIG_ALPHA_GENERIC
 834EXPORT_SYMBOL(marvel_ioremap);
 835EXPORT_SYMBOL(marvel_iounmap);
 836EXPORT_SYMBOL(marvel_is_mmio);
 837EXPORT_SYMBOL(marvel_ioportmap);
 838EXPORT_SYMBOL(marvel_ioread8);
 839EXPORT_SYMBOL(marvel_iowrite8);
 840#endif
 841
 842/*
 843 * AGP GART Support.
 844 */
 845#include <linux/agp_backend.h>
 846#include <asm/agp_backend.h>
 847#include <linux/slab.h>
 848#include <linux/delay.h>
 849
 850struct marvel_agp_aperture {
 851	struct pci_iommu_arena *arena;
 852	long pg_start;
 853	long pg_count;
 854};
 855
 856static int
 857marvel_agp_setup(alpha_agp_info *agp)
 858{
 859	struct marvel_agp_aperture *aper;
 860
 861	if (!alpha_agpgart_size)
 862		return -ENOMEM;
 863
 864	aper = kmalloc(sizeof(*aper), GFP_KERNEL);
 865	if (aper == NULL) return -ENOMEM;
 866
 867	aper->arena = agp->hose->sg_pci;
 868	aper->pg_count = alpha_agpgart_size / PAGE_SIZE;
 869	aper->pg_start = iommu_reserve(aper->arena, aper->pg_count,
 870				       aper->pg_count - 1);
 871
 872	if (aper->pg_start < 0) {
 873		printk(KERN_ERR "Failed to reserve AGP memory\n");
 874		kfree(aper);
 875		return -ENOMEM;
 876	}
 877
 878	agp->aperture.bus_base = 
 879		aper->arena->dma_base + aper->pg_start * PAGE_SIZE;
 880	agp->aperture.size = aper->pg_count * PAGE_SIZE;
 881	agp->aperture.sysdata = aper;
 882
 883	return 0;
 884}
 885
 886static void
 887marvel_agp_cleanup(alpha_agp_info *agp)
 888{
 889	struct marvel_agp_aperture *aper = agp->aperture.sysdata;
 890	int status;
 891
 892	status = iommu_release(aper->arena, aper->pg_start, aper->pg_count);
 893	if (status == -EBUSY) {
 894		printk(KERN_WARNING
 895		       "Attempted to release bound AGP memory - unbinding\n");
 896		iommu_unbind(aper->arena, aper->pg_start, aper->pg_count);
 897		status = iommu_release(aper->arena, aper->pg_start, 
 898				       aper->pg_count);
 899	}
 900	if (status < 0)
 901		printk(KERN_ERR "Failed to release AGP memory\n");
 902
 903	kfree(aper);
 904	kfree(agp);
 905}
 906
 907static int
 908marvel_agp_configure(alpha_agp_info *agp)
 909{
 910	io7_ioport_csrs *csrs = ((struct io7_port *)agp->hose->sysdata)->csrs;
 911	struct io7 *io7 = ((struct io7_port *)agp->hose->sysdata)->io7;
 912	unsigned int new_rate = 0;
 913	unsigned long agp_pll;
 914
 915	/*
 916	 * Check the requested mode against the PLL setting.
 917	 * The agpgart_be code has not programmed the card yet,
 918	 * so we can still tweak mode here.
 919	 */
 920	agp_pll = io7->csrs->POx_RST[IO7_AGP_PORT].csr;
 921	switch(IO7_PLL_RNGB(agp_pll)) {
 922	case 0x4:				/* 2x only */
 923		/* 
 924		 * The PLL is only programmed for 2x, so adjust the
 925		 * rate to 2x, if necessary.
 926		 */
 927		if (agp->mode.bits.rate != 2) 
 928			new_rate = 2;
 929		break;
 930
 931	case 0x6:				/* 1x / 4x */
 932		/*
 933		 * The PLL is programmed for 1x or 4x.  Don't go faster
 934		 * than requested, so if the requested rate is 2x, use 1x.
 935		 */
 936		if (agp->mode.bits.rate == 2) 
 937			new_rate = 1;
 938		break;
 939
 940	default:				/* ??????? */
 941		/*
 942		 * Don't know what this PLL setting is, take the requested
 943		 * rate, but warn the user.
 944		 */
 945		printk("%s: unknown PLL setting RNGB=%lx (PLL6_CTL=%016lx)\n",
 946		       __func__, IO7_PLL_RNGB(agp_pll), agp_pll);
 947		break;
 948	}
 949
 950	/*
 951	 * Set the new rate, if necessary.
 952	 */
 953	if (new_rate) {
 954		printk("Requested AGP Rate %dX not compatible "
 955		       "with PLL setting - using %dX\n",
 956		       agp->mode.bits.rate,
 957		       new_rate);
 958
 959		agp->mode.bits.rate = new_rate;
 960	}
 961		
 962	printk("Enabling AGP on hose %d: %dX%s RQ %d\n", 
 963	       agp->hose->index, agp->mode.bits.rate, 
 964	       agp->mode.bits.sba ? " - SBA" : "", agp->mode.bits.rq);
 965
 966	csrs->AGP_CMD.csr = agp->mode.lw;
 967
 968	return 0;
 969}
 970
 971static int 
 972marvel_agp_bind_memory(alpha_agp_info *agp, off_t pg_start, struct agp_memory *mem)
 973{
 974	struct marvel_agp_aperture *aper = agp->aperture.sysdata;
 975	return iommu_bind(aper->arena, aper->pg_start + pg_start, 
 976			  mem->page_count, mem->pages);
 977}
 978
 979static int 
 980marvel_agp_unbind_memory(alpha_agp_info *agp, off_t pg_start, struct agp_memory *mem)
 981{
 982	struct marvel_agp_aperture *aper = agp->aperture.sysdata;
 983	return iommu_unbind(aper->arena, aper->pg_start + pg_start,
 984			    mem->page_count);
 985}
 986
 987static unsigned long
 988marvel_agp_translate(alpha_agp_info *agp, dma_addr_t addr)
 989{
 990	struct marvel_agp_aperture *aper = agp->aperture.sysdata;
 991	unsigned long baddr = addr - aper->arena->dma_base;
 992	unsigned long pte;
 993
 994	if (addr < agp->aperture.bus_base ||
 995	    addr >= agp->aperture.bus_base + agp->aperture.size) {
 996		printk("%s: addr out of range\n", __func__);
 997		return -EINVAL;
 998	}
 999
1000	pte = aper->arena->ptes[baddr >> PAGE_SHIFT];
1001	if (!(pte & 1)) {
1002		printk("%s: pte not valid\n", __func__);
1003		return -EINVAL;
1004	} 
1005	return (pte >> 1) << PAGE_SHIFT;
1006}
1007
1008struct alpha_agp_ops marvel_agp_ops =
1009{
1010	.setup		= marvel_agp_setup,
1011	.cleanup	= marvel_agp_cleanup,
1012	.configure	= marvel_agp_configure,
1013	.bind		= marvel_agp_bind_memory,
1014	.unbind		= marvel_agp_unbind_memory,
1015	.translate	= marvel_agp_translate
1016};
1017
1018alpha_agp_info *
1019marvel_agp_info(void)
1020{
1021	struct pci_controller *hose;
1022	io7_ioport_csrs *csrs;
1023	alpha_agp_info *agp;
1024	struct io7 *io7;
1025
1026	/*
1027	 * Find the first IO7 with an AGP card.
1028	 *
1029	 * FIXME -- there should be a better way (we want to be able to
1030	 * specify and what if the agp card is not video???)
1031	 */
1032	hose = NULL;
1033	for (io7 = NULL; (io7 = marvel_next_io7(io7)) != NULL; ) {
1034		struct pci_controller *h;
1035		vuip addr;
1036
1037		if (!io7->ports[IO7_AGP_PORT].enabled)
1038			continue;
1039
1040		h = io7->ports[IO7_AGP_PORT].hose;
1041		addr = (vuip)build_conf_addr(h, 0, PCI_DEVFN(5, 0), 0);
1042
1043		if (*addr != 0xffffffffu) {
1044			hose = h;
1045			break;
1046		}
1047	}
1048
1049	if (!hose || !hose->sg_pci)
1050		return NULL;
1051
1052	printk("MARVEL - using hose %d as AGP\n", hose->index);
1053
1054	/* 
1055	 * Get the csrs from the hose.
1056	 */
1057	csrs = ((struct io7_port *)hose->sysdata)->csrs;
1058
1059	/*
1060	 * Allocate the info structure.
1061	 */
1062	agp = kmalloc(sizeof(*agp), GFP_KERNEL);
1063	if (!agp)
1064		return NULL;
1065
1066	/*
1067	 * Fill it in.
1068	 */
1069	agp->hose = hose;
1070	agp->private = NULL;
1071	agp->ops = &marvel_agp_ops;
1072
1073	/*
1074	 * Aperture - not configured until ops.setup().
1075	 */
1076	agp->aperture.bus_base = 0;
1077	agp->aperture.size = 0;
1078	agp->aperture.sysdata = NULL;
1079
1080	/*
1081	 * Capabilities.
1082	 *
1083	 * NOTE: IO7 reports through AGP_STAT that it can support a read queue
1084	 *       depth of 17 (rq = 0x10). It actually only supports a depth of
1085	 * 	 16 (rq = 0xf).
1086	 */
1087	agp->capability.lw = csrs->AGP_STAT.csr;
1088	agp->capability.bits.rq = 0xf;
1089	
1090	/*
1091	 * Mode.
1092	 */
1093	agp->mode.lw = csrs->AGP_CMD.csr;
1094
1095	return agp;
1096}