core_cia.c

   1// SPDX-License-Identifier: GPL-2.0
   2/*
   3 *	linux/arch/alpha/kernel/core_cia.c
   4 *
   5 * Written by David A Rusling (david.rusling@reo.mts.dec.com).
   6 * December 1995.
   7 *
   8 *	Copyright (C) 1995  David A Rusling
   9 *	Copyright (C) 1997, 1998  Jay Estabrook
  10 *	Copyright (C) 1998, 1999, 2000  Richard Henderson
  11 *
  12 * Code common to all CIA core logic chips.
  13 */
  14
  15#define __EXTERN_INLINE inline
  16#include <asm/io.h>
  17#include <asm/core_cia.h>
  18#undef __EXTERN_INLINE
  19
  20#include <linux/types.h>
  21#include <linux/pci.h>
  22#include <linux/sched.h>
  23#include <linux/init.h>
  24#include <linux/memblock.h>
  25
  26#include <asm/ptrace.h>
  27#include <asm/mce.h>
  28
  29#include "proto.h"
  30#include "pci_impl.h"
  31
  32
  33/*
  34 * NOTE: Herein lie back-to-back mb instructions.  They are magic. 
  35 * One plausible explanation is that the i/o controller does not properly
  36 * handle the system transaction.  Another involves timing.  Ho hum.
  37 */
  38
  39#define DEBUG_CONFIG 0
  40#if DEBUG_CONFIG
  41# define DBGC(args)	printk args
  42#else
  43# define DBGC(args)
  44#endif
  45
  46#define vip	volatile int  *
  47
  48/*
  49 * Given a bus, device, and function number, compute resulting
  50 * configuration space address.  It is therefore not safe to have
  51 * concurrent invocations to configuration space access routines, but
  52 * there really shouldn't be any need for this.
  53 *
  54 * Type 0:
  55 *
  56 *  3 3|3 3 2 2|2 2 2 2|2 2 2 2|1 1 1 1|1 1 1 1|1 1 
  57 *  3 2|1 0 9 8|7 6 5 4|3 2 1 0|9 8 7 6|5 4 3 2|1 0 9 8|7 6 5 4|3 2 1 0
  58 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
  59 * | | |D|D|D|D|D|D|D|D|D|D|D|D|D|D|D|D|D|D|D|D|D|F|F|F|R|R|R|R|R|R|0|0|
  60 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
  61 *
  62 *	31:11	Device select bit.
  63 * 	10:8	Function number
  64 * 	 7:2	Register number
  65 *
  66 * Type 1:
  67 *
  68 *  3 3|3 3 2 2|2 2 2 2|2 2 2 2|1 1 1 1|1 1 1 1|1 1 
  69 *  3 2|1 0 9 8|7 6 5 4|3 2 1 0|9 8 7 6|5 4 3 2|1 0 9 8|7 6 5 4|3 2 1 0
  70 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
  71 * | | | | | | | | | | |B|B|B|B|B|B|B|B|D|D|D|D|D|F|F|F|R|R|R|R|R|R|0|1|
  72 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
  73 *
  74 *	31:24	reserved
  75 *	23:16	bus number (8 bits = 128 possible buses)
  76 *	15:11	Device number (5 bits)
  77 *	10:8	function number
  78 *	 7:2	register number
  79 *  
  80 * Notes:
  81 *	The function number selects which function of a multi-function device 
  82 *	(e.g., SCSI and Ethernet).
  83 * 
  84 *	The register selects a DWORD (32 bit) register offset.  Hence it
  85 *	doesn't get shifted by 2 bits as we want to "drop" the bottom two
  86 *	bits.
  87 */
  88
  89static int
  90mk_conf_addr(struct pci_bus *bus_dev, unsigned int device_fn, int where,
  91	     unsigned long *pci_addr, unsigned char *type1)
  92{
  93	u8 bus = bus_dev->number;
  94
  95	*type1 = (bus != 0);
  96	*pci_addr = (bus << 16) | (device_fn << 8) | where;
  97
  98	DBGC(("mk_conf_addr(bus=%d ,device_fn=0x%x, where=0x%x,"
  99	      " returning address 0x%p\n"
 100	      bus, device_fn, where, *pci_addr));
 101
 102	return 0;
 103}
 104
 105static unsigned int
 106conf_read(unsigned long addr, unsigned char type1)
 107{
 108	unsigned long flags;
 109	int stat0, value;
 110	int cia_cfg = 0;
 111
 112	DBGC(("conf_read(addr=0x%lx, type1=%d) ", addr, type1));
 113	local_irq_save(flags);
 114
 115	/* Reset status register to avoid losing errors.  */
 116	stat0 = *(vip)CIA_IOC_CIA_ERR;
 117	*(vip)CIA_IOC_CIA_ERR = stat0;
 118	mb();
 119	*(vip)CIA_IOC_CIA_ERR; /* re-read to force write */
 120
 121	/* If Type1 access, must set CIA CFG. */
 122	if (type1) {
 123		cia_cfg = *(vip)CIA_IOC_CFG;
 124		*(vip)CIA_IOC_CFG = (cia_cfg & ~3) | 1;
 125		mb();
 126		*(vip)CIA_IOC_CFG;
 127	}
 128
 129	mb();
 130	draina();
 131	mcheck_expected(0) = 1;
 132	mcheck_taken(0) = 0;
 133	mb();
 134
 135	/* Access configuration space.  */
 136	value = *(vip)addr;
 137	mb();
 138	mb();  /* magic */
 139	if (mcheck_taken(0)) {
 140		mcheck_taken(0) = 0;
 141		value = 0xffffffff;
 142		mb();
 143	}
 144	mcheck_expected(0) = 0;
 145	mb();
 146
 147	/* If Type1 access, must reset IOC CFG so normal IO space ops work.  */
 148	if (type1) {
 149		*(vip)CIA_IOC_CFG = cia_cfg;
 150		mb();
 151		*(vip)CIA_IOC_CFG;
 152	}
 153
 154	local_irq_restore(flags);
 155	DBGC(("done\n"));
 156
 157	return value;
 158}
 159
 160static void
 161conf_write(unsigned long addr, unsigned int value, unsigned char type1)
 162{
 163	unsigned long flags;
 164	int stat0, cia_cfg = 0;
 165
 166	DBGC(("conf_write(addr=0x%lx, type1=%d) ", addr, type1));
 167	local_irq_save(flags);
 168
 169	/* Reset status register to avoid losing errors.  */
 170	stat0 = *(vip)CIA_IOC_CIA_ERR;
 171	*(vip)CIA_IOC_CIA_ERR = stat0;
 172	mb();
 173	*(vip)CIA_IOC_CIA_ERR; /* re-read to force write */
 174
 175	/* If Type1 access, must set CIA CFG.  */
 176	if (type1) {
 177		cia_cfg = *(vip)CIA_IOC_CFG;
 178		*(vip)CIA_IOC_CFG = (cia_cfg & ~3) | 1;
 179		mb();
 180		*(vip)CIA_IOC_CFG;
 181	}
 182
 183	mb();
 184	draina();
 185	mcheck_expected(0) = 1;
 186	mcheck_taken(0) = 0;
 187	mb();
 188
 189	/* Access configuration space.  */
 190	*(vip)addr = value;
 191	mb();
 192	*(vip)addr; /* read back to force the write */
 193
 194	mcheck_expected(0) = 0;
 195	mb();
 196
 197	/* If Type1 access, must reset IOC CFG so normal IO space ops work.  */
 198	if (type1) {
 199		*(vip)CIA_IOC_CFG = cia_cfg;
 200		mb();
 201		*(vip)CIA_IOC_CFG;
 202	}
 203
 204	local_irq_restore(flags);
 205	DBGC(("done\n"));
 206}
 207
 208static int 
 209cia_read_config(struct pci_bus *bus, unsigned int devfn, int where, int size,
 210		u32 *value)
 211{
 212	unsigned long addr, pci_addr;
 213	long mask;
 214	unsigned char type1;
 215	int shift;
 216
 217	if (mk_conf_addr(bus, devfn, where, &pci_addr, &type1))
 218		return PCIBIOS_DEVICE_NOT_FOUND;
 219
 220	mask = (size - 1) * 8;
 221	shift = (where & 3) * 8;
 222	addr = (pci_addr << 5) + mask + CIA_CONF;
 223	*value = conf_read(addr, type1) >> (shift);
 224	return PCIBIOS_SUCCESSFUL;
 225}
 226
 227static int 
 228cia_write_config(struct pci_bus *bus, unsigned int devfn, int where, int size,
 229		 u32 value)
 230{
 231	unsigned long addr, pci_addr;
 232	long mask;
 233	unsigned char type1;
 234
 235	if (mk_conf_addr(bus, devfn, where, &pci_addr, &type1))
 236		return PCIBIOS_DEVICE_NOT_FOUND;
 237
 238	mask = (size - 1) * 8;
 239	addr = (pci_addr << 5) + mask + CIA_CONF;
 240	conf_write(addr, value << ((where & 3) * 8), type1);
 241	return PCIBIOS_SUCCESSFUL;
 242}
 243
 244struct pci_ops cia_pci_ops = 
 245{
 246	.read = 	cia_read_config,
 247	.write =	cia_write_config,
 248};
 249
 250/*
 251 * CIA Pass 1 and PYXIS Pass 1 and 2 have a broken scatter-gather tlb.
 252 * It cannot be invalidated.  Rather than hard code the pass numbers,
 253 * actually try the tbia to see if it works.
 254 */
 255
 256void
 257cia_pci_tbi(struct pci_controller *hose, dma_addr_t start, dma_addr_t end)
 258{
 259	wmb();
 260	*(vip)CIA_IOC_PCI_TBIA = 3;	/* Flush all locked and unlocked.  */
 261	mb();
 262	*(vip)CIA_IOC_PCI_TBIA;
 263}
 264
 265/*
 266 * On PYXIS, even if the tbia works, we cannot use it. It effectively locks
 267 * the chip (as well as direct write to the tag registers) if there is a
 268 * SG DMA operation in progress. This is true at least for PYXIS rev. 1,
 269 * so always use the method below.
 270 */
 271/*
 272 * This is the method NT and NetBSD use.
 273 *
 274 * Allocate mappings, and put the chip into DMA loopback mode to read a
 275 * garbage page.  This works by causing TLB misses, causing old entries to
 276 * be purged to make room for the new entries coming in for the garbage page.
 277 */
 278
 279#define CIA_BROKEN_TBIA_BASE	0x30000000
 280#define CIA_BROKEN_TBIA_SIZE	1024
 281
 282/* Always called with interrupts disabled */
 283static void
 284cia_pci_tbi_try2(struct pci_controller *hose,
 285		 dma_addr_t start, dma_addr_t end)
 286{
 287	void __iomem *bus_addr;
 288	int ctrl;
 289
 290	/* Put the chip into PCI loopback mode.  */
 291	mb();
 292	ctrl = *(vip)CIA_IOC_CIA_CTRL;
 293	*(vip)CIA_IOC_CIA_CTRL = ctrl | CIA_CTRL_PCI_LOOP_EN;
 294	mb();
 295	*(vip)CIA_IOC_CIA_CTRL;
 296	mb();
 297
 298	/* Read from PCI dense memory space at TBI_ADDR, skipping 32k on
 299	   each read.  This forces SG TLB misses.  NetBSD claims that the
 300	   TLB entries are not quite LRU, meaning that we need to read more
 301	   times than there are actual tags.  The 2117x docs claim strict
 302	   round-robin.  Oh well, we've come this far...  */
 303	/* Even better - as seen on the PYXIS rev 1 the TLB tags 0-3 can
 304	   be filled by the TLB misses *only once* after being invalidated
 305	   (by tbia or direct write). Next misses won't update them even
 306	   though the lock bits are cleared. Tags 4-7 are "quite LRU" though,
 307	   so use them and read at window 3 base exactly 4 times. Reading
 308	   more sometimes makes the chip crazy.  -ink */
 309
 310	bus_addr = cia_ioremap(CIA_BROKEN_TBIA_BASE, 32768 * 4);
 311
 312	cia_readl(bus_addr + 0x00000);
 313	cia_readl(bus_addr + 0x08000);
 314	cia_readl(bus_addr + 0x10000);
 315	cia_readl(bus_addr + 0x18000);
 316
 317	cia_iounmap(bus_addr);
 318
 319	/* Restore normal PCI operation.  */
 320	mb();
 321	*(vip)CIA_IOC_CIA_CTRL = ctrl;
 322	mb();
 323	*(vip)CIA_IOC_CIA_CTRL;
 324	mb();
 325}
 326
 327static inline void
 328cia_prepare_tbia_workaround(int window)
 329{
 330	unsigned long *ppte, pte;
 331	long i;
 332
 333	/* Use minimal 1K map. */
 334	ppte = memblock_alloc_or_panic(CIA_BROKEN_TBIA_SIZE, 32768);
 335	pte = (virt_to_phys(ppte) >> (PAGE_SHIFT - 1)) | 1;
 336
 337	for (i = 0; i < CIA_BROKEN_TBIA_SIZE / sizeof(unsigned long); ++i)
 338		ppte[i] = pte;
 339
 340	*(vip)CIA_IOC_PCI_Wn_BASE(window) = CIA_BROKEN_TBIA_BASE | 3;
 341	*(vip)CIA_IOC_PCI_Wn_MASK(window)
 342	  = (CIA_BROKEN_TBIA_SIZE*1024 - 1) & 0xfff00000;
 343	*(vip)CIA_IOC_PCI_Tn_BASE(window) = virt_to_phys(ppte) >> 2;
 344}
 345
 346static void __init
 347verify_tb_operation(void)
 348{
 349	static int page[PAGE_SIZE/4]
 350		__attribute__((aligned(PAGE_SIZE)))
 351		__initdata = { 0 };
 352
 353	struct pci_iommu_arena *arena = pci_isa_hose->sg_isa;
 354	int ctrl, addr0, tag0, pte0, data0;
 355	int temp, use_tbia_try2 = 0;
 356	void __iomem *bus_addr;
 357
 358	/* pyxis -- tbia is broken */
 359	if (pci_isa_hose->dense_io_base)
 360		use_tbia_try2 = 1;
 361
 362	/* Put the chip into PCI loopback mode.  */
 363	mb();
 364	ctrl = *(vip)CIA_IOC_CIA_CTRL;
 365	*(vip)CIA_IOC_CIA_CTRL = ctrl | CIA_CTRL_PCI_LOOP_EN;
 366	mb();
 367	*(vip)CIA_IOC_CIA_CTRL;
 368	mb();
 369
 370	/* Write a valid entry directly into the TLB registers.  */
 371
 372	addr0 = arena->dma_base;
 373	tag0 = addr0 | 1;
 374	pte0 = (virt_to_phys(page) >> (PAGE_SHIFT - 1)) | 1;
 375
 376	*(vip)CIA_IOC_TB_TAGn(0) = tag0;
 377	*(vip)CIA_IOC_TB_TAGn(1) = 0;
 378	*(vip)CIA_IOC_TB_TAGn(2) = 0;
 379	*(vip)CIA_IOC_TB_TAGn(3) = 0;
 380	*(vip)CIA_IOC_TB_TAGn(4) = 0;
 381	*(vip)CIA_IOC_TB_TAGn(5) = 0;
 382	*(vip)CIA_IOC_TB_TAGn(6) = 0;
 383	*(vip)CIA_IOC_TB_TAGn(7) = 0;
 384	*(vip)CIA_IOC_TBn_PAGEm(0,0) = pte0;
 385	*(vip)CIA_IOC_TBn_PAGEm(0,1) = 0;
 386	*(vip)CIA_IOC_TBn_PAGEm(0,2) = 0;
 387	*(vip)CIA_IOC_TBn_PAGEm(0,3) = 0;
 388	mb();
 389
 390	/* Get a usable bus address */
 391	bus_addr = cia_ioremap(addr0, 8*PAGE_SIZE);
 392
 393	/* First, verify we can read back what we've written.  If
 394	   this fails, we can't be sure of any of the other testing
 395	   we're going to do, so bail.  */
 396	/* ??? Actually, we could do the work with machine checks.
 397	   By passing this register update test, we pretty much
 398	   guarantee that cia_pci_tbi_try1 works.  If this test
 399	   fails, cia_pci_tbi_try2 might still work.  */
 400
 401	temp = *(vip)CIA_IOC_TB_TAGn(0);
 402	if (temp != tag0) {
 403		printk("pci: failed tb register update test "
 404		       "(tag0 %#x != %#x)\n", temp, tag0);
 405		goto failed;
 406	}
 407	temp = *(vip)CIA_IOC_TB_TAGn(1);
 408	if (temp != 0) {
 409		printk("pci: failed tb register update test "
 410		       "(tag1 %#x != 0)\n", temp);
 411		goto failed;
 412	}
 413	temp = *(vip)CIA_IOC_TBn_PAGEm(0,0);
 414	if (temp != pte0) {
 415		printk("pci: failed tb register update test "
 416		       "(pte0 %#x != %#x)\n", temp, pte0);
 417		goto failed;
 418	}
 419	printk("pci: passed tb register update test\n");
 420
 421	/* Second, verify we can actually do I/O through this entry.  */
 422
 423	data0 = 0xdeadbeef;
 424	page[0] = data0;
 425	mcheck_expected(0) = 1;
 426	mcheck_taken(0) = 0;
 427	mb();
 428	temp = cia_readl(bus_addr);
 429	mb();
 430	mcheck_expected(0) = 0;
 431	mb();
 432	if (mcheck_taken(0)) {
 433		printk("pci: failed sg loopback i/o read test (mcheck)\n");
 434		goto failed;
 435	}
 436	if (temp != data0) {
 437		printk("pci: failed sg loopback i/o read test "
 438		       "(%#x != %#x)\n", temp, data0);
 439		goto failed;
 440	}
 441	printk("pci: passed sg loopback i/o read test\n");
 442
 443	/* Third, try to invalidate the TLB.  */
 444
 445	if (! use_tbia_try2) {
 446		cia_pci_tbi(arena->hose, 0, -1);
 447		temp = *(vip)CIA_IOC_TB_TAGn(0);
 448		if (temp & 1) {
 449			use_tbia_try2 = 1;
 450			printk("pci: failed tbia test; workaround available\n");
 451		} else {
 452			printk("pci: passed tbia test\n");
 453		}
 454	}
 455
 456	/* Fourth, verify the TLB snoops the EV5's caches when
 457	   doing a tlb fill.  */
 458
 459	data0 = 0x5adda15e;
 460	page[0] = data0;
 461	arena->ptes[4] = pte0;
 462	mcheck_expected(0) = 1;
 463	mcheck_taken(0) = 0;
 464	mb();
 465	temp = cia_readl(bus_addr + 4*PAGE_SIZE);
 466	mb();
 467	mcheck_expected(0) = 0;
 468	mb();
 469	if (mcheck_taken(0)) {
 470		printk("pci: failed pte write cache snoop test (mcheck)\n");
 471		goto failed;
 472	}
 473	if (temp != data0) {
 474		printk("pci: failed pte write cache snoop test "
 475		       "(%#x != %#x)\n", temp, data0);
 476		goto failed;
 477	}
 478	printk("pci: passed pte write cache snoop test\n");
 479
 480	/* Fifth, verify that a previously invalid PTE entry gets
 481	   filled from the page table.  */
 482
 483	data0 = 0xabcdef12;
 484	page[0] = data0;
 485	arena->ptes[5] = pte0;
 486	mcheck_expected(0) = 1;
 487	mcheck_taken(0) = 0;
 488	mb();
 489	temp = cia_readl(bus_addr + 5*PAGE_SIZE);
 490	mb();
 491	mcheck_expected(0) = 0;
 492	mb();
 493	if (mcheck_taken(0)) {
 494		printk("pci: failed valid tag invalid pte reload test "
 495		       "(mcheck; workaround available)\n");
 496		/* Work around this bug by aligning new allocations
 497		   on 4 page boundaries.  */
 498		arena->align_entry = 4;
 499	} else if (temp != data0) {
 500		printk("pci: failed valid tag invalid pte reload test "
 501		       "(%#x != %#x)\n", temp, data0);
 502		goto failed;
 503	} else {
 504		printk("pci: passed valid tag invalid pte reload test\n");
 505	}
 506
 507	/* Sixth, verify machine checks are working.  Test invalid
 508	   pte under the same valid tag as we used above.  */
 509
 510	mcheck_expected(0) = 1;
 511	mcheck_taken(0) = 0;
 512	mb();
 513	temp = cia_readl(bus_addr + 6*PAGE_SIZE);
 514	mb();
 515	mcheck_expected(0) = 0;
 516	mb();
 517	printk("pci: %s pci machine check test\n",
 518	       mcheck_taken(0) ? "passed" : "failed");
 519
 520	/* Clean up after the tests.  */
 521	arena->ptes[4] = 0;
 522	arena->ptes[5] = 0;
 523
 524	if (use_tbia_try2) {
 525		alpha_mv.mv_pci_tbi = cia_pci_tbi_try2;
 526
 527		/* Tags 0-3 must be disabled if we use this workaround. */
 528		wmb();
 529		*(vip)CIA_IOC_TB_TAGn(0) = 2;
 530		*(vip)CIA_IOC_TB_TAGn(1) = 2;
 531		*(vip)CIA_IOC_TB_TAGn(2) = 2;
 532		*(vip)CIA_IOC_TB_TAGn(3) = 2;
 533
 534		printk("pci: tbia workaround enabled\n");
 535	}
 536	alpha_mv.mv_pci_tbi(arena->hose, 0, -1);
 537
 538exit:
 539	/* unmap the bus addr */
 540	cia_iounmap(bus_addr);
 541
 542	/* Restore normal PCI operation.  */
 543	mb();
 544	*(vip)CIA_IOC_CIA_CTRL = ctrl;
 545	mb();
 546	*(vip)CIA_IOC_CIA_CTRL;
 547	mb();
 548	return;
 549
 550failed:
 551	printk("pci: disabling sg translation window\n");
 552	*(vip)CIA_IOC_PCI_W0_BASE = 0;
 553	*(vip)CIA_IOC_PCI_W1_BASE = 0;
 554	pci_isa_hose->sg_isa = NULL;
 555	alpha_mv.mv_pci_tbi = NULL;
 556	goto exit;
 557}
 558
 559#if defined(ALPHA_RESTORE_SRM_SETUP)
 560/* Save CIA configuration data as the console had it set up.  */
 561struct 
 562{
 563    unsigned int hae_mem;
 564    unsigned int hae_io;
 565    unsigned int pci_dac_offset;
 566    unsigned int err_mask;
 567    unsigned int cia_ctrl;
 568    unsigned int cia_cnfg;
 569    struct {
 570	unsigned int w_base;
 571	unsigned int w_mask;
 572	unsigned int t_base;
 573    } window[4];
 574} saved_config __attribute((common));
 575
 576static void
 577cia_save_srm_settings(int is_pyxis)
 578{
 579	int i;
 580
 581	/* Save some important registers. */
 582	saved_config.err_mask       = *(vip)CIA_IOC_ERR_MASK;
 583	saved_config.cia_ctrl       = *(vip)CIA_IOC_CIA_CTRL;
 584	saved_config.hae_mem        = *(vip)CIA_IOC_HAE_MEM;
 585	saved_config.hae_io         = *(vip)CIA_IOC_HAE_IO;
 586	saved_config.pci_dac_offset = *(vip)CIA_IOC_PCI_W_DAC;
 587
 588	if (is_pyxis)
 589	    saved_config.cia_cnfg   = *(vip)CIA_IOC_CIA_CNFG;
 590	else
 591	    saved_config.cia_cnfg   = 0;
 592
 593	/* Save DMA windows configuration. */
 594	for (i = 0; i < 4; i++) {
 595	    saved_config.window[i].w_base = *(vip)CIA_IOC_PCI_Wn_BASE(i);
 596	    saved_config.window[i].w_mask = *(vip)CIA_IOC_PCI_Wn_MASK(i);
 597	    saved_config.window[i].t_base = *(vip)CIA_IOC_PCI_Tn_BASE(i);
 598	}
 599	mb();
 600}
 601
 602static void
 603cia_restore_srm_settings(void)
 604{
 605	int i;
 606
 607	for (i = 0; i < 4; i++) {
 608	    *(vip)CIA_IOC_PCI_Wn_BASE(i) = saved_config.window[i].w_base;
 609	    *(vip)CIA_IOC_PCI_Wn_MASK(i) = saved_config.window[i].w_mask;
 610	    *(vip)CIA_IOC_PCI_Tn_BASE(i) = saved_config.window[i].t_base;
 611	}
 612
 613	*(vip)CIA_IOC_HAE_MEM   = saved_config.hae_mem;
 614	*(vip)CIA_IOC_HAE_IO    = saved_config.hae_io;
 615	*(vip)CIA_IOC_PCI_W_DAC = saved_config.pci_dac_offset;	
 616	*(vip)CIA_IOC_ERR_MASK  = saved_config.err_mask;
 617	*(vip)CIA_IOC_CIA_CTRL  = saved_config.cia_ctrl;
 618
 619	if (saved_config.cia_cnfg) /* Must be pyxis. */
 620	    *(vip)CIA_IOC_CIA_CNFG  = saved_config.cia_cnfg;
 621
 622	mb();
 623}
 624#else /* ALPHA_RESTORE_SRM_SETUP */
 625#define cia_save_srm_settings(p)	do {} while (0)
 626#define cia_restore_srm_settings()	do {} while (0)
 627#endif /* ALPHA_RESTORE_SRM_SETUP */
 628
 629
 630static void __init
 631do_init_arch(int is_pyxis)
 632{
 633	struct pci_controller *hose;
 634	int temp, cia_rev, tbia_window;
 635
 636	cia_rev = *(vip)CIA_IOC_CIA_REV & CIA_REV_MASK;
 637	printk("pci: cia revision %d%s\n",
 638	       cia_rev, is_pyxis ? " (pyxis)" : "");
 639
 640	if (alpha_using_srm)
 641		cia_save_srm_settings(is_pyxis);
 642
 643	/* Set up error reporting.  */
 644	temp = *(vip)CIA_IOC_ERR_MASK;
 645	temp &= ~(CIA_ERR_CPU_PE | CIA_ERR_MEM_NEM | CIA_ERR_PA_PTE_INV
 646		  | CIA_ERR_RCVD_MAS_ABT | CIA_ERR_RCVD_TAR_ABT);
 647	*(vip)CIA_IOC_ERR_MASK = temp;
 648
 649	/* Clear all currently pending errors.  */
 650	temp = *(vip)CIA_IOC_CIA_ERR;
 651	*(vip)CIA_IOC_CIA_ERR = temp;
 652
 653	/* Turn on mchecks.  */
 654	temp = *(vip)CIA_IOC_CIA_CTRL;
 655	temp |= CIA_CTRL_FILL_ERR_EN | CIA_CTRL_MCHK_ERR_EN;
 656	*(vip)CIA_IOC_CIA_CTRL = temp;
 657
 658	/* Clear the CFG register, which gets used for PCI config space
 659	   accesses.  That is the way we want to use it, and we do not
 660	   want to depend on what ARC or SRM might have left behind.  */
 661	*(vip)CIA_IOC_CFG = 0;
 662 
 663	/* Zero the HAEs.  */
 664	*(vip)CIA_IOC_HAE_MEM = 0;
 665	*(vip)CIA_IOC_HAE_IO = 0;
 666
 667	/* For PYXIS, we always use BWX bus and i/o accesses.  To that end,
 668	   make sure they're enabled on the controller.  At the same time,
 669	   enable the monster window.  */
 670	if (is_pyxis) {
 671		temp = *(vip)CIA_IOC_CIA_CNFG;
 672		temp |= CIA_CNFG_IOA_BWEN | CIA_CNFG_PCI_MWEN;
 673		*(vip)CIA_IOC_CIA_CNFG = temp;
 674	}
 675
 676	/* Synchronize with all previous changes.  */
 677	mb();
 678	*(vip)CIA_IOC_CIA_REV;
 679
 680	/*
 681	 * Create our single hose.
 682	 */
 683
 684	pci_isa_hose = hose = alloc_pci_controller();
 685	hose->io_space = &ioport_resource;
 686	hose->mem_space = &iomem_resource;
 687	hose->index = 0;
 688
 689	if (! is_pyxis) {
 690		struct resource *hae_mem = alloc_resource();
 691		hose->mem_space = hae_mem;
 692
 693		hae_mem->start = 0;
 694		hae_mem->end = CIA_MEM_R1_MASK;
 695		hae_mem->name = pci_hae0_name;
 696		hae_mem->flags = IORESOURCE_MEM;
 697
 698		if (request_resource(&iomem_resource, hae_mem) < 0)
 699			printk(KERN_ERR "Failed to request HAE_MEM\n");
 700
 701		hose->sparse_mem_base = CIA_SPARSE_MEM - IDENT_ADDR;
 702		hose->dense_mem_base = CIA_DENSE_MEM - IDENT_ADDR;
 703		hose->sparse_io_base = CIA_IO - IDENT_ADDR;
 704		hose->dense_io_base = 0;
 705	} else {
 706		hose->sparse_mem_base = 0;
 707		hose->dense_mem_base = CIA_BW_MEM - IDENT_ADDR;
 708		hose->sparse_io_base = 0;
 709		hose->dense_io_base = CIA_BW_IO - IDENT_ADDR;
 710	}
 711
 712	/*
 713	 * Set up the PCI to main memory translation windows.
 714	 *
 715	 * Window 0 is S/G 8MB at 8MB (for isa)
 716	 * Window 1 is S/G 1MB at 768MB (for tbia) (unused for CIA rev 1)
 717	 * Window 2 is direct access 2GB at 2GB
 718	 * Window 3 is DAC access 4GB at 8GB (or S/G for tbia if CIA rev 1)
 719	 *
 720	 * ??? NetBSD hints that page tables must be aligned to 32K,
 721	 * possibly due to a hardware bug.  This is over-aligned
 722	 * from the 8K alignment one would expect for an 8MB window. 
 723	 * No description of what revisions affected.
 724	 */
 725
 726	hose->sg_pci = NULL;
 727	hose->sg_isa = iommu_arena_new(hose, 0x00800000, 0x00800000, 32768);
 728
 729	__direct_map_base = 0x80000000;
 730	__direct_map_size = 0x80000000;
 731
 732	*(vip)CIA_IOC_PCI_W0_BASE = hose->sg_isa->dma_base | 3;
 733	*(vip)CIA_IOC_PCI_W0_MASK = (hose->sg_isa->size - 1) & 0xfff00000;
 734	*(vip)CIA_IOC_PCI_T0_BASE = virt_to_phys(hose->sg_isa->ptes) >> 2;
 735
 736	*(vip)CIA_IOC_PCI_W2_BASE = __direct_map_base | 1;
 737	*(vip)CIA_IOC_PCI_W2_MASK = (__direct_map_size - 1) & 0xfff00000;
 738	*(vip)CIA_IOC_PCI_T2_BASE = 0 >> 2;
 739
 740	/* On PYXIS we have the monster window, selected by bit 40, so
 741	   there is no need for window3 to be enabled.
 742
 743	   On CIA, we don't have true arbitrary addressing -- bits <39:32>
 744	   are compared against W_DAC.  We can, however, directly map 4GB,
 745	   which is better than before.  However, due to assumptions made
 746	   elsewhere, we should not claim that we support DAC unless that
 747	   4GB covers all of physical memory.
 748
 749	   On CIA rev 1, apparently W1 and W2 can't be used for SG. 
 750	   At least, there are reports that it doesn't work for Alcor. 
 751	   In that case, we have no choice but to use W3 for the TBIA 
 752	   workaround, which means we can't use DAC at all. */ 
 753
 754	tbia_window = 1;
 755	if (is_pyxis) {
 756		*(vip)CIA_IOC_PCI_W3_BASE = 0;
 757	} else if (cia_rev == 1) {
 758		*(vip)CIA_IOC_PCI_W1_BASE = 0;
 759		tbia_window = 3;
 760	} else if (max_low_pfn > (0x100000000UL >> PAGE_SHIFT)) {
 761		*(vip)CIA_IOC_PCI_W3_BASE = 0;
 762	} else {
 763		*(vip)CIA_IOC_PCI_W3_BASE = 0x00000000 | 1 | 8;
 764		*(vip)CIA_IOC_PCI_W3_MASK = 0xfff00000;
 765		*(vip)CIA_IOC_PCI_T3_BASE = 0 >> 2;
 766
 767		alpha_mv.pci_dac_offset = 0x200000000UL;
 768		*(vip)CIA_IOC_PCI_W_DAC = alpha_mv.pci_dac_offset >> 32;
 769	}
 770
 771	/* Prepare workaround for apparently broken tbia. */
 772	cia_prepare_tbia_workaround(tbia_window);
 773}
 774
 775void __init
 776cia_init_arch(void)
 777{
 778	do_init_arch(0);
 779}
 780
 781void __init
 782pyxis_init_arch(void)
 783{
 784	/* On pyxis machines we can precisely calculate the
 785	   CPU clock frequency using pyxis real time counter.
 786	   It's especially useful for SX164 with broken RTC.
 787
 788	   Both CPU and chipset are driven by the single 16.666M
 789	   or 16.667M crystal oscillator. PYXIS_RT_COUNT clock is
 790	   66.66 MHz. -ink */
 791
 792	unsigned int cc0, cc1;
 793	unsigned long pyxis_cc;
 794
 795	__asm__ __volatile__ ("rpcc %0" : "=r"(cc0));
 796	pyxis_cc = *(vulp)PYXIS_RT_COUNT;
 797	do { } while(*(vulp)PYXIS_RT_COUNT - pyxis_cc < 4096);
 798	__asm__ __volatile__ ("rpcc %0" : "=r"(cc1));
 799	cc1 -= cc0;
 800	hwrpb->cycle_freq = ((cc1 >> 11) * 100000000UL) / 3;
 801	hwrpb_update_checksum(hwrpb);
 802
 803	do_init_arch(1);
 804}
 805
 806void
 807cia_kill_arch(int mode)
 808{
 809	if (alpha_using_srm)
 810		cia_restore_srm_settings();
 811}
 812
 813void __init
 814cia_init_pci(void)
 815{
 816	/* Must delay this from init_arch, as we need machine checks.  */
 817	verify_tb_operation();
 818	common_init_pci();
 819}
 820
 821static inline void
 822cia_pci_clr_err(void)
 823{
 824	int jd;
 825
 826	jd = *(vip)CIA_IOC_CIA_ERR;
 827	*(vip)CIA_IOC_CIA_ERR = jd;
 828	mb();
 829	*(vip)CIA_IOC_CIA_ERR;		/* re-read to force write.  */
 830}
 831
 832#ifdef CONFIG_VERBOSE_MCHECK
 833static void
 834cia_decode_pci_error(struct el_CIA_sysdata_mcheck *cia, const char *msg)
 835{
 836	static const char * const pci_cmd_desc[16] = {
 837		"Interrupt Acknowledge", "Special Cycle", "I/O Read",
 838		"I/O Write", "Reserved 0x4", "Reserved 0x5", "Memory Read",
 839		"Memory Write", "Reserved 0x8", "Reserved 0x9",
 840		"Configuration Read", "Configuration Write",
 841		"Memory Read Multiple", "Dual Address Cycle",
 842		"Memory Read Line", "Memory Write and Invalidate"
 843	};
 844
 845	if (cia->cia_err & (CIA_ERR_COR_ERR
 846			    | CIA_ERR_UN_COR_ERR
 847			    | CIA_ERR_MEM_NEM
 848			    | CIA_ERR_PA_PTE_INV)) {
 849		static const char * const window_desc[6] = {
 850			"No window active", "Window 0 hit", "Window 1 hit",
 851			"Window 2 hit", "Window 3 hit", "Monster window hit"
 852		};
 853
 854		const char *window;
 855		const char *cmd;
 856		unsigned long addr, tmp;
 857		int lock, dac;
 858	
 859		cmd = pci_cmd_desc[cia->pci_err0 & 0x7];
 860		lock = (cia->pci_err0 >> 4) & 1;
 861		dac = (cia->pci_err0 >> 5) & 1;
 862
 863		tmp = (cia->pci_err0 >> 8) & 0x1F;
 864		tmp = ffs(tmp);
 865		window = window_desc[tmp];
 866
 867		addr = cia->pci_err1;
 868		if (dac) {
 869			tmp = *(vip)CIA_IOC_PCI_W_DAC & 0xFFUL;
 870			addr |= tmp << 32;
 871		}
 872
 873		printk(KERN_CRIT "CIA machine check: %s\n", msg);
 874		printk(KERN_CRIT "  DMA command: %s\n", cmd);
 875		printk(KERN_CRIT "  PCI address: %#010lx\n", addr);
 876		printk(KERN_CRIT "  %s, Lock: %d, DAC: %d\n",
 877		       window, lock, dac);
 878	} else if (cia->cia_err & (CIA_ERR_PERR
 879				   | CIA_ERR_PCI_ADDR_PE
 880				   | CIA_ERR_RCVD_MAS_ABT
 881				   | CIA_ERR_RCVD_TAR_ABT
 882				   | CIA_ERR_IOA_TIMEOUT)) {
 883		static const char * const master_st_desc[16] = {
 884			"Idle", "Drive bus", "Address step cycle",
 885			"Address cycle", "Data cycle", "Last read data cycle",
 886			"Last write data cycle", "Read stop cycle",
 887			"Write stop cycle", "Read turnaround cycle",
 888			"Write turnaround cycle", "Reserved 0xB",
 889			"Reserved 0xC", "Reserved 0xD", "Reserved 0xE",
 890			"Unknown state"
 891		};
 892		static const char * const target_st_desc[16] = {
 893			"Idle", "Busy", "Read data cycle", "Write data cycle",
 894			"Read stop cycle", "Write stop cycle",
 895			"Read turnaround cycle", "Write turnaround cycle",
 896			"Read wait cycle", "Write wait cycle",
 897			"Reserved 0xA", "Reserved 0xB", "Reserved 0xC",
 898			"Reserved 0xD", "Reserved 0xE", "Unknown state"
 899		};
 900
 901		const char *cmd;
 902		const char *master, *target;
 903		unsigned long addr, tmp;
 904		int dac;
 905
 906		master = master_st_desc[(cia->pci_err0 >> 16) & 0xF];
 907		target = target_st_desc[(cia->pci_err0 >> 20) & 0xF];
 908		cmd = pci_cmd_desc[(cia->pci_err0 >> 24) & 0xF];
 909		dac = (cia->pci_err0 >> 28) & 1;
 910
 911		addr = cia->pci_err2;
 912		if (dac) {
 913			tmp = *(volatile int *)CIA_IOC_PCI_W_DAC & 0xFFUL;
 914			addr |= tmp << 32;
 915		}
 916
 917		printk(KERN_CRIT "CIA machine check: %s\n", msg);
 918		printk(KERN_CRIT "  PCI command: %s\n", cmd);
 919		printk(KERN_CRIT "  Master state: %s, Target state: %s\n",
 920		       master, target);
 921		printk(KERN_CRIT "  PCI address: %#010lx, DAC: %d\n",
 922		       addr, dac);
 923	} else {
 924		printk(KERN_CRIT "CIA machine check: %s\n", msg);
 925		printk(KERN_CRIT "  Unknown PCI error\n");
 926		printk(KERN_CRIT "  PCI_ERR0 = %#08lx", cia->pci_err0);
 927		printk(KERN_CRIT "  PCI_ERR1 = %#08lx", cia->pci_err1);
 928		printk(KERN_CRIT "  PCI_ERR2 = %#08lx", cia->pci_err2);
 929	}
 930}
 931
 932static void
 933cia_decode_mem_error(struct el_CIA_sysdata_mcheck *cia, const char *msg)
 934{
 935	unsigned long mem_port_addr;
 936	unsigned long mem_port_mask;
 937	const char *mem_port_cmd;
 938	const char *seq_state;
 939	const char *set_select;
 940	unsigned long tmp;
 941
 942	/* If this is a DMA command, also decode the PCI bits.  */
 943	if ((cia->mem_err1 >> 20) & 1)
 944		cia_decode_pci_error(cia, msg);
 945	else
 946		printk(KERN_CRIT "CIA machine check: %s\n", msg);
 947
 948	mem_port_addr = cia->mem_err0 & 0xfffffff0;
 949	mem_port_addr |= (cia->mem_err1 & 0x83UL) << 32;
 950
 951	mem_port_mask = (cia->mem_err1 >> 12) & 0xF;
 952
 953	tmp = (cia->mem_err1 >> 8) & 0xF;
 954	tmp |= ((cia->mem_err1 >> 20) & 1) << 4;
 955	if ((tmp & 0x1E) == 0x06)
 956		mem_port_cmd = "WRITE BLOCK or WRITE BLOCK LOCK";
 957	else if ((tmp & 0x1C) == 0x08)
 958		mem_port_cmd = "READ MISS or READ MISS MODIFY";
 959	else if (tmp == 0x1C)
 960		mem_port_cmd = "BC VICTIM";
 961	else if ((tmp & 0x1E) == 0x0E)
 962		mem_port_cmd = "READ MISS MODIFY";
 963	else if ((tmp & 0x1C) == 0x18)
 964		mem_port_cmd = "DMA READ or DMA READ MODIFY";
 965	else if ((tmp & 0x1E) == 0x12)
 966		mem_port_cmd = "DMA WRITE";
 967	else
 968		mem_port_cmd = "Unknown";
 969
 970	tmp = (cia->mem_err1 >> 16) & 0xF;
 971	switch (tmp) {
 972	case 0x0:
 973		seq_state = "Idle";
 974		break;
 975	case 0x1:
 976		seq_state = "DMA READ or DMA WRITE";
 977		break;
 978	case 0x2: case 0x3:
 979		seq_state = "READ MISS (or READ MISS MODIFY) with victim";
 980		break;
 981	case 0x4: case 0x5: case 0x6:
 982		seq_state = "READ MISS (or READ MISS MODIFY) with no victim";
 983		break;
 984	case 0x8: case 0x9: case 0xB:
 985		seq_state = "Refresh";
 986		break;
 987	case 0xC:
 988		seq_state = "Idle, waiting for DMA pending read";
 989		break;
 990	case 0xE: case 0xF:
 991		seq_state = "Idle, ras precharge";
 992		break;
 993	default:
 994		seq_state = "Unknown";
 995		break;
 996	}
 997
 998	tmp = (cia->mem_err1 >> 24) & 0x1F;
 999	switch (tmp) {
1000	case 0x00: set_select = "Set 0 selected"; break;
1001	case 0x01: set_select = "Set 1 selected"; break;
1002	case 0x02: set_select = "Set 2 selected"; break;
1003	case 0x03: set_select = "Set 3 selected"; break;
1004	case 0x04: set_select = "Set 4 selected"; break;
1005	case 0x05: set_select = "Set 5 selected"; break;
1006	case 0x06: set_select = "Set 6 selected"; break;
1007	case 0x07: set_select = "Set 7 selected"; break;
1008	case 0x08: set_select = "Set 8 selected"; break;
1009	case 0x09: set_select = "Set 9 selected"; break;
1010	case 0x0A: set_select = "Set A selected"; break;
1011	case 0x0B: set_select = "Set B selected"; break;
1012	case 0x0C: set_select = "Set C selected"; break;
1013	case 0x0D: set_select = "Set D selected"; break;
1014	case 0x0E: set_select = "Set E selected"; break;
1015	case 0x0F: set_select = "Set F selected"; break;
1016	case 0x10: set_select = "No set selected"; break;
1017	case 0x1F: set_select = "Refresh cycle"; break;
1018	default:   set_select = "Unknown"; break;
1019	}
1020
1021	printk(KERN_CRIT "  Memory port command: %s\n", mem_port_cmd);
1022	printk(KERN_CRIT "  Memory port address: %#010lx, mask: %#lx\n",
1023	       mem_port_addr, mem_port_mask);
1024	printk(KERN_CRIT "  Memory sequencer state: %s\n", seq_state);
1025	printk(KERN_CRIT "  Memory set: %s\n", set_select);
1026}
1027
1028static void
1029cia_decode_ecc_error(struct el_CIA_sysdata_mcheck *cia, const char *msg)
1030{
1031	long syn;
1032	long i;
1033	const char *fmt;
1034
1035	cia_decode_mem_error(cia, msg);
1036
1037	syn = cia->cia_syn & 0xff;
1038	if (syn == (syn & -syn)) {
1039		fmt = KERN_CRIT "  ECC syndrome %#x -- check bit %d\n";
1040		i = ffs(syn) - 1;
1041	} else {
1042		static unsigned char const data_bit[64] = {
1043			0xCE, 0xCB, 0xD3, 0xD5,
1044			0xD6, 0xD9, 0xDA, 0xDC,
1045			0x23, 0x25, 0x26, 0x29,
1046			0x2A, 0x2C, 0x31, 0x34,
1047			0x0E, 0x0B, 0x13, 0x15,
1048			0x16, 0x19, 0x1A, 0x1C,
1049			0xE3, 0xE5, 0xE6, 0xE9,
1050			0xEA, 0xEC, 0xF1, 0xF4,
1051			0x4F, 0x4A, 0x52, 0x54,
1052			0x57, 0x58, 0x5B, 0x5D,
1053			0xA2, 0xA4, 0xA7, 0xA8,
1054			0xAB, 0xAD, 0xB0, 0xB5,
1055			0x8F, 0x8A, 0x92, 0x94,
1056			0x97, 0x98, 0x9B, 0x9D,
1057			0x62, 0x64, 0x67, 0x68,
1058			0x6B, 0x6D, 0x70, 0x75
1059		};
1060
1061		for (i = 0; i < 64; ++i)
1062			if (data_bit[i] == syn)
1063				break;
1064
1065		if (i < 64)
1066			fmt = KERN_CRIT "  ECC syndrome %#x -- data bit %d\n";
1067		else
1068			fmt = KERN_CRIT "  ECC syndrome %#x -- unknown bit\n";
1069	}
1070
1071	printk (fmt, syn, i);
1072}
1073
1074static void
1075cia_decode_parity_error(struct el_CIA_sysdata_mcheck *cia)
1076{
1077	static const char * const cmd_desc[16] = {
1078		"NOP", "LOCK", "FETCH", "FETCH_M", "MEMORY BARRIER",
1079		"SET DIRTY", "WRITE BLOCK", "WRITE BLOCK LOCK",
1080		"READ MISS0", "READ MISS1", "READ MISS MOD0",
1081		"READ MISS MOD1", "BCACHE VICTIM", "Spare",
1082		"READ MISS MOD STC0", "READ MISS MOD STC1"
1083	};
1084
1085	unsigned long addr;
1086	unsigned long mask;
1087	const char *cmd;
1088	int par;
1089
1090	addr = cia->cpu_err0 & 0xfffffff0;
1091	addr |= (cia->cpu_err1 & 0x83UL) << 32;
1092	cmd = cmd_desc[(cia->cpu_err1 >> 8) & 0xF];
1093	mask = (cia->cpu_err1 >> 12) & 0xF;
1094	par = (cia->cpu_err1 >> 21) & 1;
1095
1096	printk(KERN_CRIT "CIA machine check: System bus parity error\n");
1097	printk(KERN_CRIT "  Command: %s, Parity bit: %d\n", cmd, par);
1098	printk(KERN_CRIT "  Address: %#010lx, Mask: %#lx\n", addr, mask);
1099}
1100#endif /* CONFIG_VERBOSE_MCHECK */
1101
1102
1103static int
1104cia_decode_mchk(unsigned long la_ptr)
1105{
1106	struct el_common *com;
1107	struct el_CIA_sysdata_mcheck *cia;
1108
1109	com = (void *)la_ptr;
1110	cia = (void *)(la_ptr + com->sys_offset);
1111
1112	if ((cia->cia_err & CIA_ERR_VALID) == 0)
1113		return 0;
1114
1115#ifdef CONFIG_VERBOSE_MCHECK
1116	if (!alpha_verbose_mcheck)
1117		return 1;
1118
1119	switch (ffs(cia->cia_err & 0xfff) - 1) {
1120	case 0: /* CIA_ERR_COR_ERR */
1121		cia_decode_ecc_error(cia, "Corrected ECC error");
1122		break;
1123	case 1: /* CIA_ERR_UN_COR_ERR */
1124		cia_decode_ecc_error(cia, "Uncorrected ECC error");
1125		break;
1126	case 2: /* CIA_ERR_CPU_PE */
1127		cia_decode_parity_error(cia);
1128		break;
1129	case 3: /* CIA_ERR_MEM_NEM */
1130		cia_decode_mem_error(cia, "Access to nonexistent memory");
1131		break;
1132	case 4: /* CIA_ERR_PCI_SERR */
1133		cia_decode_pci_error(cia, "PCI bus system error");
1134		break;
1135	case 5: /* CIA_ERR_PERR */
1136		cia_decode_pci_error(cia, "PCI data parity error");
1137		break;
1138	case 6: /* CIA_ERR_PCI_ADDR_PE */
1139		cia_decode_pci_error(cia, "PCI address parity error");
1140		break;
1141	case 7: /* CIA_ERR_RCVD_MAS_ABT */
1142		cia_decode_pci_error(cia, "PCI master abort");
1143		break;
1144	case 8: /* CIA_ERR_RCVD_TAR_ABT */
1145		cia_decode_pci_error(cia, "PCI target abort");
1146		break;
1147	case 9: /* CIA_ERR_PA_PTE_INV */
1148		cia_decode_pci_error(cia, "PCI invalid PTE");
1149		break;
1150	case 10: /* CIA_ERR_FROM_WRT_ERR */
1151		cia_decode_mem_error(cia, "Write to flash ROM attempted");
1152		break;
1153	case 11: /* CIA_ERR_IOA_TIMEOUT */
1154		cia_decode_pci_error(cia, "I/O timeout");
1155		break;
1156	}
1157
1158	if (cia->cia_err & CIA_ERR_LOST_CORR_ERR)
1159		printk(KERN_CRIT "CIA lost machine check: "
1160		       "Correctable ECC error\n");
1161	if (cia->cia_err & CIA_ERR_LOST_UN_CORR_ERR)
1162		printk(KERN_CRIT "CIA lost machine check: "
1163		       "Uncorrectable ECC error\n");
1164	if (cia->cia_err & CIA_ERR_LOST_CPU_PE)
1165		printk(KERN_CRIT "CIA lost machine check: "
1166		       "System bus parity error\n");
1167	if (cia->cia_err & CIA_ERR_LOST_MEM_NEM)
1168		printk(KERN_CRIT "CIA lost machine check: "
1169		       "Access to nonexistent memory\n");
1170	if (cia->cia_err & CIA_ERR_LOST_PERR)
1171		printk(KERN_CRIT "CIA lost machine check: "
1172		       "PCI data parity error\n");
1173	if (cia->cia_err & CIA_ERR_LOST_PCI_ADDR_PE)
1174		printk(KERN_CRIT "CIA lost machine check: "
1175		       "PCI address parity error\n");
1176	if (cia->cia_err & CIA_ERR_LOST_RCVD_MAS_ABT)
1177		printk(KERN_CRIT "CIA lost machine check: "
1178		       "PCI master abort\n");
1179	if (cia->cia_err & CIA_ERR_LOST_RCVD_TAR_ABT)
1180		printk(KERN_CRIT "CIA lost machine check: "
1181		       "PCI target abort\n");
1182	if (cia->cia_err & CIA_ERR_LOST_PA_PTE_INV)
1183		printk(KERN_CRIT "CIA lost machine check: "
1184		       "PCI invalid PTE\n");
1185	if (cia->cia_err & CIA_ERR_LOST_FROM_WRT_ERR)
1186		printk(KERN_CRIT "CIA lost machine check: "
1187		       "Write to flash ROM attempted\n");
1188	if (cia->cia_err & CIA_ERR_LOST_IOA_TIMEOUT)
1189		printk(KERN_CRIT "CIA lost machine check: "
1190		       "I/O timeout\n");
1191#endif /* CONFIG_VERBOSE_MCHECK */
1192
1193	return 1;
1194}
1195
1196void
1197cia_machine_check(unsigned long vector, unsigned long la_ptr)
1198{
1199	int expected;
1200
1201	/* Clear the error before any reporting.  */
1202	mb();
1203	mb();  /* magic */
1204	draina();
1205	cia_pci_clr_err();
1206	wrmces(rdmces());	/* reset machine check pending flag.  */
1207	mb();
1208
1209	expected = mcheck_expected(0);
1210	if (!expected && vector == 0x660)
1211		expected = cia_decode_mchk(la_ptr);
1212	process_mcheck_info(vector, la_ptr, "CIA", expected);
1213}