dma.h

  1/* SPDX-License-Identifier: GPL-2.0 */
  2/*
  3 * include/asm-alpha/dma.h
  4 *
  5 * This is essentially the same as the i386 DMA stuff, as the AlphaPCs
  6 * use ISA-compatible dma.  The only extension is support for high-page
  7 * registers that allow to set the top 8 bits of a 32-bit DMA address.
  8 * This register should be written last when setting up a DMA address
  9 * as this will also enable DMA across 64 KB boundaries.
 10 */
 11
 12/* $Id: dma.h,v 1.7 1992/12/14 00:29:34 root Exp root $
 13 * linux/include/asm/dma.h: Defines for using and allocating dma channels.
 14 * Written by Hennus Bergman, 1992.
 15 * High DMA channel support & info by Hannu Savolainen
 16 * and John Boyd, Nov. 1992.
 17 */
 18
 19#ifndef _ASM_DMA_H
 20#define _ASM_DMA_H
 21
 22#include <linux/spinlock.h>
 23#include <asm/io.h>
 24
 25#define dma_outb	outb
 26#define dma_inb		inb
 27
 28/*
 29 * NOTES about DMA transfers:
 30 *
 31 *  controller 1: channels 0-3, byte operations, ports 00-1F
 32 *  controller 2: channels 4-7, word operations, ports C0-DF
 33 *
 34 *  - ALL registers are 8 bits only, regardless of transfer size
 35 *  - channel 4 is not used - cascades 1 into 2.
 36 *  - channels 0-3 are byte - addresses/counts are for physical bytes
 37 *  - channels 5-7 are word - addresses/counts are for physical words
 38 *  - transfers must not cross physical 64K (0-3) or 128K (5-7) boundaries
 39 *  - transfer count loaded to registers is 1 less than actual count
 40 *  - controller 2 offsets are all even (2x offsets for controller 1)
 41 *  - page registers for 5-7 don't use data bit 0, represent 128K pages
 42 *  - page registers for 0-3 use bit 0, represent 64K pages
 43 *
 44 * DMA transfers are limited to the lower 16MB of _physical_ memory.  
 45 * Note that addresses loaded into registers must be _physical_ addresses,
 46 * not logical addresses (which may differ if paging is active).
 47 *
 48 *  Address mapping for channels 0-3:
 49 *
 50 *   A23 ... A16 A15 ... A8  A7 ... A0    (Physical addresses)
 51 *    |  ...  |   |  ... |   |  ... |
 52 *    |  ...  |   |  ... |   |  ... |
 53 *    |  ...  |   |  ... |   |  ... |
 54 *   P7  ...  P0  A7 ... A0  A7 ... A0   
 55 * |    Page    | Addr MSB | Addr LSB |   (DMA registers)
 56 *
 57 *  Address mapping for channels 5-7:
 58 *
 59 *   A23 ... A17 A16 A15 ... A9 A8 A7 ... A1 A0    (Physical addresses)
 60 *    |  ...  |   \   \   ... \  \  \  ... \  \
 61 *    |  ...  |    \   \   ... \  \  \  ... \  (not used)
 62 *    |  ...  |     \   \   ... \  \  \  ... \
 63 *   P7  ...  P1 (0) A7 A6  ... A0 A7 A6 ... A0   
 64 * |      Page      |  Addr MSB   |  Addr LSB  |   (DMA registers)
 65 *
 66 * Again, channels 5-7 transfer _physical_ words (16 bits), so addresses
 67 * and counts _must_ be word-aligned (the lowest address bit is _ignored_ at
 68 * the hardware level, so odd-byte transfers aren't possible).
 69 *
 70 * Transfer count (_not # bytes_) is limited to 64K, represented as actual
 71 * count - 1 : 64K => 0xFFFF, 1 => 0x0000.  Thus, count is always 1 or more,
 72 * and up to 128K bytes may be transferred on channels 5-7 in one operation. 
 73 *
 74 */
 75
 76#define MAX_DMA_CHANNELS	8
 77
 78/*
 79  ISA DMA limitations on Alpha platforms,
 80
 81  These may be due to SIO (PCI<->ISA bridge) chipset limitation, or
 82  just a wiring limit.
 83*/
 84
 85/* The maximum address for ISA DMA transfer on RUFFIAN,
 86   due to an hardware SIO limitation, is 16MB.
 87*/
 88#define ALPHA_RUFFIAN_MAX_ISA_DMA_ADDRESS	0x01000000UL
 89
 90/* The maximum address for ISA DMA transfer on SABLE, and some ALCORs,
 91   due to an hardware SIO chip limitation, is 2GB.
 92*/
 93#define ALPHA_SABLE_MAX_ISA_DMA_ADDRESS		0x80000000UL
 94#define ALPHA_ALCOR_MAX_ISA_DMA_ADDRESS		0x80000000UL
 95
 96/*
 97  Maximum address for all the others is the complete 32-bit bus
 98  address space.
 99*/
100#define ALPHA_MAX_ISA_DMA_ADDRESS		0x100000000UL
101
102#ifdef CONFIG_ALPHA_GENERIC
103# define MAX_ISA_DMA_ADDRESS		(alpha_mv.max_isa_dma_address)
104#else
105# if defined(CONFIG_ALPHA_RUFFIAN)
106#  define MAX_ISA_DMA_ADDRESS		ALPHA_RUFFIAN_MAX_ISA_DMA_ADDRESS
107# elif defined(CONFIG_ALPHA_SABLE)
108#  define MAX_ISA_DMA_ADDRESS		ALPHA_SABLE_MAX_ISA_DMA_ADDRESS
109# elif defined(CONFIG_ALPHA_ALCOR)
110#  define MAX_ISA_DMA_ADDRESS		ALPHA_ALCOR_MAX_ISA_DMA_ADDRESS
111# else
112#  define MAX_ISA_DMA_ADDRESS		ALPHA_MAX_ISA_DMA_ADDRESS
113# endif
114#endif
115
116/* If we have the iommu, we don't have any address limitations on DMA.
117   Otherwise (Nautilus, RX164), we have to have 0-16 Mb DMA zone
118   like i386. */
119#define MAX_DMA_ADDRESS		(alpha_mv.mv_pci_tbi ?	\
120				 ~0UL : IDENT_ADDR + 0x01000000)
121
122/* 8237 DMA controllers */
123#define IO_DMA1_BASE	0x00	/* 8 bit slave DMA, channels 0..3 */
124#define IO_DMA2_BASE	0xC0	/* 16 bit master DMA, ch 4(=slave input)..7 */
125
126/* DMA controller registers */
127#define DMA1_CMD_REG		0x08	/* command register (w) */
128#define DMA1_STAT_REG		0x08	/* status register (r) */
129#define DMA1_REQ_REG            0x09    /* request register (w) */
130#define DMA1_MASK_REG		0x0A	/* single-channel mask (w) */
131#define DMA1_MODE_REG		0x0B	/* mode register (w) */
132#define DMA1_CLEAR_FF_REG	0x0C	/* clear pointer flip-flop (w) */
133#define DMA1_TEMP_REG           0x0D    /* Temporary Register (r) */
134#define DMA1_RESET_REG		0x0D	/* Master Clear (w) */
135#define DMA1_CLR_MASK_REG       0x0E    /* Clear Mask */
136#define DMA1_MASK_ALL_REG       0x0F    /* all-channels mask (w) */
137#define DMA1_EXT_MODE_REG	(0x400 | DMA1_MODE_REG)
138
139#define DMA2_CMD_REG		0xD0	/* command register (w) */
140#define DMA2_STAT_REG		0xD0	/* status register (r) */
141#define DMA2_REQ_REG            0xD2    /* request register (w) */
142#define DMA2_MASK_REG		0xD4	/* single-channel mask (w) */
143#define DMA2_MODE_REG		0xD6	/* mode register (w) */
144#define DMA2_CLEAR_FF_REG	0xD8	/* clear pointer flip-flop (w) */
145#define DMA2_TEMP_REG           0xDA    /* Temporary Register (r) */
146#define DMA2_RESET_REG		0xDA	/* Master Clear (w) */
147#define DMA2_CLR_MASK_REG       0xDC    /* Clear Mask */
148#define DMA2_MASK_ALL_REG       0xDE    /* all-channels mask (w) */
149#define DMA2_EXT_MODE_REG	(0x400 | DMA2_MODE_REG)
150
151#define DMA_ADDR_0              0x00    /* DMA address registers */
152#define DMA_ADDR_1              0x02
153#define DMA_ADDR_2              0x04
154#define DMA_ADDR_3              0x06
155#define DMA_ADDR_4              0xC0
156#define DMA_ADDR_5              0xC4
157#define DMA_ADDR_6              0xC8
158#define DMA_ADDR_7              0xCC
159
160#define DMA_CNT_0               0x01    /* DMA count registers */
161#define DMA_CNT_1               0x03
162#define DMA_CNT_2               0x05
163#define DMA_CNT_3               0x07
164#define DMA_CNT_4               0xC2
165#define DMA_CNT_5               0xC6
166#define DMA_CNT_6               0xCA
167#define DMA_CNT_7               0xCE
168
169#define DMA_PAGE_0              0x87    /* DMA page registers */
170#define DMA_PAGE_1              0x83
171#define DMA_PAGE_2              0x81
172#define DMA_PAGE_3              0x82
173#define DMA_PAGE_5              0x8B
174#define DMA_PAGE_6              0x89
175#define DMA_PAGE_7              0x8A
176
177#define DMA_HIPAGE_0		(0x400 | DMA_PAGE_0)
178#define DMA_HIPAGE_1		(0x400 | DMA_PAGE_1)
179#define DMA_HIPAGE_2		(0x400 | DMA_PAGE_2)
180#define DMA_HIPAGE_3		(0x400 | DMA_PAGE_3)
181#define DMA_HIPAGE_4		(0x400 | DMA_PAGE_4)
182#define DMA_HIPAGE_5		(0x400 | DMA_PAGE_5)
183#define DMA_HIPAGE_6		(0x400 | DMA_PAGE_6)
184#define DMA_HIPAGE_7		(0x400 | DMA_PAGE_7)
185
186#define DMA_MODE_READ	0x44	/* I/O to memory, no autoinit, increment, single mode */
187#define DMA_MODE_WRITE	0x48	/* memory to I/O, no autoinit, increment, single mode */
188#define DMA_MODE_CASCADE 0xC0   /* pass thru DREQ->HRQ, DACK<-HLDA only */
189
190#define DMA_AUTOINIT	0x10
191
192extern spinlock_t  dma_spin_lock;
193
194static __inline__ unsigned long claim_dma_lock(void)
195{
196	unsigned long flags;
197	spin_lock_irqsave(&dma_spin_lock, flags);
198	return flags;
199}
200
201static __inline__ void release_dma_lock(unsigned long flags)
202{
203	spin_unlock_irqrestore(&dma_spin_lock, flags);
204}
205
206/* enable/disable a specific DMA channel */
207static __inline__ void enable_dma(unsigned int dmanr)
208{
209	if (dmanr<=3)
210		dma_outb(dmanr,  DMA1_MASK_REG);
211	else
212		dma_outb(dmanr & 3,  DMA2_MASK_REG);
213}
214
215static __inline__ void disable_dma(unsigned int dmanr)
216{
217	if (dmanr<=3)
218		dma_outb(dmanr | 4,  DMA1_MASK_REG);
219	else
220		dma_outb((dmanr & 3) | 4,  DMA2_MASK_REG);
221}
222
223/* Clear the 'DMA Pointer Flip Flop'.
224 * Write 0 for LSB/MSB, 1 for MSB/LSB access.
225 * Use this once to initialize the FF to a known state.
226 * After that, keep track of it. :-)
227 * --- In order to do that, the DMA routines below should ---
228 * --- only be used while interrupts are disabled! ---
229 */
230static __inline__ void clear_dma_ff(unsigned int dmanr)
231{
232	if (dmanr<=3)
233		dma_outb(0,  DMA1_CLEAR_FF_REG);
234	else
235		dma_outb(0,  DMA2_CLEAR_FF_REG);
236}
237
238/* set mode (above) for a specific DMA channel */
239static __inline__ void set_dma_mode(unsigned int dmanr, char mode)
240{
241	if (dmanr<=3)
242		dma_outb(mode | dmanr,  DMA1_MODE_REG);
243	else
244		dma_outb(mode | (dmanr&3),  DMA2_MODE_REG);
245}
246
247/* set extended mode for a specific DMA channel */
248static __inline__ void set_dma_ext_mode(unsigned int dmanr, char ext_mode)
249{
250	if (dmanr<=3)
251		dma_outb(ext_mode | dmanr,  DMA1_EXT_MODE_REG);
252	else
253		dma_outb(ext_mode | (dmanr&3),  DMA2_EXT_MODE_REG);
254}
255
256/* Set only the page register bits of the transfer address.
257 * This is used for successive transfers when we know the contents of
258 * the lower 16 bits of the DMA current address register.
259 */
260static __inline__ void set_dma_page(unsigned int dmanr, unsigned int pagenr)
261{
262	switch(dmanr) {
263		case 0:
264			dma_outb(pagenr, DMA_PAGE_0);
265			dma_outb((pagenr >> 8), DMA_HIPAGE_0);
266			break;
267		case 1:
268			dma_outb(pagenr, DMA_PAGE_1);
269			dma_outb((pagenr >> 8), DMA_HIPAGE_1);
270			break;
271		case 2:
272			dma_outb(pagenr, DMA_PAGE_2);
273			dma_outb((pagenr >> 8), DMA_HIPAGE_2);
274			break;
275		case 3:
276			dma_outb(pagenr, DMA_PAGE_3);
277			dma_outb((pagenr >> 8), DMA_HIPAGE_3);
278			break;
279		case 5:
280			dma_outb(pagenr & 0xfe, DMA_PAGE_5);
281			dma_outb((pagenr >> 8), DMA_HIPAGE_5);
282			break;
283		case 6:
284			dma_outb(pagenr & 0xfe, DMA_PAGE_6);
285			dma_outb((pagenr >> 8), DMA_HIPAGE_6);
286			break;
287		case 7:
288			dma_outb(pagenr & 0xfe, DMA_PAGE_7);
289			dma_outb((pagenr >> 8), DMA_HIPAGE_7);
290			break;
291	}
292}
293
294
295/* Set transfer address & page bits for specific DMA channel.
296 * Assumes dma flipflop is clear.
297 */
298static __inline__ void set_dma_addr(unsigned int dmanr, unsigned int a)
299{
300	if (dmanr <= 3)  {
301	    dma_outb( a & 0xff, ((dmanr&3)<<1) + IO_DMA1_BASE );
302            dma_outb( (a>>8) & 0xff, ((dmanr&3)<<1) + IO_DMA1_BASE );
303	}  else  {
304	    dma_outb( (a>>1) & 0xff, ((dmanr&3)<<2) + IO_DMA2_BASE );
305	    dma_outb( (a>>9) & 0xff, ((dmanr&3)<<2) + IO_DMA2_BASE );
306	}
307	set_dma_page(dmanr, a>>16);	/* set hipage last to enable 32-bit mode */
308}
309
310
311/* Set transfer size (max 64k for DMA1..3, 128k for DMA5..7) for
312 * a specific DMA channel.
313 * You must ensure the parameters are valid.
314 * NOTE: from a manual: "the number of transfers is one more
315 * than the initial word count"! This is taken into account.
316 * Assumes dma flip-flop is clear.
317 * NOTE 2: "count" represents _bytes_ and must be even for channels 5-7.
318 */
319static __inline__ void set_dma_count(unsigned int dmanr, unsigned int count)
320{
321        count--;
322	if (dmanr <= 3)  {
323	    dma_outb( count & 0xff, ((dmanr&3)<<1) + 1 + IO_DMA1_BASE );
324	    dma_outb( (count>>8) & 0xff, ((dmanr&3)<<1) + 1 + IO_DMA1_BASE );
325        } else {
326	    dma_outb( (count>>1) & 0xff, ((dmanr&3)<<2) + 2 + IO_DMA2_BASE );
327	    dma_outb( (count>>9) & 0xff, ((dmanr&3)<<2) + 2 + IO_DMA2_BASE );
328        }
329}
330
331
332/* Get DMA residue count. After a DMA transfer, this
333 * should return zero. Reading this while a DMA transfer is
334 * still in progress will return unpredictable results.
335 * If called before the channel has been used, it may return 1.
336 * Otherwise, it returns the number of _bytes_ left to transfer.
337 *
338 * Assumes DMA flip-flop is clear.
339 */
340static __inline__ int get_dma_residue(unsigned int dmanr)
341{
342	unsigned int io_port = (dmanr<=3)? ((dmanr&3)<<1) + 1 + IO_DMA1_BASE
343					 : ((dmanr&3)<<2) + 2 + IO_DMA2_BASE;
344
345	/* using short to get 16-bit wrap around */
346	unsigned short count;
347
348	count = 1 + dma_inb(io_port);
349	count += dma_inb(io_port) << 8;
350	
351	return (dmanr<=3)? count : (count<<1);
352}
353
354
355/* These are in kernel/dma.c: */
356extern int request_dma(unsigned int dmanr, const char * device_id);	/* reserve a DMA channel */
357extern void free_dma(unsigned int dmanr);	/* release it again */
358#define KERNEL_HAVE_CHECK_DMA
359extern int check_dma(unsigned int dmanr);
360
361#endif /* _ASM_DMA_H */