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intel-multi-link.rst
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linux-6.19.14/Documentation/sound/hd-audio/intel-multi-link.rst
1.. SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) 2.. include:: <isonum.txt> 3 4================================================ 5HDAudio multi-link extensions on Intel platforms 6================================================ 7 8:Copyright: |copy| 2023 Intel Corporation 9 10This file documents the 'multi-link structure' introduced in 2015 with 11the Skylake processor and recently extended in newer Intel platforms 12 13HDaudio existing link mapping (2015 addition in SkyLake) 14======================================================== 15 16External HDAudio codecs are handled with link #0, while iDISP codec 17for HDMI/DisplayPort is handled with link #1. 18 19The only change to the 2015 definitions is the declaration of the 20LCAP.ALT=0x0 - since the ALT bit was previously reserved, this is a 21backwards-compatible change. 22 23LCTL.SPA and LCTL.CPA are automatically set when exiting reset. They 24are only used in existing drivers when the SCF value needs to be 25corrected. 26 27Basic structure for HDaudio codecs 28---------------------------------- 29 30:: 31 32 +-----------+ 33 | ML cap #0 | 34 +-----------+ 35 | ML cap #1 |---+ 36 +-----------+ | 37 | 38 +--> 0x0 +---------------+ LCAP 39 | ALT=0 | 40 +---------------+ 41 | S192 | 42 +---------------+ 43 | S96 | 44 +---------------+ 45 | S48 | 46 +---------------+ 47 | S24 | 48 +---------------+ 49 | S12 | 50 +---------------+ 51 | S6 | 52 +---------------+ 53 54 0x4 +---------------+ LCTL 55 | INTSTS | 56 +---------------+ 57 | CPA | 58 +---------------+ 59 | SPA | 60 +---------------+ 61 | SCF | 62 +---------------+ 63 64 0x8 +---------------+ LOSIDV 65 | L1OSIVD15 | 66 +---------------+ 67 | L1OSIDV.. | 68 +---------------+ 69 | L1OSIDV1 | 70 +---------------+ 71 72 0xC +---------------+ LSDIID 73 | SDIID14 | 74 +---------------+ 75 | SDIID... | 76 +---------------+ 77 | SDIID0 | 78 +---------------+ 79 80SoundWire HDaudio extended link mapping 81======================================= 82 83A SoundWire extended link is identified when LCAP.ALT=1 and 84LEPTR.ID=0. 85 86DMA control uses the existing LOSIDV register. 87 88Changes include additional descriptions for enumeration that were not 89present in earlier generations. 90 91- multi-link synchronization: capabilities in LCAP.LSS and control in LSYNC 92- number of sublinks (manager IP) in LCAP.LSCOUNT 93- power management moved from SHIM to LCTL.SPA bits 94- hand-over to the DSP for access to multi-link registers, SHIM/IP with LCTL.OFLEN 95- mapping of SoundWire codecs to SDI ID bits 96- move of SHIM and Cadence registers to different offsets, with no 97 change in functionality. The LEPTR.PTR value is an offset from the 98 ML address, with a default value of 0x30000. 99 100Extended structure for SoundWire (assuming 4 Manager IP) 101-------------------------------------------------------- 102 103:: 104 105 +-----------+ 106 | ML cap #0 | 107 +-----------+ 108 | ML cap #1 | 109 +-----------+ 110 | ML cap #2 |---+ 111 +-----------+ | 112 | 113 +--> 0x0 +---------------+ LCAP 114 | ALT=1 | 115 +---------------+ 116 | INTC | 117 +---------------+ 118 | OFLS | 119 +---------------+ 120 | LSS | 121 +---------------+ 122 | SLCOUNT=4 |-----------+ 123 +---------------+ | 124 | 125 0x4 +---------------+ LCTL | 126 | INTSTS | | 127 +---------------+ | 128 | CPA (x bits) | | 129 +---------------+ | 130 | SPA (x bits) | | 131 +---------------+ for each sublink x 132 | INTEN | | 133 +---------------+ | 134 | OFLEN | | 135 +---------------+ | 136 | 137 0x8 +---------------+ LOSIDV | 138 | L1OSIVD15 | | 139 +---------------+ | 140 | L1OSIDV.. | | 141 +---------------+ | 142 | L1OSIDV1 | +---+----------------------------------------------------------+ 143 +---------------+ | | 144 v | 145 0xC + 0x2 * x +---------------+ LSDIIDx +---> 0x30000 +-----------------+ 0x00030000 | 146 | SDIID14 | | | SoundWire SHIM | | 147 +---------------+ | | generic | | 148 | SDIID... | | +-----------------+ 0x00030100 | 149 +---------------+ | | SoundWire IP | | 150 | SDIID0 | | +-----------------+ 0x00036000 | 151 +---------------+ | | SoundWire SHIM | | 152 | | vendor-specific | | 153 0x1C +---------------+ LSYNC | +-----------------+ | 154 | CMDSYNC | | v 155 +---------------+ | +-----------------+ 0x00030000 + 0x8000 * x 156 | SYNCGO | | | SoundWire SHIM | 157 +---------------+ | | generic | 158 | SYNCPU | | +-----------------+ 0x00030100 + 0x8000 * x 159 +---------------+ | | SoundWire IP | 160 | SYNPRD | | +-----------------+ 0x00036000 + 0x8000 * x 161 +---------------+ | | SoundWire SHIM | 162 | | vendor-specific | 163 0x20 +---------------+ LEPTR | +-----------------+ 164 | ID = 0 | | 165 +---------------+ | 166 | VER | | 167 +---------------+ | 168 | PTR |------------+ 169 +---------------+ 170 171 172DMIC HDaudio extended link mapping 173================================== 174 175A DMIC extended link is identified when LCAP.ALT=1 and 176LEPTR.ID=0xC1 are set. 177 178DMA control uses the existing LOSIDV register 179 180Changes include additional descriptions for enumeration that were not 181present in earlier generations. 182 183- multi-link synchronization: capabilities in LCAP.LSS and control in LSYNC 184- power management with LCTL.SPA bits 185- hand-over to the DSP for access to multi-link registers, SHIM/IP with LCTL.OFLEN 186 187- move of DMIC registers to different offsets, with no change in 188 functionality. The LEPTR.PTR value is an offset from the ML 189 address, with a default value of 0x10000. 190 191Extended structure for DMIC 192--------------------------- 193 194:: 195 196 +-----------+ 197 | ML cap #0 | 198 +-----------+ 199 | ML cap #1 | 200 +-----------+ 201 | ML cap #2 |---+ 202 +-----------+ | 203 | 204 +--> 0x0 +---------------+ LCAP 205 | ALT=1 | 206 +---------------+ 207 | INTC | 208 +---------------+ 209 | OFLS | 210 +---------------+ 211 | SLCOUNT=1 | 212 +---------------+ 213 214 0x4 +---------------+ LCTL 215 | INTSTS | 216 +---------------+ 217 | CPA | 218 +---------------+ 219 | SPA | 220 +---------------+ 221 | INTEN | 222 +---------------+ 223 | OFLEN | 224 +---------------+ +---> 0x10000 +-----------------+ 0x00010000 225 | | DMIC SHIM | 226 0x8 +---------------+ LOSIDV | | generic | 227 | L1OSIVD15 | | +-----------------+ 0x00010100 228 +---------------+ | | DMIC IP | 229 | L1OSIDV.. | | +-----------------+ 0x00016000 230 +---------------+ | | DMIC SHIM | 231 | L1OSIDV1 | | | vendor-specific | 232 +---------------+ | +-----------------+ 233 | 234 0x20 +---------------+ LEPTR | 235 | ID = 0xC1 | | 236 +---------------+ | 237 | VER | | 238 +---------------+ | 239 | PTR |-----------+ 240 +---------------+ 241 242 243SSP HDaudio extended link mapping 244================================= 245 246A DMIC extended link is identified when LCAP.ALT=1 and 247LEPTR.ID=0xC0 are set. 248 249DMA control uses the existing LOSIDV register 250 251Changes include additional descriptions for enumeration and control that were not 252present in earlier generations: 253- number of sublinks (SSP IP instances) in LCAP.LSCOUNT 254- power management moved from SHIM to LCTL.SPA bits 255- hand-over to the DSP for access to multi-link registers, SHIM/IP 256with LCTL.OFLEN 257- move of SHIM and SSP IP registers to different offsets, with no 258change in functionality. The LEPTR.PTR value is an offset from the ML 259address, with a default value of 0x28000. 260 261Extended structure for SSP (assuming 3 instances of the IP) 262----------------------------------------------------------- 263 264:: 265 266 +-----------+ 267 | ML cap #0 | 268 +-----------+ 269 | ML cap #1 | 270 +-----------+ 271 | ML cap #2 |---+ 272 +-----------+ | 273 | 274 +--> 0x0 +---------------+ LCAP 275 | ALT=1 | 276 +---------------+ 277 | INTC | 278 +---------------+ 279 | OFLS | 280 +---------------+ 281 | SLCOUNT=3 |-------------------------for each sublink x -------------------------+ 282 +---------------+ | 283 | 284 0x4 +---------------+ LCTL | 285 | INTSTS | | 286 +---------------+ | 287 | CPA (x bits) | | 288 +---------------+ | 289 | SPA (x bits) | | 290 +---------------+ | 291 | INTEN | | 292 +---------------+ | 293 | OFLEN | | 294 +---------------+ +---> 0x28000 +-----------------+ 0x00028000 | 295 | | SSP SHIM | | 296 0x8 +---------------+ LOSIDV | | generic | | 297 | L1OSIVD15 | | +-----------------+ 0x00028100 | 298 +---------------+ | | SSP IP | | 299 | L1OSIDV.. | | +-----------------+ 0x00028C00 | 300 +---------------+ | | SSP SHIM | | 301 | L1OSIDV1 | | | vendor-specific | | 302 +---------------+ | +-----------------+ | 303 | v 304 0x20 +---------------+ LEPTR | +-----------------+ 0x00028000 + 0x1000 * x 305 | ID = 0xC0 | | | SSP SHIM | 306 +---------------+ | | generic | 307 | VER | | +-----------------+ 0x00028100 + 0x1000 * x 308 +---------------+ | | SSP IP | 309 | PTR |-----------+ +-----------------+ 0x00028C00 + 0x1000 * x 310 +---------------+ | SSP SHIM | 311 | vendor-specific | 312 +-----------------+
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