renesas,r9a09g057-wdt.yaml

 1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
 2%YAML 1.2
 3---
 4$id: http://devicetree.org/schemas/watchdog/renesas,r9a09g057-wdt.yaml#
 5$schema: http://devicetree.org/meta-schemas/core.yaml#
 6
 7title: Renesas RZ/V2H(P) Watchdog Timer (WDT) Controller
 8
 9maintainers:
10  - Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
11
12properties:
13  compatible:
14    oneOf:
15      - items:
16          - enum:
17              - renesas,r9a09g047-wdt # RZ/G3E
18              - renesas,r9a09g056-wdt # RZ/V2N
19          - const: renesas,r9a09g057-wdt # RZ/V2H(P)
20
21      - items:
22          - const: renesas,r9a09g087-wdt # RZ/N2H
23          - const: renesas,r9a09g077-wdt # RZ/T2H
24
25      - enum:
26          - renesas,r9a09g057-wdt    # RZ/V2H(P)
27          - renesas,r9a09g077-wdt    # RZ/T2H
28
29  reg:
30    minItems: 1
31    maxItems: 2
32
33  clocks:
34    minItems: 1
35    items:
36      - description: Register access clock
37      - description: Main clock
38
39  clock-names:
40    minItems: 1
41    items:
42      - const: pclk
43      - const: oscclk
44
45  power-domains:
46    maxItems: 1
47
48  resets:
49    maxItems: 1
50
51  timeout-sec: true
52
53required:
54  - compatible
55  - reg
56  - clocks
57  - clock-names
58  - power-domains
59
60allOf:
61  - $ref: watchdog.yaml#
62
63  - if:
64      properties:
65        compatible:
66          contains:
67            const: renesas,r9a09g057-wdt
68    then:
69      properties:
70        reg:
71          maxItems: 1
72        clocks:
73          minItems: 2
74        clock-names:
75          minItems: 2
76    else:
77      properties:
78        clocks:
79          maxItems: 1
80        clock-names:
81          maxItems: 1
82        reg:
83          minItems: 2
84        resets: false
85
86additionalProperties: false
87
88examples:
89  - |
90    #include <dt-bindings/clock/renesas,r9a09g057-cpg.h>
91
92    watchdog@11c00400 {
93            compatible = "renesas,r9a09g057-wdt";
94            reg = <0x11c00400 0x400>;
95            clocks = <&cpg CPG_MOD 0x4b>, <&cpg CPG_MOD 0x4c>;
96            clock-names = "pclk", "oscclk";
97            resets = <&cpg 0x75>;
98            power-domains = <&cpg>;
99    };