FILE
mediatek,mtk-wdt.yaml
File preview with syntax highlighting.
linux-6.19.14/Documentation/devicetree/bindings/watchdog/mediatek,mtk-wdt.yaml
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/watchdog/mediatek,mtk-wdt.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: MediaTek SoCs Watchdog timer 8 9maintainers: 10 - Matthias Brugger <matthias.bgg@gmail.com> 11 12description: 13 The watchdog supports a pre-timeout interrupt that fires 14 timeout-sec/2 before the expiry. 15 16allOf: 17 - $ref: watchdog.yaml# 18 19properties: 20 compatible: 21 oneOf: 22 - enum: 23 - mediatek,mt2712-wdt 24 - mediatek,mt6589-wdt 25 - mediatek,mt6735-wdt 26 - mediatek,mt6795-wdt 27 - mediatek,mt7986-wdt 28 - mediatek,mt7988-wdt 29 - mediatek,mt8183-wdt 30 - mediatek,mt8186-wdt 31 - mediatek,mt8188-wdt 32 - mediatek,mt8192-wdt 33 - mediatek,mt8195-wdt 34 - items: 35 - enum: 36 - mediatek,mt2701-wdt 37 - mediatek,mt6572-wdt 38 - mediatek,mt6582-wdt 39 - mediatek,mt6797-wdt 40 - mediatek,mt7622-wdt 41 - mediatek,mt7623-wdt 42 - mediatek,mt7629-wdt 43 - mediatek,mt8173-wdt 44 - mediatek,mt8188-wdt 45 - mediatek,mt8189-wdt 46 - mediatek,mt8365-wdt 47 - mediatek,mt8516-wdt 48 - const: mediatek,mt6589-wdt 49 50 reg: 51 maxItems: 1 52 53 interrupts: 54 items: 55 - description: Watchdog pre-timeout (bark) interrupt 56 57 mediatek,disable-extrst: 58 description: Disable sending output reset signal 59 type: boolean 60 61 mediatek,reset-by-toprgu: 62 description: The Top Reset Generation Unit (TOPRGU) generates reset signals 63 and distributes them to each IP. If present, the watchdog timer will be 64 reset by TOPRGU once system resets. 65 type: boolean 66 67 '#reset-cells': 68 const: 1 69 70required: 71 - compatible 72 - reg 73 74unevaluatedProperties: false 75 76examples: 77 - | 78 #include <dt-bindings/interrupt-controller/arm-gic.h> 79 80 soc { 81 #address-cells = <2>; 82 #size-cells = <2>; 83 84 watchdog: watchdog@10007000 { 85 compatible = "mediatek,mt8183-wdt"; 86 reg = <0 0x10007000 0 0x100>; 87 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_LOW>; 88 mediatek,disable-extrst; 89 timeout-sec = <10>; 90 #reset-cells = <1>; 91 }; 92 };
~/
Read-only file preview.