rockchip,dwc3.yaml

  1# SPDX-License-Identifier: GPL-2.0
  2%YAML 1.2
  3---
  4$id: http://devicetree.org/schemas/usb/rockchip,dwc3.yaml#
  5$schema: http://devicetree.org/meta-schemas/core.yaml#
  6
  7title: Rockchip SuperSpeed DWC3 USB SoC controller
  8
  9maintainers:
 10  - Heiko Stuebner <heiko@sntech.de>
 11
 12description:
 13  The common content of the node is defined in snps,dwc3.yaml.
 14
 15  Phy documentation is provided in the following places.
 16
 17  USB2.0 PHY
 18  Documentation/devicetree/bindings/phy/rockchip,inno-usb2phy.yaml
 19
 20  Type-C PHY
 21  Documentation/devicetree/bindings/phy/rockchip,rk3399-typec-phy.yaml
 22
 23select:
 24  properties:
 25    compatible:
 26      contains:
 27        enum:
 28          - rockchip,rk3328-dwc3
 29          - rockchip,rk3562-dwc3
 30          - rockchip,rk3568-dwc3
 31          - rockchip,rk3576-dwc3
 32          - rockchip,rk3588-dwc3
 33  required:
 34    - compatible
 35
 36properties:
 37  compatible:
 38    items:
 39      - enum:
 40          - rockchip,rk3328-dwc3
 41          - rockchip,rk3562-dwc3
 42          - rockchip,rk3568-dwc3
 43          - rockchip,rk3576-dwc3
 44          - rockchip,rk3588-dwc3
 45      - const: snps,dwc3
 46
 47  reg:
 48    maxItems: 1
 49
 50  interrupts:
 51    maxItems: 1
 52
 53  clocks:
 54    minItems: 3
 55    items:
 56      - description:
 57          Controller reference clock, must to be 24 MHz
 58      - description:
 59          Controller suspend clock, must to be 24 MHz or 32 KHz
 60      - description:
 61          Master/Core clock, must to be >= 62.5 MHz for SS
 62          operation and >= 30MHz for HS operation
 63      - description:
 64          Controller grf clock OR UTMI clock
 65      - description:
 66          PIPE clock
 67
 68  clock-names:
 69    minItems: 3
 70    items:
 71      - const: ref_clk
 72      - const: suspend_clk
 73      - const: bus_clk
 74      - enum:
 75          - grf_clk
 76          - utmi
 77          - pipe
 78      - const: pipe
 79
 80  power-domains:
 81    maxItems: 1
 82
 83  resets:
 84    maxItems: 1
 85
 86  reset-names:
 87    const: usb3-otg
 88
 89unevaluatedProperties: false
 90
 91required:
 92  - compatible
 93  - reg
 94  - interrupts
 95  - clocks
 96  - clock-names
 97
 98allOf:
 99  - $ref: snps,dwc3.yaml#
100  - if:
101      properties:
102        compatible:
103          contains:
104            const: rockchip,rk3328-dwc3
105    then:
106      properties:
107        clocks:
108          minItems: 3
109          maxItems: 4
110        clock-names:
111          minItems: 3
112          items:
113            - const: ref_clk
114            - const: suspend_clk
115            - const: bus_clk
116            - const: grf_clk
117  - if:
118      properties:
119        compatible:
120          contains:
121            const: rockchip,rk3562-dwc3
122    then:
123      properties:
124        clocks:
125          minItems: 4
126          maxItems: 4
127        clock-names:
128          items:
129            - const: ref_clk
130            - const: suspend_clk
131            - const: bus_clk
132            - const: pipe
133  - if:
134      properties:
135        compatible:
136          contains:
137            enum:
138              - rockchip,rk3568-dwc3
139              - rockchip,rk3576-dwc3
140    then:
141      properties:
142        clocks:
143          maxItems: 3
144        clock-names:
145          maxItems: 3
146  - if:
147      properties:
148        compatible:
149          contains:
150            const: rockchip,rk3588-dwc3
151    then:
152      properties:
153        clock-names:
154          minItems: 3
155          items:
156            - const: ref_clk
157            - const: suspend_clk
158            - const: bus_clk
159            - const: utmi
160            - const: pipe
161
162examples:
163  - |
164    #include <dt-bindings/clock/rk3328-cru.h>
165    #include <dt-bindings/interrupt-controller/arm-gic.h>
166
167    bus {
168      #address-cells = <2>;
169      #size-cells = <2>;
170
171      usbdrd3_0: usb@fe800000 {
172        compatible = "rockchip,rk3328-dwc3", "snps,dwc3";
173        reg = <0x0 0xfe800000 0x0 0x100000>;
174        interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
175        clocks = <&cru SCLK_USB3OTG_REF>, <&cru SCLK_USB3OTG_SUSPEND>,
176                 <&cru ACLK_USB3OTG>;
177        clock-names = "ref_clk", "suspend_clk",
178                      "bus_clk", "grf_clk";
179        dr_mode = "otg";
180      };
181    };