nvidia,tegra194-xusb.yaml

  1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
  2%YAML 1.2
  3---
  4$id: http://devicetree.org/schemas/usb/nvidia,tegra194-xusb.yaml#
  5$schema: http://devicetree.org/meta-schemas/core.yaml#
  6
  7title: NVIDIA Tegra194 xHCI controller
  8
  9maintainers:
 10  - Thierry Reding <thierry.reding@gmail.com>
 11  - Jon Hunter <jonathanh@nvidia.com>
 12
 13description: The Tegra xHCI controller supports both USB2 and USB3 interfaces
 14  exposed by the Tegra XUSB pad controller.
 15
 16properties:
 17  compatible:
 18    const: nvidia,tegra194-xusb
 19
 20  reg:
 21    items:
 22      - description: base and length of the xHCI host registers
 23      - description: base and length of the XUSB FPCI registers
 24
 25  reg-names:
 26    items:
 27      - const: hcd
 28      - const: fpci
 29
 30  interrupts:
 31    items:
 32      - description: xHCI host interrupt
 33      - description: mailbox interrupt
 34
 35  clocks:
 36    items:
 37      - description: XUSB host clock
 38      - description: XUSB Falcon source clock
 39      - description: XUSB SuperSpeed clock
 40      - description: XUSB SuperSpeed source clock
 41      - description: XUSB HighSpeed clock source
 42      - description: XUSB FullSpeed clock source
 43      - description: USB PLL
 44      - description: reference clock
 45      - description: I/O PLL
 46
 47  clock-names:
 48    items:
 49      - const: xusb_host
 50      - const: xusb_falcon_src
 51      - const: xusb_ss
 52      - const: xusb_ss_src
 53      - const: xusb_hs_src
 54      - const: xusb_fs_src
 55      - const: pll_u_480m
 56      - const: clk_m
 57      - const: pll_e
 58
 59  interconnects:
 60    items:
 61      - description: read client
 62      - description: write client
 63
 64  interconnect-names:
 65    items:
 66      - const: dma-mem # read
 67      - const: write
 68
 69  iommus:
 70    maxItems: 1
 71
 72  nvidia,xusb-padctl:
 73    $ref: /schemas/types.yaml#/definitions/phandle
 74    description: phandle to the XUSB pad controller that is used to configure
 75      the USB pads used by the XHCI controller
 76
 77  phys:
 78    minItems: 1
 79    maxItems: 8
 80
 81  phy-names:
 82    minItems: 1
 83    maxItems: 8
 84    items:
 85      enum:
 86        - usb2-0
 87        - usb2-1
 88        - usb2-2
 89        - usb2-3
 90        - usb3-0
 91        - usb3-1
 92        - usb3-2
 93        - usb3-3
 94
 95  power-domains:
 96    items:
 97      - description: XUSBC power domain (for Host and USB 2.0)
 98      - description: XUSBA power domain (for SuperSpeed)
 99
100  power-domain-names:
101    items:
102      - const: xusb_host
103      - const: xusb_ss
104
105  dvddio-pex-supply:
106    description: PCIe/USB3 analog logic power supply. Must supply 1.05 V.
107
108  hvddio-pex-supply:
109    description: High-voltage PCIe/USB3 power supply. Must supply 1.8 V.
110
111  avdd-usb-supply:
112    description: USB controller power supply. Must supply 3.3 V.
113
114  avdd-pll-utmip-supply:
115    description: UTMI PLL power supply. Must supply 1.8 V.
116
117  avdd-pll-uerefe-supply:
118    description: PLLE reference PLL power supply. Must supply 1.05 V.
119
120  dvdd-usb-ss-pll-supply:
121    description: PCIe/USB3 PLL power supply. Must supply 1.05 V.
122
123  hvdd-usb-ss-pll-e-supply:
124    description: High-voltage PLLE power supply. Must supply 1.8 V.
125
126allOf:
127  - $ref: usb-xhci.yaml
128
129unevaluatedProperties: false
130
131examples:
132  - |
133    #include <dt-bindings/clock/tegra194-clock.h>
134    #include <dt-bindings/interrupt-controller/arm-gic.h>
135    #include <dt-bindings/memory/tegra194-mc.h>
136    #include <dt-bindings/power/tegra194-powergate.h>
137    #include <dt-bindings/reset/tegra194-reset.h>
138
139    usb@3610000 {
140        compatible = "nvidia,tegra194-xusb";
141        reg = <0x03610000 0x40000>,
142              <0x03600000 0x10000>;
143        reg-names = "hcd", "fpci";
144
145        interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
146                     <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
147
148        clocks = <&bpmp TEGRA194_CLK_XUSB_CORE_HOST>,
149                 <&bpmp TEGRA194_CLK_XUSB_FALCON>,
150                 <&bpmp TEGRA194_CLK_XUSB_CORE_SS>,
151                 <&bpmp TEGRA194_CLK_XUSB_SS>,
152                 <&bpmp TEGRA194_CLK_CLK_M>,
153                 <&bpmp TEGRA194_CLK_XUSB_FS>,
154                 <&bpmp TEGRA194_CLK_UTMIPLL>,
155                 <&bpmp TEGRA194_CLK_CLK_M>,
156                 <&bpmp TEGRA194_CLK_PLLE>;
157        clock-names = "xusb_host", "xusb_falcon_src",
158                      "xusb_ss", "xusb_ss_src", "xusb_hs_src",
159                      "xusb_fs_src", "pll_u_480m", "clk_m",
160                      "pll_e";
161        interconnects = <&mc TEGRA194_MEMORY_CLIENT_XUSB_HOSTR &emc>,
162                        <&mc TEGRA194_MEMORY_CLIENT_XUSB_HOSTW &emc>;
163        interconnect-names = "dma-mem", "write";
164        iommus = <&smmu TEGRA194_SID_XUSB_HOST>;
165
166        power-domains = <&bpmp TEGRA194_POWER_DOMAIN_XUSBC>,
167                        <&bpmp TEGRA194_POWER_DOMAIN_XUSBA>;
168        power-domain-names = "xusb_host", "xusb_ss";
169
170        nvidia,xusb-padctl = <&xusb_padctl>;
171
172        phys = <&phy_usb2_0>, <&phy_usb2_1>, <&phy_usb2_3>, <&phy_usb3_0>,
173               <&phy_usb3_2>, <&phy_usb3_3>;
174        phy-names = "usb2-0", "usb2-1", "usb2-3", "usb3-0", "usb3-2", "usb3-3";
175    };