fsl,imx8mp-dwc3.yaml

  1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
  2# Copyright (c) 2020 NXP
  3%YAML 1.2
  4---
  5$id: http://devicetree.org/schemas/usb/fsl,imx8mp-dwc3.yaml#
  6$schema: http://devicetree.org/meta-schemas/core.yaml#
  7
  8title: NXP iMX8MP Soc USB Controller
  9
 10maintainers:
 11  - Li Jun <jun.li@nxp.com>
 12
 13properties:
 14  compatible:
 15    oneOf:
 16      - items:
 17          - const: fsl,imx95-dwc3
 18          - const: fsl,imx8mp-dwc3
 19      - const: fsl,imx8mp-dwc3
 20
 21  reg:
 22    items:
 23      - description: Address and length of the register set for HSIO Block Control
 24      - description: Address and length of the register set for the wrapper of dwc3 core on the SOC.
 25
 26  "#address-cells":
 27    enum: [ 1, 2 ]
 28
 29  "#size-cells":
 30    enum: [ 1, 2 ]
 31
 32  dma-ranges:
 33    description:
 34      See section 2.3.9 of the DeviceTree Specification.
 35
 36  ranges: true
 37
 38  interrupts:
 39    maxItems: 1
 40    description: The interrupt that is asserted when a wakeup event is
 41      received.
 42
 43  clocks:
 44    description:
 45      A list of phandle and clock-specifier pairs for the clocks
 46      listed in clock-names.
 47    items:
 48      - description: system hsio root clock.
 49      - description: suspend clock, used for usb wakeup logic.
 50
 51  clock-names:
 52    items:
 53      - const: hsio
 54      - const: suspend
 55
 56  fsl,permanently-attached:
 57    type: boolean
 58    description:
 59      Indicates if the device attached to a downstream port is
 60      permanently attached.
 61
 62  fsl,disable-port-power-control:
 63    type: boolean
 64    description:
 65      Indicates whether the host controller implementation includes port
 66      power control. Defines Bit 3 in capability register (HCCPARAMS).
 67
 68  fsl,over-current-active-low:
 69    type: boolean
 70    description:
 71      Over current signal polarity is active low.
 72
 73  fsl,power-active-low:
 74    type: boolean
 75    description:
 76      Power pad (PWR) polarity is active low.
 77
 78  power-domains:
 79    maxItems: 1
 80
 81# Required child node:
 82
 83patternProperties:
 84  "^usb@[0-9a-f]+$":
 85    $ref: snps,dwc3.yaml#
 86
 87required:
 88  - compatible
 89  - reg
 90  - "#address-cells"
 91  - "#size-cells"
 92  - ranges
 93  - clocks
 94  - clock-names
 95  - interrupts
 96  - power-domains
 97
 98allOf:
 99  - if:
100      properties:
101        compatible:
102          const: fsl,imx8mp-dwc3
103    then:
104      required:
105        - dma-ranges
106
107additionalProperties: false
108
109examples:
110  - |
111    #include <dt-bindings/clock/imx8mp-clock.h>
112    #include <dt-bindings/power/imx8mp-power.h>
113    #include <dt-bindings/interrupt-controller/arm-gic.h>
114    usb3_0: usb@32f10100 {
115      compatible = "fsl,imx8mp-dwc3";
116      reg = <0x32f10100 0x8>,
117            <0x381f0000 0x20>;
118      clocks = <&clk IMX8MP_CLK_HSIO_ROOT>,
119               <&clk IMX8MP_CLK_USB_ROOT>;
120      clock-names = "hsio", "suspend";
121      interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
122      power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_USB>;
123      #address-cells = <1>;
124      #size-cells = <1>;
125      dma-ranges = <0x40000000 0x40000000 0xc0000000>;
126      ranges;
127
128      usb@38100000 {
129        compatible = "snps,dwc3";
130        reg = <0x38100000 0x10000>;
131        clocks = <&clk IMX8MP_CLK_HSIO_AXI>,
132                 <&clk IMX8MP_CLK_USB_CORE_REF>,
133                 <&clk IMX8MP_CLK_USB_ROOT>;
134        clock-names = "bus_early", "ref", "suspend";
135        assigned-clocks = <&clk IMX8MP_CLK_HSIO_AXI>;
136        assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_500M>;
137        assigned-clock-rates = <500000000>;
138        interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
139        phys = <&usb3_phy0>, <&usb3_phy0>;
140        phy-names = "usb2-phy", "usb3-phy";
141        snps,dis-u2-freeclk-exists-quirk;
142      };
143    };