dwc3-xilinx.yaml

  1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
  2%YAML 1.2
  3---
  4$id: http://devicetree.org/schemas/usb/dwc3-xilinx.yaml#
  5$schema: http://devicetree.org/meta-schemas/core.yaml#
  6
  7title: Xilinx SuperSpeed DWC3 USB SoC controller
  8
  9maintainers:
 10  - Radhey Shyam Pandey <radhey.shyam.pandey@amd.com>
 11
 12properties:
 13  compatible:
 14    items:
 15      - enum:
 16          - xlnx,zynqmp-dwc3
 17          - xlnx,versal-dwc3
 18  reg:
 19    maxItems: 1
 20
 21  "#address-cells":
 22    enum: [ 1, 2 ]
 23
 24  "#size-cells":
 25    enum: [ 1, 2 ]
 26
 27  ranges: true
 28
 29  dma-coherent: true
 30
 31  power-domains:
 32    description: specifies a phandle to PM domain provider node
 33    maxItems: 1
 34
 35  clocks:
 36    description:
 37      A list of phandle and clock-specifier pairs for the clocks
 38      listed in clock-names.
 39    items:
 40      - description: Master/Core clock, has to be >= 125 MHz
 41          for SS operation and >= 60MHz for HS operation.
 42      - description: Clock source to core during PHY power down.
 43
 44  clock-names:
 45    items:
 46      - const: bus_clk
 47      - const: ref_clk
 48
 49  resets:
 50    minItems: 1
 51    description:
 52      A list of phandles for resets listed in reset-names.
 53
 54    items:
 55      - description: USB core reset
 56      - description: USB hibernation reset
 57      - description: USB APB reset
 58
 59  reset-names:
 60    minItems: 1
 61    items:
 62      - const: usb_crst
 63      - const: usb_hibrst
 64      - const: usb_apbrst
 65
 66  phys:
 67    minItems: 1
 68    maxItems: 2
 69
 70  phy-names:
 71    minItems: 1
 72    maxItems: 2
 73    items:
 74      enum:
 75        - usb2-phy
 76        - usb3-phy
 77
 78  reset-gpios:
 79    description: GPIO used for the reset ulpi-phy
 80    maxItems: 1
 81
 82# Required child node:
 83
 84patternProperties:
 85  "^usb@[0-9a-f]+$":
 86    $ref: snps,dwc3.yaml#
 87
 88required:
 89  - compatible
 90  - reg
 91  - "#address-cells"
 92  - "#size-cells"
 93  - ranges
 94  - power-domains
 95  - clocks
 96  - clock-names
 97  - resets
 98  - reset-names
 99
100allOf:
101  - if:
102      properties:
103        compatible:
104          contains:
105            enum:
106              - xlnx,versal-dwc3
107    then:
108      properties:
109        resets:
110          maxItems: 1
111        reset-names:
112          maxItems: 1
113    else:
114      properties:
115        resets:
116          minItems: 3
117        reset-names:
118          minItems: 3
119
120additionalProperties: false
121
122examples:
123  - |
124    #include <dt-bindings/dma/xlnx-zynqmp-dpdma.h>
125    #include <dt-bindings/power/xlnx-zynqmp-power.h>
126    #include <dt-bindings/reset/xlnx-zynqmp-resets.h>
127    #include <dt-bindings/reset/xlnx-zynqmp-resets.h>
128    #include <dt-bindings/phy/phy.h>
129    axi {
130        #address-cells = <2>;
131        #size-cells = <2>;
132
133        usb@0 {
134            #address-cells = <0x2>;
135            #size-cells = <0x2>;
136            compatible = "xlnx,zynqmp-dwc3";
137            reg = <0x0 0xff9d0000 0x0 0x100>;
138            clocks = <&zynqmp_clk 32>, <&zynqmp_clk 34>;
139            clock-names = "bus_clk", "ref_clk";
140            power-domains = <&zynqmp_firmware PD_USB_0>;
141            resets = <&zynqmp_reset ZYNQMP_RESET_USB1_CORERESET>,
142                     <&zynqmp_reset ZYNQMP_RESET_USB1_HIBERRESET>,
143                     <&zynqmp_reset ZYNQMP_RESET_USB1_APB>;
144            reset-names = "usb_crst", "usb_hibrst", "usb_apbrst";
145            phys = <&psgtr 2 PHY_TYPE_USB3 0 2>;
146            phy-names = "usb3-phy";
147            ranges;
148
149            usb@fe200000 {
150                compatible = "snps,dwc3";
151                reg = <0x0 0xfe200000 0x0 0x40000>;
152                interrupt-names = "host", "otg";
153                interrupts = <0 65 4>, <0 69 4>;
154                dr_mode = "host";
155                dma-coherent;
156            };
157        };
158    };