qcom,sm8650-ufshc.yaml

  1# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
  2%YAML 1.2
  3---
  4$id: http://devicetree.org/schemas/ufs/qcom,sm8650-ufshc.yaml#
  5$schema: http://devicetree.org/meta-schemas/core.yaml#
  6
  7title: Qualcomm SM8650 and Other SoCs UFS Controllers
  8
  9maintainers:
 10  - Bjorn Andersson <bjorn.andersson@linaro.org>
 11
 12# Select only our matches, not all jedec,ufs-2.0
 13select:
 14  properties:
 15    compatible:
 16      contains:
 17        enum:
 18          - qcom,kaanapali-ufshc
 19          - qcom,sm8650-ufshc
 20          - qcom,sm8750-ufshc
 21  required:
 22    - compatible
 23
 24properties:
 25  compatible:
 26    items:
 27      - enum:
 28          - qcom,kaanapali-ufshc
 29          - qcom,sm8650-ufshc
 30          - qcom,sm8750-ufshc
 31      - const: qcom,ufshc
 32      - const: jedec,ufs-2.0
 33
 34  reg:
 35    minItems: 1
 36    maxItems: 2
 37
 38  reg-names:
 39    minItems: 1
 40    items:
 41      - const: std
 42      - const: mcq
 43
 44  clocks:
 45    minItems: 8
 46    maxItems: 8
 47
 48  clock-names:
 49    items:
 50      - const: core_clk
 51      - const: bus_aggr_clk
 52      - const: iface_clk
 53      - const: core_clk_unipro
 54      - const: ref_clk
 55      - const: tx_lane0_sync_clk
 56      - const: rx_lane0_sync_clk
 57      - const: rx_lane1_sync_clk
 58
 59  qcom,ice:
 60    $ref: /schemas/types.yaml#/definitions/phandle
 61    description: phandle to the Inline Crypto Engine node
 62
 63required:
 64  - compatible
 65  - reg
 66
 67allOf:
 68  - $ref: qcom,ufs-common.yaml
 69
 70unevaluatedProperties: false
 71
 72examples:
 73  - |
 74    #include <dt-bindings/clock/qcom,sm8650-gcc.h>
 75    #include <dt-bindings/clock/qcom,sm8650-tcsr.h>
 76    #include <dt-bindings/clock/qcom,rpmh.h>
 77    #include <dt-bindings/gpio/gpio.h>
 78    #include <dt-bindings/interconnect/qcom,icc.h>
 79    #include <dt-bindings/interconnect/qcom,sm8650-rpmh.h>
 80    #include <dt-bindings/interrupt-controller/arm-gic.h>
 81
 82    soc {
 83        #address-cells = <2>;
 84        #size-cells = <2>;
 85
 86        ufshc@1d84000 {
 87            compatible = "qcom,sm8650-ufshc", "qcom,ufshc", "jedec,ufs-2.0";
 88            reg = <0x0 0x01d84000 0x0 0x3000>;
 89
 90            interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH 0>;
 91
 92            clocks = <&gcc GCC_UFS_PHY_AXI_CLK>,
 93                     <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
 94                     <&gcc GCC_UFS_PHY_AHB_CLK>,
 95                     <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
 96                     <&tcsr TCSR_UFS_PAD_CLKREF_EN>,
 97                     <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
 98                     <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
 99                     <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>;
100            clock-names = "core_clk",
101                          "bus_aggr_clk",
102                          "iface_clk",
103                          "core_clk_unipro",
104                          "ref_clk",
105                          "tx_lane0_sync_clk",
106                          "rx_lane0_sync_clk",
107                          "rx_lane1_sync_clk";
108
109            resets = <&gcc GCC_UFS_PHY_BCR>;
110            reset-names = "rst";
111            reset-gpios = <&tlmm 210 GPIO_ACTIVE_LOW>;
112
113            interconnects = <&aggre1_noc MASTER_UFS_MEM QCOM_ICC_TAG_ALWAYS
114                             &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
115                            <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
116                             &config_noc SLAVE_UFS_MEM_CFG QCOM_ICC_TAG_ACTIVE_ONLY>;
117            interconnect-names = "ufs-ddr",
118                         "cpu-ufs";
119
120            power-domains = <&gcc UFS_PHY_GDSC>;
121            required-opps = <&rpmhpd_opp_nom>;
122
123            operating-points-v2 = <&ufs_opp_table>;
124
125            iommus = <&apps_smmu 0x60 0>;
126
127            lanes-per-direction = <2>;
128            qcom,ice = <&ice>;
129
130            phys = <&ufs_mem_phy>;
131            phy-names = "ufsphy";
132
133            #reset-cells = <1>;
134
135            vcc-supply = <&vreg_l7b_2p5>;
136            vcc-max-microamp = <1100000>;
137            vccq-supply = <&vreg_l9b_1p2>;
138            vccq-max-microamp = <1200000>;
139
140            ufs_opp_table: opp-table {
141                compatible = "operating-points-v2";
142
143                opp-100000000 {
144                    opp-hz = /bits/ 64 <100000000>,
145                             /bits/ 64 <0>,
146                             /bits/ 64 <0>,
147                             /bits/ 64 <100000000>,
148                             /bits/ 64 <0>,
149                             /bits/ 64 <0>,
150                             /bits/ 64 <0>,
151                             /bits/ 64 <0>;
152                    required-opps = <&rpmhpd_opp_low_svs>;
153                };
154
155                opp-201500000 {
156                    opp-hz = /bits/ 64 <201500000>,
157                             /bits/ 64 <0>,
158                             /bits/ 64 <0>,
159                             /bits/ 64 <201500000>,
160                             /bits/ 64 <0>,
161                             /bits/ 64 <0>,
162                             /bits/ 64 <0>,
163                             /bits/ 64 <0>;
164                    required-opps = <&rpmhpd_opp_svs>;
165                };
166
167                opp-403000000 {
168                    opp-hz = /bits/ 64 <403000000>,
169                             /bits/ 64 <0>,
170                             /bits/ 64 <0>,
171                             /bits/ 64 <403000000>,
172                             /bits/ 64 <0>,
173                             /bits/ 64 <0>,
174                             /bits/ 64 <0>,
175                             /bits/ 64 <0>;
176                    required-opps = <&rpmhpd_opp_nom>;
177                };
178            };
179        };
180    };